WO2014008697A1 - 浅沟槽隔离制造方法 - Google Patents

浅沟槽隔离制造方法 Download PDF

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Publication number
WO2014008697A1
WO2014008697A1 PCT/CN2012/079693 CN2012079693W WO2014008697A1 WO 2014008697 A1 WO2014008697 A1 WO 2014008697A1 CN 2012079693 W CN2012079693 W CN 2012079693W WO 2014008697 A1 WO2014008697 A1 WO 2014008697A1
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WIPO (PCT)
Prior art keywords
substrate
hard mask
etching
shallow trench
trench isolation
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PCT/CN2012/079693
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English (en)
French (fr)
Inventor
尹海洲
张珂珂
Original Assignee
中国科学院微电子研究所
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Priority to US14/413,966 priority Critical patent/US20150214097A1/en
Publication of WO2014008697A1 publication Critical patent/WO2014008697A1/zh

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    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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Definitions

  • the present invention relates to the field of semiconductor integrated circuit fabrication and, more particularly, to a method of fabricating shallow trench isolation having different stresses in different directions. Background technique
  • tensile stress is applied in the channel length direction (in the direction of the source region-channel region-drain region, which may be referred to as the second direction in the present invention)
  • a tensile stress is applied in the channel width direction (in the gate extension direction, perpendicular to the length direction, the second direction, which may be referred to as the first direction in the present invention)
  • the compressive stress is applied in the channel length direction
  • a tensile stress is applied in the channel width direction.
  • Substrate-induced uniaxial strain refers to the fabrication of MOS devices on a lattice mismatched substrate, such as SiGe, which is subjected to biaxial stress in the direction of the parallel substrate due to lattice mismatch with the substrate.
  • Process-induced uniaxial strains include: ⁇ -type embedded stressor drain regions of SiGe or Si:C materials, stress gate sidewalls of silicon nitride or diamond-like amorphous carbon (DLC), and nitridation over the entire device. Stress capping of silicon or diamond-like amorphous carbon (DLC), shallow trench isolation (STI) with stress, and more.
  • the object of the present invention is to simultaneously apply stress to the NMOS and the PMOS by using the existing tube-easy process, thereby increasing the carrier mobility of the channel region, thereby improving the overall driving capability of the device.
  • a shallow trench isolation manufacturing method comprising: forming a hard mask layer on a substrate; photolithography/etching the hard mask layer and the substrate, forming a plurality of a first trench and a plurality of second trenches, wherein the first trench is along a first direction, the second trench is in a second direction perpendicular to the first direction, and the second trench has a larger volume than the first trench The volume of the trench; depositing an insulating material in the first and second trenches; planarizing the insulating material, the hard mask layer until the substrate is exposed, forming shallow trench isolation.
  • the hard mask layer comprises silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.
  • the step of forming the plurality of first trenches and the plurality of second trenches further comprises: photolithography/etching the hard mask layer to form a hard mask pattern in the first direction until the substrate is exposed; Etching the substrate to form a first trench; photolithography/etching the hard mask layer to form a hard mask pattern in the second direction until the substrate is exposed; etching the substrate to form a second trench.
  • the step of forming the plurality of first trenches and the plurality of second trenches further comprises: photolithography/etching the hard mask layer to form a hard mask pattern in the second direction until the substrate is exposed; Etching the substrate to form a second trench; lithography/etching the hard mask layer to form a hard mask pattern in the first direction until the substrate is exposed; etching the substrate to form the first trench.
  • the step of forming the plurality of first trenches and the plurality of second trenches further comprises: lithography / Etching the hard mask layer to form a grid-like hard mask pattern having a plurality of openings along the first direction and the second direction; etching the substrate while forming the first trench and the second trench.
  • width of the second trench is greater than the width of the first trench.
  • the insulating material comprises silicon oxide, silicon nitride, silicon oxynitride, Bi 0 95 La 0 05 MO 3 , BiNi0 3 , ZrW 2 0 8 .
  • the shallow trench isolation applies a tensile stress to the substrate.
  • first direction is the device channel region width direction and the second direction is the device channel region length direction.
  • the present invention also provides a semiconductor device comprising a substrate, a shallow trench isolation formed of an insulating material in the substrate, wherein: the volume of the shallow trench isolation in the second direction is greater than the first direction The volume of shallow trench isolation.
  • a deeper, wider shallow trench isolation is etched in the channel width direction, and a shallower, narrower shallow trench is etched in the channel length direction.
  • the trench isolation while applying stress to the NMOS and PMOS, increases the carrier mobility in the channel region, thereby improving the overall driving capability of the device.
  • FIG. 1 is a flow chart of a shallow trench isolation manufacturing method in accordance with the present invention.
  • FIG. 2 is a cross-sectional view of a shallow trench isolation fabrication method in accordance with the present invention, showing deposition of a hard mask layer on a substrate;
  • FIG. 3 is a top plan view of a shallow trench isolation manufacturing method in accordance with the present invention, wherein a plurality of mutually parallel first trenches are etched in the channel width direction; [0023] FIG.
  • FIG. 4 is a top plan view of a shallow trench isolation fabrication method in accordance with the present invention, showing a plurality of mutually parallel second trenches being etched along the length of the channel; [0024] FIG.
  • FIG. 5 is a cross-sectional view of a shallow trench isolation manufacturing method in accordance with the present invention, showing a plurality of first trenches along the AA' direction shown in FIG. 3 or FIG. 4; [0025] FIG.
  • FIG. 6 is a cross-sectional view of a shallow trench isolation manufacturing method in accordance with the present invention, showing a cross-sectional view along FIG. 27 is a cross-sectional view of a shallow trench isolation manufacturing method in accordance with the present invention, showing a fill pattern 5
  • FIG. 28 is a cross-sectional view of a shallow trench isolation manufacturing method in accordance with the present invention, showing a fill pattern 6
  • FIG. 9 is a cross-sectional view of a shallow trench isolation fabrication method in accordance with the present invention, showing the planarization of the structure of FIG. 7 until the substrate is exposed;
  • FIG. 10 is a cross-sectional view of the shallow trench isolation fabrication method in accordance with the present invention, wherein The structure shown in Fig. 8 is planarized until the substrate is exposed. detailed description
  • FIG. 1 is a flow chart of a shallow trench isolation manufacturing method in accordance with the present invention, and various steps of the method of the present invention will be described in detail below with reference to the flow diagram of FIG. 1 and FIGS. 2 through 10.
  • a hard mask layer 2 is deposited on the substrate 1.
  • the substrate 1 is provided, and the material thereof may be (body) Si (for example, single crystal Si wafer), SOL GeOI (Ge on insulator), or other compound semiconductors such as GaAs, SiGe, GeSn, InP, InSb, GaN, etc. .
  • the substrate 1 is selected from a bulk Si or SOI for compatibility with a CMOS process.
  • the hard mask layer 2 is deposited on the substrate 1 by a conventional method such as LPCVD, PECVD, HDPCVD, MOCVD, MBE, ALD, evaporation, thermal oxidation or the like.
  • the material of the hard mask layer 2 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof.
  • the hard mask layer 2 may be a single layer or a combination of the above materials (e.g., lamination).
  • the hard mask layer 2 includes a pad oxide layer 2A and a mask cap layer 2B which are stacked one on another.
  • the pad oxide layer 2A is made of, for example, silicon oxide or silicon oxynitride, and has a thickness of, for example, 1 to 5 nm, for protecting the surface of the substrate during etching to prevent an increase in defects from affecting device performance.
  • the material of the mask cap layer 2B is, for example, silicon nitride, and the thickness is, for example, 10 to 30 nm.
  • FIG. 1 and FIG. 3, FIG. 5 along the first direction (a device formed in the future such as a MOSFET) Etching the hard mask layer 2 until the substrate 1 is exposed to form a hard mask pattern, and then further etching the substrate 1 to form a plurality of first grooves parallel to each other Slot 1A.
  • the etching method is selected according to the material of the hard mask layer 2 A/2B and the substrate 1 so that a high etching selectivity ratio between the layers of the material can be performed by dry etching such as fluorocarbon-based plasma etching. .
  • the width of the single first trench 1A itself (in the second direction perpendicular to the first direction) is, for example, 20 to 100 nm, and serves as a portion for forming the future shallow trench isolation on both sides in the length direction of the channel region.
  • the distance between the plurality of first trenches 1A is, for example, 200 to 2000 nm for dividing the active region of the device along the length direction of the channel region.
  • Figure 5 is a cross-sectional view along line AA of Figure 3, showing the first trench 1A having a narrower width, and preferably having a shallower depth, such as 50 to 200 nm.
  • the second direction (the direction of the channel region length of the MOSFET device formed in the future, that is, the direction in which the source region-channel region-drain region extends, preferably perpendicular to The foregoing first direction) continues to etch the hard mask layer 2 to form a second hard mask pattern, and then further etches the substrate 1 to form a plurality of second trenches 1B that are parallel to each other.
  • the second trench 1B can be formed by the above dry etching.
  • the volume of the second trench IB is larger than the volume of the first trench 1A, so that the volume of the STI formed in the future in the width direction of the channel region is larger than the volume at both ends in the length direction of the channel region, thereby making the device
  • the stress applied in the width direction of the channel region is greater than the stress in the length direction of the channel region of the device.
  • the width of the single second trench 1B itself (in a first direction perpendicular to the second direction) is larger than the width of the single first trench 1A itself, for example, 50 to 300 nm.
  • the distance between the plurality of second trenches 1B is, for example, 200 to 100 nm, for dividing the active region of the device along the width direction of the channel region.
  • Figure 6 is a cross-sectional view taken along line BB of Figure 4, the width of the second groove 1B being greater than the width of the first groove 1A as compared with Figure 5. And preferably, the depth of the second trench 1B is also greater than the depth of the first trench 1A, which is, for example, 100 to 300 nm.
  • the first trench is etched and then the second trench is etched.
  • the second trench may be etched and the first trench may be etched. The etching step and parameters are similar to the above. .
  • the volume of the second trench 1B shown in the embodiment is larger than the volume of the first trench 1A
  • the width and the depth are both larger than, but alternatively, the width may be the same and the depth is larger, or the depth is the same and the width is larger.
  • FIG. 3 to FIG. 6 show the order in which the hard mask pattern and the first trench are formed first, and then the hard mask pattern and the second trench are formed again in the embodiment, other modifications may be employed in the modification. Implement the process. For example, a grid-shaped photolithography mask is used to lithography/etch a hard mask at a time to form a grid-like hard mask pattern as shown in FIG.
  • the depths of the two trenches may be the same and the widths are different; or, the etching sequence shown in FIG. 3 to FIG. 6 is used, that is, the first trench is etched first, and then the second trench is etched, but the two trenches are The width is the same except that the depth of the second trench 1B is greater than the depth of the first trench 1A.
  • the step of forming the plurality of first trenches and the plurality of second trenches further comprises: photolithography/etching the hard mask layer to form a hard mask pattern in the second direction until the substrate is exposed; etching the substrate Forming a second trench; lithography/etching the hard mask layer to form a hard mask pattern along the first direction until the substrate is exposed; etching the substrate to form the first trench
  • the insulating material 3 is simultaneously deposited in the first trench 1A and the second trench 1B to serve as an STI and to provide stress.
  • the deposition method is, for example, a conventional method such as PECVD or HDPCVD, and the stress is adjusted by controlling the deposition process parameters, for example, the absolute value of the stress is 600 MPa to 2 GPa.
  • the insulating material 3 applies a tensile stress to the substrate 1.
  • the insulating material 3 may be a conventional silicon oxide, silicon nitride, silicon oxynitride or a negative thermal expansion dielectric material such as Bi 0 . 95 La 0 .
  • the tensile stress applied to the insulating material 3 having tensile stress in the second trench IB is greater than the tensile stress applied in the first trench 1 A, and thus the high tensile stress applied in the width direction of the channel region of the device is obtained for the NMOS.
  • the carrier mobility of the electrons in the NMOS channel region is greatly increased, and although the compressive stress is not applied to the PMOS region in the length direction of the channel region of the device, it is also applied in the width direction of the channel region.
  • the large tensile stress partially offsets the degradation of the PMOS performance, that is, the substantial increase in the NMOS driving capability compensates for the insufficient improvement of the PMOS driving capability and improves the driving capability of the entire IC as a whole.
  • the insulating material 3 and the hard mask layer 2 are planarized by techniques such as etch back or CMP until the substrate 1 is exposed to form a final shallow trench isolation 3A/ 3B.
  • the volume of the portion 3A in which the STI is distributed in the first direction is smaller than the volume of the portion 3B distributed in the second direction. Therefore, the shallow trench isolation formed in accordance with the manufacturing method of the present invention has a volume in the width direction of the channel region of the device larger than that in the length direction of the channel region of the device to apply a larger stress.
  • a deeper, wider shallow trench isolation is etched in the channel width direction, and a shallower, narrower shallow trench is etched in the channel length direction.
  • Slot isolation At the same time, stress is applied to the NMOS and PMOS to increase the carrier mobility in the channel region, thereby improving the overall driving capability of the device.

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Abstract

本发明公开了一种浅沟槽隔离的制造方法，包括：在衬底上形成硬掩模层；光刻/刻蚀硬掩模层和衬底，形成多个第一沟槽和多个第二沟槽，其中，第一沟槽沿第一方向，第二沟槽沿垂直于第一方向的第二方向，并且第二沟槽的体积大于第一沟槽的体积；在第一和第二沟槽中沉积绝缘材料；平坦化绝缘材料、硬掩模层直至暴露衬底，形成浅沟槽隔离。依照本发明的浅沟槽隔离制造方法，在沟道宽度方向刻蚀填充较深、较宽的浅沟槽隔离，而在沟道长度方向刻蚀填充较浅、较窄的浅沟槽隔离，同时向NMOS和PMOS施加应力，增大其沟道区载流子迁移率，从而提高器件整体驱动能力。

Description

浅沟槽隔离制造方法
[0001]本申请要求了 2012月 7月 13日提交的、 申请号为 201210244781.X、发 明名称为 "浅沟槽隔离制造方法"的中国专利申请的优先权， 其全部内容通过 引用结合在本申请中。 技术领域
[0002]本发明涉及半导体集成电路制造领域， 更具体地， 涉及一种沿不同方 向具有不同应力的浅沟槽隔离的制造方法。 背景技术
[0003]随着器件尺寸缩减， 器件综合性能不断提高， 然而例如 MOSFET沟道 区的载流子迁移率受制于材料和工艺并没有随着大幅度提高， 因此其驱动能 力显得日益不足。 为了提高载流子迁移率、 增强器件驱动能力， 现有技术中 一种可选的方法是向 MOSFET施加应力。 例如对于（100)/<110>^々NMOS而言 在沟道长度方向 （沿源区-沟道区-漏区的方向， 在本发明中可以称为第二方 向）上施加张应力、 在沟道宽度方向 （沿栅极延伸方向， 垂直于长度方向、 第二方向， 在本发明中可以称为第一方向）上施加张应力； 而对于 PMOS而 言， 在沟道长度方向施加压应力， 在沟道宽度方向上施加张应力。 如此的双 轴应力结构 /方法可以分别增加 NMOS沟道区中电子、 PMOS沟道区中空穴的 载流子迁移率， 从而相应提高驱动能力。
[0004]现有的向沟道区施加应力的结构 /方法包括衬底致双轴应变、工艺致单 轴应变。衬底致单轴应变是指在晶格失配的衬底（如 SiGe )上制造 MOS器件， 沟道由于与衬底晶格失配在平行衬底方向上受到双轴应力。 工艺致单轴应变 包括： SiGe或者 Si:C材质的∑型嵌入式应力源漏区、 氮化硅或者类金刚石无 定形碳（DLC )材质的应力栅极侧墙、 整个器件上覆盖的氮化硅或者类金刚 石无定形碳（DLC )材质的应力盖层、 以及具有应力的浅沟槽隔离 （STI ) 等等。 理论计算和实际试验数据证明， 工艺致单轴应变在器件特张尺寸持续 缩小的情况下具有更好的效果。 [0005]与此同时， 随着器件特征尺寸持续缩减到 32nm以下，上述各种应力提 供结构 /方法中存在了光刻 /刻蚀精度不足、 材料沉积填充率减小、 与沟道区 间距仍不够小等等问题。 而由于 NMOS与 PMOS通常具有相同的栅极方向、 沟道区方向， 因此使用质量控制容易的应力 STI来增强载流子迁移率， 逐渐 成为一项重要选择。
[0006]然而，现有的应力 STI技术虽然对于集中分布的 NMOS和 PMOS可以分 别施加不同应力， 然而对于混杂分布的情形则难以利用筒单工艺实现区别对 待， 因此难以统一地同时提高两种 MOSFET的迁移率。 此外， 至少两次形成 不同应力类型的 STI技术， 也提高了工艺的复杂度、 增加了时间和制造成本。 发明内容
[0007]有鉴于此， 本发明的目的在于利用现有的筒易工艺同时向 NMOS和 PMOS施加应力，增大其沟道区载流子迁移率，从而提高器件整体驱动能力。
[0008] 实现本发明的上述目的， 是通过提供一种浅沟槽隔离的制造方法， 包 括： 在衬底上形成硬掩模层； 光刻 /刻蚀硬掩模层和衬底， 形成多个第一沟槽 和多个第二沟槽， 其中， 第一沟槽沿第一方向， 第二沟槽沿垂直于第一方向 的第二方向， 并且第二沟槽的体积大于第一沟槽的体积； 在第一和第二沟槽 中沉积绝缘材料； 平坦化绝缘材料、 硬掩模层直至暴露衬底， 形成浅沟槽隔 离。
[0009】其中， 硬掩模层包括氧化硅、 氮化硅、 氮氧化硅及其组合。
[0010】其中， 形成多个第一沟槽和多个第二沟槽的步骤进一步包括： 光刻 / 刻蚀硬掩模层形成沿第一方向的硬掩模图形， 直至暴露衬底； 刻蚀衬底， 形 成第一沟槽； 光刻 /刻蚀硬掩模层形成沿第二方向的硬掩模图形，直至暴露衬 底； 刻蚀衬底， 形成第二沟槽。
[0011】其中， 形成多个第一沟槽和多个第二沟槽的步骤进一步包括： 光刻 / 刻蚀硬掩模层形成沿第二方向的硬掩模图形， 直至暴露衬底； 刻蚀衬底， 形 成第二沟槽； 光刻 /刻蚀硬掩模层形成沿第一方向的硬掩模图形，直至暴露衬 底； 刻蚀衬底， 形成第一沟槽。
[0012】其中， 形成多个第一沟槽和多个第二沟槽的步骤进一步包括： 光刻 / 刻蚀硬掩模层形成网格状的硬掩模图形，具有多个沿第一方向以及第二方向 的开口； 刻蚀衬底， 同时形成第一沟槽和第二沟槽。
[0013】其中， 第二沟槽的宽度大于第一沟槽的宽度。
[0014]其中， 第二沟槽的深度大于第一沟槽的深度。
[0015】其中， 绝缘材料包括氧化硅、 氮化硅、 氮氧化硅、 Bi0 95La0 05MO3、 BiNi03、 ZrW208。
[0016】其中， 浅沟槽隔离向衬底施加张应力。
[0017】其中， 第一方向是器件沟道区宽度方向， 第二方向是器件沟道区长度 方向。
[0018】本发明还提供了一种半导体器件， 包括衬底、 衬底中的绝缘材料构成 的浅沟槽隔离， 其特征在于： 第二方向上浅沟槽隔离的体积要大于第一方向 上浅沟槽隔离的体积。
[0019]依照本发明的浅沟槽隔离制造方法， 在沟道宽度方向刻蚀填充较深、 较宽的浅沟槽隔离， 而在沟道长度方向刻蚀填充较浅、 较窄的浅沟槽隔离， 同时向 NMOS和 PMOS施加应力， 增大其沟道区载流子迁移率， 从而提高器 件整体驱动能力。 附图说明
[0020] 以下参照附图来详细说明本发明的技术方案， 其中：
[0021] 图 1为根据本发明的浅槽隔离制造方法的流程图；
[0022] 图 2为根据本发明的浅槽隔离制造方法的剖视图， 其中显示了在衬底 上沉积硬掩模层；
[0023] 图 3为根据本发明的浅槽隔离制造方法的顶视图， 其中显示了沿沟道 宽度方向刻蚀多个相互平行的第一沟槽；
[0024] 图 4为根据本发明的浅槽隔离制造方法的顶视图， 其中显示了沿沟道 长度方向刻蚀多个相互平行的第二沟槽；
[0025] 图 5为根据本发明的浅槽隔离制造方法的剖视图，其中显示了沿图 3或 者图 4所示 AA'方向的多个第一沟槽；
[0026] 图 6为根据本发明的浅槽隔离制造方法的剖视图，其中显示了沿图 4所 27] 图 7为根据本发明的浅槽隔离制造方法的剖视图，其中显示了填充图 5
Figure imgf000006_0001
28] 图 8为根据本发明的浅槽隔离制造方法的剖视图，其中显示了填充图 6
Figure imgf000006_0002
[0029] 图 9为根据本发明的浅槽隔离制造方法的剖视图， 其中显示了平坦化 图 7所示结构直至暴露衬底； 图 10为根据本发明的浅槽隔离制造方法的剖视 图， 其中显示了平坦化图 8所示结构直至暴露衬底。 具体实施方式
[0030] 以下参照附图并结合示意性的实施例来详细说明本发明技术方案的 特征及其技术效果。 需要指出的是， 类似的附图标记表示类似的结构， 本申 请中所用的术语"第一"、 "第二"、 "上"、 "下"、 "厚"、 "薄"等等可用于修饰 各种器件结构。 这些修饰除非特别说明并非暗示所修饰器件结构的空间、 次 序或层级关系。
[0031] 图 1为根据本发明的浅槽隔离制造方法的流程图， 以下将参照图 1的流 程图以及图 2至图 10来详细说明本发明的方法的各个步骤。
[0032】参照图 1以及图 2 , 在衬底 1上沉积硬掩模层 2。 提供衬底 1 , 其材质可 以是（体） Si (例如单晶 Si晶片）、 SOL GeOI (绝缘体上 Ge ), 也可以是其 他化合物半导体， 例如 GaAs、 SiGe、 GeSn、 InP、 InSb、 GaN等等。 优选地， 衬底 1选用体 Si或 SOI , 以便与 CMOS工艺兼容。 采用 LPCVD、 PECVD、 HDPCVD、 MOCVD、 MBE、 ALD、 蒸发、 热氧化等常规方法， 在衬底 1上 沉积硬掩模层 2。 硬掩模层 2的材质例如包括氧化硅、 氮化硅、 氮氧化硅及其 组合。 硬掩模层 2可以是单层， 也可以是上述材料的组合（例如层叠）。 优选 地， 在本发明实施例中， 硬掩模层 2包括上下层叠的垫氧化层 2A以及掩模盖 层 2B。 垫氧化层 2A材质例如为氧化硅或者氮氧化硅， 厚度例如 l ~ 5nm, 用 于在刻蚀时保护衬底表面以避免增加缺陷影响器件性能。掩模盖层 2B材质例 如为氮化硅， 厚度例如 10 ~ 30nm。
[0033]参照图 1以及图 3、 图 5 , 沿第一方向 （未来形成的器件例如 MOSFET 的沟道宽度方向， 也即未来栅极延伸的方向）刻蚀硬掩模层 2直至暴露衬底 1 形成硬掩模图形，随后进一步刻蚀衬底 1而形成多个相互平行的第一沟槽 1A。 刻蚀方法根据硬掩模层 2 A/2B与衬底 1的材料来选择，使得各层材料之间具有 较高的刻蚀选择比， 可以采用干法刻蚀例如碳氟基气体等离子刻蚀。 单个第 一沟槽 1A自身的宽度（沿垂直于第一方向的第二方向）例如为 20 ~ 100nm, 用作形成未来浅沟槽隔离在沟道区长度方向上两侧的部分。多个第一沟槽 1A 之间的距离例如为 200 ~ 2000nm,用于划分出器件有源区沿沟道区长度方向。 图 5为图 3沿 AA，的剖视图， 其中显示了第一沟槽 1A具有较窄的宽度， 并且优 选地具有较浅的深度， 深度例如是 50 ~ 200nm。
[0034】参照图 1以及图 4、 图 6 , 沿第二方向 （未来形成的 MOSFET器件的沟 道区长度方向， 也即源区 -沟道区 -漏区延伸分布的方向， 优选地垂直于前 述的第一方向）继续刻蚀硬掩模层 2形成第二硬掩模图形， 随后进一步刻蚀 衬底 1而形成多个相互平行的第二沟槽 1B。 类似地， 可以采用上述干法刻蚀 形成第二沟槽 1B。 第二沟槽 IB的体积要大于第一沟槽 1A的体积， 以使得未 来形成的 STI在沟道区宽度方向上两端的体积要大于在沟道区长度方向上两 端的体积，从而使得向器件沟道区宽度方向上施加的应力要大于器件沟道区 长度方向上的应力。 例如， 单个第二沟槽 1B自身的宽度（沿垂直于第二方向 的第一方向）比单个第一沟槽 1A自身的宽度要大， 例如是 50 ~ 300nm。 多个 第二沟槽 1B之间的距离例如是 200 ~ lOOOnm, 用于划分出器件有源区沿沟道 区宽度方向。 图 6是图 4沿 BB，上的剖视图， 与图 5相比， 第二沟槽 1B的宽度 要大于第一沟槽 1A的宽度。 并且优选地， 第二沟槽 1B的深度也大于第一沟 槽 1A的深度， 该深度例如是 100 ~ 300nm。 实施例中显示的为先刻蚀第一沟 槽后刻蚀第二沟槽， 可选地， 也可以刻蚀第二沟槽后刻蚀第一沟槽， 刻蚀步 骤与参数与以上所述类似。虽然实施例中显示的第二沟槽 1B体积大于第一沟 槽 1A体积的方式是宽度、 深度均要大于， 但是可选地， 也可以宽度相同而深 度更大， 或者深度相同而宽度更大。 此外， 虽然图 3〜图 6显示了实施例中先 形成硬掩模图形与第一沟槽、然后再次形成硬掩模图形与第二沟槽的先后顺 序， 但是变形例中也可以采用其他的实施工序。 例如， 采用网格状的光刻掩 模板一次性光刻 /刻蚀硬掩模而形成如图 4所示的网格状硬掩模图形 （也即具 有多个沿第一方向的开口以及多个沿第二方向的开口）， 然后采用一次性干 法刻蚀形成图 5以及图 6中的第一沟槽 1 A和第二沟槽 1 B , 此时两沟槽深度可 以相同而宽度不同； 或者， 采用图 3〜图 6所示的刻蚀顺序， 也即先刻蚀第一 沟槽， 然后刻蚀第二沟槽， 但是两个沟槽的宽度相同， 只是第二沟槽 1B深度 大于第一沟槽 1A深度。或者，形成多个第一沟槽和多个第二沟槽的步骤进一 步包括： 光刻 /刻蚀硬掩模层形成沿第二方向的硬掩模图形， 直至暴露衬底； 刻蚀衬底，形成第二沟槽；光刻 /刻蚀硬掩模层形成沿第一方向的硬掩模图形， 直至暴露衬底； 刻蚀衬底， 形成第一沟槽
[0035】此后， 参照图 1以及图 7、 图 8, 在第一沟槽 1A以及第二沟槽 1B中同时 沉积绝缘材料 3 , 用作 STI并提供应力。 沉积方法例如是 PECVD、 HDPCVD 等常规方法， 通过控制沉积工艺参数来调整应力大小， 例如应力的绝对值为 600MPa ~ 2GPa。 优选地， 绝缘材料 3向衬底 1施加张应力。 绝缘材料 3可以是 传统的氧化硅、 氮化硅、 氮氧化硅， 也可以负热膨胀介质材料， 如 Bi0.95La0.05NiO3、 BiNi03、 ZrW208等钙钛矿型氧化物， 其在 100K温度下的线 性体积膨胀系数的绝对值大于 10_4/K。具有张应力的绝缘材料 3在第二沟槽 IB 中施加的张应力大于第一沟槽 1 A中施加的张应力， 因此对于 NMOS而言器件 沟道区宽度方向上施加的高张应力得到了大幅提高从而提高了 NMOS沟道 区电子的载流子迁移率， 而对于 PMOS而言虽然并未在器件沟道区长度方向 上施加压应力， 但是因为其在沟道区宽度方向上也施加了较大的张应力， 而 部分抵消了 PMOS性能的退化， 也即 NMOS驱动能力的大幅提升弥补了 PMOS驱动能力的改善不足而整体上提高了整个 IC的驱动能力。
[0036]最后， 参照图 1以及图 9、 图 10, 采用回刻或者 CMP等技术平坦化绝缘 材料 3以及硬掩模层 2, 直至暴露衬底 1 , 形成了最终的浅沟槽隔离 3A/3B。 其 中， STI在第一方向上分布的部分 3A的体积要小于在第二方向上分布的部分 3B的体积。 因此， 依照本发明的制造方法形成的浅沟槽隔离， 在器件沟道区 宽度方向上的体积要大于在器件沟道区长度方向上的体积， 以便施加更大的 应力。
[0037]依照本发明的浅沟槽隔离制造方法， 在沟道宽度方向刻蚀填充较深、 较宽的浅沟槽隔离， 而在沟道长度方向刻蚀填充较浅、 较窄的浅沟槽隔离， 同时向 NMOS和 PMOS施加应力， 增大其沟道区载流子迁移率， 从而提高器 件整体驱动能力。
[0038]尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可 以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变 和等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材料的 修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作为用于实现 本发明的最佳实施方式而公开的特定实施例， 而所公开的器件结构及其制造 方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种浅沟槽隔离的制造方法， 包括：
在衬底上形成硬掩模层；
光刻 /刻蚀硬掩模层和衬底， 形成多个第一沟槽和多个第二沟槽， 其中， 第一沟槽沿第一方向， 第二沟槽沿垂直于第一方向的第二方向， 并且第二沟 槽的体积大于第一沟槽的体积；
在第一和第二沟槽中沉积绝缘材料；
平坦化绝缘材料、 硬掩模层直至暴露衬底， 形成浅沟槽隔离。
2. 如权利要求 1的浅沟槽隔离的制造方法， 其中， 硬掩模层包括氧化 硅、 氮化硅、 氮氧化硅及其组合。
3. 如权利要求 1的浅沟槽隔离的制造方法， 其中， 形成多个第一沟槽 和多个第二沟槽的步骤进一步包括：光刻 /刻蚀硬掩模层形成沿第一方向的硬 掩模图形， 直至暴露衬底； 刻蚀衬底， 形成第一沟槽； 光刻 /刻蚀硬掩模层形 成沿第二方向的硬掩模图形， 直至暴露衬底； 刻蚀衬底， 形成第二沟槽。
4. 如权利要求 1的浅槽隔离的制造方法， 其中， 形成多个第一沟槽和 多个第二沟槽的步骤进一步包括：光刻 /刻蚀硬掩模层形成沿第二方向的硬掩 模图形， 直至暴露衬底； 刻蚀衬底， 形成第二沟槽； 光刻 /刻蚀硬掩模层形成 沿第一方向的硬掩模图形， 直至暴露衬底； 刻蚀衬底， 形成第一沟槽。
5. 如权利要求 1的浅沟槽隔离的制造方法， 其中， 形成多个第一沟槽 和多个第二沟槽的步骤进一步包括：光刻 /刻蚀硬掩模层形成网格状的硬掩模 图形， 具有多个沿第一方向以及第二方向的开口； 刻蚀衬底， 同时形成第一 沟槽和第二沟槽。
6. 如权利要求 1的浅沟槽隔离的制造方法， 其中， 第二沟槽的宽度大 于第一沟槽的宽度。
7. 如权利要求 1的浅沟槽隔离的制造方法， 其中， 第二沟槽的深度大 于第一沟槽的深度。
8. 如权利要求 1的浅沟槽隔离的制造方法， 其中， 绝缘材料包括氧化 硅、 氮化硅、 氮氧化硅、 Bi0.95La0.05NiO3、 BiNi03、 ZrW208。
9. 如权利要求 1的浅沟槽隔离的制造方法， 其中， 浅沟槽隔离向衬底 施力口张应力。
10. 如权利要求 1的浅沟槽隔离的制造方法， 其中， 第一方向是器件沟 道区宽度方向， 第二方向是器件沟道区长度方向。
11. 一种半导体器件， 包括衬底、 衬底中的绝缘材料构成的浅沟槽隔 离， 其特征在于： 第二方向上浅沟槽隔离的体积要大于第一方向上浅沟槽隔 离的体积。
PCT/CN2012/079693 2012-07-13 2012-08-03 浅沟槽隔离制造方法 WO2014008697A1 (zh)

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