CN103545241A - 浅沟槽隔离制造方法 - Google Patents

浅沟槽隔离制造方法 Download PDF

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CN103545241A
CN103545241A CN201210244781.XA CN201210244781A CN103545241A CN 103545241 A CN103545241 A CN 103545241A CN 201210244781 A CN201210244781 A CN 201210244781A CN 103545241 A CN103545241 A CN 103545241A
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groove
trench isolation
shallow trench
substrate
forms
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尹海洲
张珂珂
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN201210244781.XA priority Critical patent/CN103545241A/zh
Priority to PCT/CN2012/079693 priority patent/WO2014008697A1/zh
Priority to US14/413,966 priority patent/US20150214097A1/en
Publication of CN103545241A publication Critical patent/CN103545241A/zh
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Abstract

本发明公开了一种浅沟槽隔离的制造方法，包括：在衬底上形成硬掩模层；光刻/刻蚀硬掩模层和衬底，形成多个第一沟槽和多个第二沟槽，其中，第一沟槽沿第一方向，第二沟槽沿垂直于第一方向的第二方向，并且第二沟槽的体积大于第一沟槽的体积；在第一和第二沟槽中沉积绝缘材料；平坦化绝缘材料、硬掩模层直至暴露衬底，形成浅沟槽隔离。依照本发明的浅沟槽隔离制造方法，在沟道宽度方向刻蚀填充较深、较宽的浅沟槽隔离，而在沟道长度方向刻蚀填充较浅、较窄的浅沟槽隔离，同时向NMOS和PMOS施加应力，增大其沟道区载流子迁移率，从而提高器件整体驱动能力。

Description

浅沟槽隔离制造方法
技术领域
本发明涉及半导体集成电路制造领域，更具体地，涉及一种沿不同方向具有不同应力的浅沟槽隔离的制造方法。
背景技术
随着器件尺寸缩减，器件综合性能不断提高，然而例如MOSFET沟道区的载流子迁移率受制于材料和工艺并没有随着大幅度提高，因此其驱动能力显得日益不足。为了提高载流子迁移率、增强器件驱动能力，现有技术中一种可选的方法是向MOSFET施加应力。例如对于(100)/<110>的N MOS而言在沟道长度方向(沿源区-沟道区-漏区的方向，在本发明中可以称为第二方向)上施加张应力、在沟道宽度方向(沿栅极延伸方向，垂直于长度方向、第二方向，在本发明中可以称为第一方向)上施加张应力；而对于PMOS而言，在沟道长度方向施加压应力，在沟道宽度方向上施加张应力。如此的双轴应力结构/方法可以分别增加N MOS沟道区中电子、PMOS沟道区中空穴的载流子迁移率，从而相应提高驱动能力。
现有的向沟道区施加应力的结构/方法包括衬底致双轴应变、工艺致单轴应变。衬底致单轴应变是指在晶格失配的衬底(如SiGe)上制造MOS器件，沟道由于与衬底晶格失配在平行衬底方向上受到双轴应力。工艺致单轴应变包括：SiGe或者Si：C材质的Σ型嵌入式应力源漏区、氮化硅或者类金刚石无定形碳(DLC)材质的应力栅极侧墙、整个器件上覆盖的氮化硅或者类金刚石无定形碳(DLC)材质的应力盖层、以及具有应力的浅沟槽隔离(STI)等等。理论计算和实际试验数据证明，工艺致单轴应变在器件特张尺寸持续缩小的情况下具有更好的效果。
与此同时，随着器件特征尺寸持续缩减到32nm以下，上述各种应力提供结构/方法中存在了光刻/刻蚀精度不足、材料沉积填充率减小、与沟道区间距仍不够小等等问题。而由于N MOS与PMOS通常具有相同的栅极方向、沟道区方向，因此使用质量控制容易的应力STI来增强载流子迁移率，逐渐成为一项重要选择。
然而，现有的应力STI技术虽然对于集中分布的N MOS和PMOS可以分别施加不同应力，然而对于混杂分布的情形则难以利用简单工艺实现区别对待，因此难以统一地同时提高两种MOSFET的迁移率。此外，至少两次形成不同应力类型的STI技术，也提高了工艺的复杂度、增加了时间和制造成本。
发明内容
有鉴于此，本发明的目的在于利用现有的简易工艺同时向NMOS和PMOS施加应力，增大其沟道区载流子迁移率，从而提高器件整体驱动能力。
实现本发明的上述目的，是通过提供一种浅沟槽隔离的制造方法，包括：在衬底上形成硬掩模层；光刻/刻蚀硬掩模层和衬底，形成多个第一沟槽和多个第二沟槽，其中，第一沟槽沿第一方向，第二沟槽沿垂直于第一方向的第二方向，并且第二沟槽的体积大于第一沟槽的体积；在第一和第二沟槽中沉积绝缘材料；平坦化绝缘材料、硬掩模层直至暴露衬底，形成浅沟槽隔离。
其中，硬掩模层包括氧化硅、氮化硅、氮氧化硅及其组合。
其中，形成多个第一沟槽和多个第二沟槽的步骤进一步包括：光刻/刻蚀硬掩模层形成沿第一方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第一沟槽；光刻/刻蚀硬掩模层形成沿第二方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第二沟槽。
其中，形成多个第一沟槽和多个第二沟槽的步骤进一步包括：光刻/刻蚀硬掩模层形成沿第二方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第二沟槽；光刻/刻蚀硬掩模层形成沿第一方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第一沟槽。
其中，形成多个第一沟槽和多个第二沟槽的步骤进一步包括：光刻/刻蚀硬掩模层形成网格状的硬掩模图形，具有多个沿第一方向以及第二方向的开口；刻蚀衬底，同时形成第一沟槽和第二沟槽。
其中，第二沟槽的宽度大于第一沟槽的宽度。
其中，第二沟槽的深度大于第一沟槽的深度。
其中，绝缘材料包括氧化硅、氮化硅、氮氧化硅、Bi0.95La0.05NiO3、BiNiO3、ZrW2O8。
其中，浅沟槽隔离向衬底施加张应力。
其中，第一方向是器件沟道区宽度方向，第二方向是器件沟道区长度方向。
本发明还提供了一种半导体器件，包括衬底、衬底中的绝缘材料构成的浅沟槽隔离，其特征在于：第二方向上浅沟槽隔离的体积要大于第一方向上浅沟槽隔离的体积。
依照本发明的浅沟槽隔离制造方法，在沟道宽度方向刻蚀填充较深、较宽的浅沟槽隔离，而在沟道长度方向刻蚀填充较浅、较窄的浅沟槽隔离，同时向N MOS和PMOS施加应力，增大其沟道区载流子迁移率，从而提高器件整体驱动能力。
附图说明
以下参照附图来详细说明本发明的技术方案，其中：
图1为根据本发明的浅槽隔离制造方法的流程图；
图2为根据本发明的浅槽隔离制造方法的剖视图，其中显示了在衬底上沉积硬掩模层；
图3为根据本发明的浅槽隔离制造方法的顶视图，其中显示了沿沟道宽度方向刻蚀多个相互平行的第一沟槽；
图4为根据本发明的浅槽隔离制造方法的顶视图，其中显示了沿沟道长度方向刻蚀多个相互平行的第二沟槽；
图5为根据本发明的浅槽隔离制造方法的剖视图，其中显示了沿图3或者图4所示AA，方向的多个第一沟槽；
图6为根据本发明的浅槽隔离制造方法的剖视图，其中显示了沿图4所示BB，方向的多个第二沟槽；
图7为根据本发明的浅槽隔离制造方法的剖视图，其中显示了填充图5所示的多个第一沟槽；
图8为根据本发明的浅槽隔离制造方法的剖视图，其中显示了填充图6所示的多个第二沟槽；
图9为根据本发明的浅槽隔离制造方法的剖视图，其中显示了平坦化图7所示结构直至暴露衬底；图10为根据本发明的浅槽隔离制造方法的剖视图，其中显示了平坦化图8所示结构直至暴露衬底。
具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案的特征及其技术效果。需要指出的是，类似的附图标记表示类似的结构，本申请中所用的术语“第一”、“第二”、“上”、“下”、“厚”、“薄”等等可用于修饰各种器件结构。这些修饰除非特别说明并非暗示所修饰器件结构的空间、次序或层级关系。
图1为根据本发明的浅槽隔离制造方法的流程图，以下将参照图1的流程图以及图2至图10来详细说明本发明的方法的各个步骤。
参照图1以及图2，在衬底1上沉积硬掩模层2。提供衬底1，其材质可以是(体)Si(例如单晶Si晶片)、SOI、GeOI(绝缘体上Ge)，也可以是其他化合物半导体，例如GaAs、SiGe、GeSn、InP、InSb、GaN等等。优选地，衬底1选用体Si或SOI，以便与CMOS工艺兼容。采用LPCVD、PECVD、HDPCVD、MOCVD、MBE、ALD、蒸发、热氧化等常规方法，在衬底1上沉积硬掩模层2。硬掩模层2的材质例如包括氧化硅、氮化硅、氮氧化硅及其组合。硬掩模层2可以是单层，也可以是上述材料的组合(例如层叠)。优选地，在本发明实施例中，硬掩模层2包括上下层叠的垫氧化层2A以及掩模盖层2B。垫氧化层2A材质例如为氧化硅或者氮氧化硅，厚度例如1～5nm，用于在刻蚀时保护衬底表面以避免增加缺陷影响器件性能。掩模盖层2B材质例如为氮化硅，厚度例如10～30nm。
参照图1以及图3、图5，沿第一方向(未来形成的器件例如MOSFET的沟道宽度方向，也即未来栅极延伸的方向)刻蚀硬掩模层2直至暴露衬底1形成硬掩模图形，随后进一步刻蚀衬底1而形成多个相互平行的第一沟槽1A。刻蚀方法根据硬掩模层2A/2B与衬底1的材料来选择，使得各层材料之间具有较高的刻蚀选择比，可以采用干法刻蚀例如碳氟基气体等离子刻蚀。单个第一沟槽1A自身的宽度(沿垂直于第一方向的第二方向)例如为20～100nm，用作形成未来浅沟槽隔离在沟道区长度方向上两侧的部分。多个第一沟槽1A之间的距离例如为200～2000nm，用于划分出器件有源区沿沟道区长度方向。图5为图3沿AA，的剖视图，其中显示了第一沟槽1A具有较窄的宽度，并且优选地具有较浅的深度，深度例如是50～200nm。
参照图1以及图4、图6，沿第二方向(未来形成的MOSFET器件的沟道区长度方向，也即源区-沟道区-漏区延伸分布的方向，优选地垂直于前述的第一方向)继续刻蚀硬掩模层2形成第二硬掩模图形，随后进一步刻蚀衬底1而形成多个相互平行的第二沟槽1B。类似地，可以采用上述干法刻蚀形成第二沟槽1B。第二沟槽1B的体积要大于第一沟槽1A的体积，以使得未来形成的STI在沟道区宽度方向上两端的体积要大于在沟道区长度方向上两端的体积，从而使得向器件沟道区宽度方向上施加的应力要大于器件沟道区长度方向上的应力。例如，单个第二沟槽1B自身的宽度(沿垂直于第二方向的第一方向)比单个第一沟槽1A自身的宽度要大，例如是50～300nm。多个第二沟槽1B之间的距离例如是200～1000nm，用于划分出器件有源区沿沟道区宽度方向。图6是图4沿BB，上的剖视图，与图5相比，第二沟槽1B的宽度要大于第一沟槽1A的宽度。并且优选地，第二沟槽1B的深度也大于第一沟槽1A的深度，该深度例如是100～300nm。实施例中显示的为先刻蚀第一沟槽后刻蚀第二沟槽，可选地，也可以刻蚀第二沟槽后刻蚀第一沟槽，刻蚀步骤与参数与以上所述类似。虽然实施例中显示的第二沟槽1B体积大于第一沟槽1A体积的方式是宽度、深度均要大于，但是可选地，也可以宽度相同而深度更大，或者深度相同而宽度更大。此外，虽然图3～图6显示了实施例中先形成硬掩模图形与第一沟槽、然后再次形成硬掩模图形与第二沟槽的先后顺序，但是变形例中也可以采用其他的实施工序。例如，采用网格状的光刻掩模板一次性光刻/刻蚀硬掩模而形成如图4所示的网格状硬掩模图形(也即具有多个沿第一方向的开口以及多个沿第二方向的开口)，然后采用一次性干法刻蚀形成图5以及图6中的第一沟槽1A和第二沟槽1B，此时两沟槽深度可以相同而宽度不同；或者，采用图3～图6所示的刻蚀顺序，也即先刻蚀第一沟槽，然后刻蚀第二沟槽，但是两个沟槽的宽度相同，只是第二沟槽1B深度大于第一沟槽1A深度。或者，形成多个第一沟槽和多个第二沟槽的步骤进一步包括：光刻/刻蚀硬掩模层形成沿第二方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第二沟槽；光刻/刻蚀硬掩模层形成沿第一方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第一沟槽
此后，参照图1以及图7、图8，在第一沟槽1A以及第二沟槽1B中同时沉积绝缘材料3，用作STI并提供应力。沉积方法例如是PECVD、HDPCVD等常规方法，通过控制沉积工艺参数来调整应力大小，例如应力的绝对值为600M Pa～2GPa。优选地，绝缘材料3向衬底1施加张应力。绝缘材料3可以是传统的氧化硅、氮化硅、氮氧化硅，也可以负热膨胀介质材料，如Bi0.95La0.05NiO3、BiNiO3、ZrW2O8等钙钛矿型氧化物，其在100K温度下的线性体积膨胀系数的绝对值大于10-4/K。具有张应力的绝缘材料3在第二沟槽1B中施加的张应力大于第一沟槽1A中施加的张应力，因此对于NMOS而言器件沟道区宽度方向上施加的高张应力得到了大幅提高从而提高了NMOS沟道区电子的载流子迁移率，而对于PMOS而言虽然并未在器件沟道区长度方向上施加压应力，但是因为其在沟道区宽度方向上也施加了较大的张应力，而部分抵消了PMOS性能的退化，也即NMOS驱动能力的大幅提升弥补了PMOS驱动能力的改善不足而整体上提高了整个IC的驱动能力。
最后，参照图1以及图9、图10，采用回刻或者CMP等技术平坦化绝缘材料3以及硬掩模层2，直至暴露衬底1，形成了最终的浅沟槽隔离3A/3B。其中，STI在第一方向上分布的部分3A的体积要小于在第二方向上分布的部分3B的体积。因此，依照本发明的制造方法形成的浅沟槽隔离，在器件沟道区宽度方向上的体积要大于在器件沟道区长度方向上的体积，以便施加更大的应力。
依照本发明的浅沟槽隔离制造方法，在沟道宽度方向刻蚀填充较深、较宽的浅沟槽隔离，而在沟道长度方向刻蚀填充较浅、较窄的浅沟槽隔离，同时向NMOS和PMOS施加应力，增大其沟道区载流子迁移率，从而提高器件整体驱动能力。
尽管已参照一个或多个示例性实施例说明本发明，本领域技术人员可以知晓无需脱离本发明范围而对形成器件结构的方法做出各种合适的改变和等价方式。此外，由所公开的教导可做出许多可能适于特定情形或材料的修改而不脱离本发明范围。因此，本发明的目的不在于限定在作为用于实现本发明的最佳实施方式而公开的特定实施例，而所公开的器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims (11)

1.一种浅沟槽隔离的制造方法，包括：
在衬底上形成硬掩模层；
光刻/刻蚀硬掩模层和衬底，形成多个第一沟槽和多个第二沟槽，其中，第一沟槽沿第一方向，第二沟槽沿垂直于第一方向的第二方向，并且第二沟槽的体积大于第一沟槽的体积；
在第一和第二沟槽中沉积绝缘材料；
平坦化绝缘材料、硬掩模层直至暴露衬底，形成浅沟槽隔离。
2.如权利要求1的浅沟槽隔离的制造方法，其中，硬掩模层包括氧化硅、氮化硅、氮氧化硅及其组合。
3.如权利要求1的浅沟槽隔离的制造方法，其中，形成多个第一沟槽和多个第二沟槽的步骤进一步包括：光刻/刻蚀硬掩模层形成沿第一方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第一沟槽；光刻/刻蚀硬掩模层形成沿第二方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第二沟槽。
4.如权利要求1的浅槽隔离的制造方法，其中，形成多个第一沟槽和多个第二沟槽的步骤进一步包括：光刻/刻蚀硬掩模层形成沿第二方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第二沟槽；光刻/刻蚀硬掩模层形成沿第一方向的硬掩模图形，直至暴露衬底；刻蚀衬底，形成第一沟槽。
5.如权利要求1的浅沟槽隔离的制造方法，其中，形成多个第一沟槽和多个第二沟槽的步骤进一步包括：光刻/刻蚀硬掩模层形成网格状的硬掩模图形，具有多个沿第一方向以及第二方向的开口；刻蚀衬底，同时形成第一沟槽和第二沟槽。
6.如权利要求1的浅沟槽隔离的制造方法，其中，第二沟槽的宽度大于第一沟槽的宽度。
7.如权利要求1的浅沟槽隔离的制造方法，其中，第二沟槽的深度大于第一沟槽的深度。
8.如权利要求1的浅沟槽隔离的制造方法，其中，绝缘材料包括氧化硅、氮化硅、氮氧化硅、Bi0.95La0.05NiO3、BiNiO3、ZrW2O8。
9.如权利要求1的浅沟槽隔离的制造方法，其中，浅沟槽隔离向衬底施加张应力。
10.如权利要求1的浅沟槽隔离的制造方法，其中，第一方向是器件沟道区宽度方向，第二方向是器件沟道区长度方向。
11.一种半导体器件，包括衬底、衬底中的绝缘材料构成的浅沟槽隔离，其特征在于：第二方向上浅沟槽隔离的体积要大于第一方向上浅沟槽隔离的体积。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633009A (zh) * 2012-08-24 2014-03-12 中国科学院微电子研究所 浅沟槽隔离及其制造方法

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9318574B2 (en) * 2014-06-18 2016-04-19 International Business Machines Corporation Method and structure for enabling high aspect ratio sacrificial gates
US9570457B2 (en) * 2014-08-26 2017-02-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method to control the common drain of a pair of control gates and to improve inter-layer dielectric (ILD) filling between the control gates
KR102463863B1 (ko) * 2015-07-20 2022-11-04 삼성전자주식회사 연마용 조성물 및 이를 이용한 반도체 장치의 제조 방법

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040092115A1 (en) * 2002-11-07 2004-05-13 Winbond Electronics Corp. Memory device having isolation trenches with different depths and the method for making the same
US20070045623A1 (en) * 2005-08-30 2007-03-01 Kabushiki Kaisha Toshiba Semiconductor device that is advantageous in operational environment at high temperatures
CN101593718A (zh) * 2008-05-27 2009-12-02 台湾积体电路制造股份有限公司 形成集成电路结构的方法
US20100123197A1 (en) * 2008-11-17 2010-05-20 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20100176457A1 (en) * 2009-01-14 2010-07-15 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN102456576A (zh) * 2010-10-29 2012-05-16 中国科学院微电子研究所 应力隔离沟槽半导体器件及其形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7119404B2 (en) * 2004-05-19 2006-10-10 Taiwan Semiconductor Manufacturing Co. Ltd. High performance strained channel MOSFETs by coupled stress effects
JP2010141263A (ja) * 2008-12-15 2010-06-24 Toshiba Corp 半導体装置
CN102456577B (zh) * 2010-10-29 2014-10-01 中国科学院微电子研究所 应力隔离沟槽半导体器件的形成方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040092115A1 (en) * 2002-11-07 2004-05-13 Winbond Electronics Corp. Memory device having isolation trenches with different depths and the method for making the same
US20070045623A1 (en) * 2005-08-30 2007-03-01 Kabushiki Kaisha Toshiba Semiconductor device that is advantageous in operational environment at high temperatures
CN101593718A (zh) * 2008-05-27 2009-12-02 台湾积体电路制造股份有限公司 形成集成电路结构的方法
US20100123197A1 (en) * 2008-11-17 2010-05-20 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20100176457A1 (en) * 2009-01-14 2010-07-15 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
CN102456576A (zh) * 2010-10-29 2012-05-16 中国科学院微电子研究所 应力隔离沟槽半导体器件及其形成方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103633009A (zh) * 2012-08-24 2014-03-12 中国科学院微电子研究所 浅沟槽隔离及其制造方法
CN103633009B (zh) * 2012-08-24 2016-12-28 中国科学院微电子研究所 浅沟槽隔离及其制造方法

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