WO2013189160A1 - Substrat de matrice, son procédé de fabrication, substrat de matrice de dispositif d'affichage, son procédé de fabrication et son dispositif d'affichage - Google Patents

Substrat de matrice, son procédé de fabrication, substrat de matrice de dispositif d'affichage, son procédé de fabrication et son dispositif d'affichage Download PDF

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Publication number
WO2013189160A1
WO2013189160A1 PCT/CN2012/086987 CN2012086987W WO2013189160A1 WO 2013189160 A1 WO2013189160 A1 WO 2013189160A1 CN 2012086987 W CN2012086987 W CN 2012086987W WO 2013189160 A1 WO2013189160 A1 WO 2013189160A1
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WO
WIPO (PCT)
Prior art keywords
photoresist
film
gate
substrate
source
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PCT/CN2012/086987
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English (en)
Chinese (zh)
Inventor
高涛
李太亮
吕志军
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京东方科技集团股份有限公司
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Publication of WO2013189160A1 publication Critical patent/WO2013189160A1/fr

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • Thin Film Transistor Liquid Crystal Display has the advantages of small size, low power consumption, no radiation, and has dominated the current flat panel display market.
  • the existing thin film transistor array substrate is prepared by first depositing a metal film layer and various non-metal film layers on a glass substrate by plasma enhanced chemical precipitation (PECVD) and magnetron sputtering (Sputter), and then applying photolithography.
  • PECVD plasma enhanced chemical precipitation
  • Sputter magnetron sputtering
  • the adhesive is subjected to an exposure process using a mask to obtain a desired thin film transistor array substrate structure.
  • the fabrication of the source and drain electrodes of all TFTs is fully aligned by the alignment marks on the respective corners of the device alignment, and the alignment accuracy of such alignment method is achieved.
  • the size of the thin film transistor is extremely small, as small as a few microns, so it is extremely difficult to align the source and drain electrodes with the gate by using the alignment mark of the mask, thus causing the underlying gate and source.
  • the principle of TFT conduction is to apply a lead voltage between the source and the gate, and charge the pixel electrode through the semiconductor channel to display color.
  • the capacitance of the TFT C gs + C trench + Cg d , where C gs is the capacitance of the gate and source overlap, Cg d is the capacitance of the gate and drain overlap, and ⁇ £ can be 0, ideal
  • C gs C.
  • C gs C.
  • C gs is not equal to Cg d , resulting in inconsistent capacitance of each TFT.
  • the voltages of the pixels are inconsistent, causing a mura phenomenon of the display.
  • the overlap between the source-drain electrodes and the gate of the semiconductor layer is increased in the design of the mask to ensure even In Appropriate overlap can also be achieved in the case of the largest misalignment. This not only increases the source-drain and gate of the device.
  • An aspect of an embodiment of the present invention provides a method for fabricating an array substrate, comprising the steps of: forming a pattern including a gate and a gate line on a substrate;
  • a pattern including a source/drain electrode, a data line, a channel, a passivation layer, and a via hole on a substrate on which the gate insulating layer and the semiconductor layer are formed;
  • a pattern of pixel electrodes is formed on a substrate on which the source/drain electrodes, the data lines, and the passivation layer are formed.
  • the pattern of the gate insulating layer and the semiconductor layer is formed on the substrate on which the gate electrode and the gate line are formed, and the trench is determined by gate back exposure over the semiconductor layer
  • the steps of the road area include:
  • the gate is formed on the substrate on which the gate and the gate line are formed a step of patterning the insulating layer and the semiconductor layer, and determining a channel region by gate back exposure over the semiconductor layer, comprising:
  • the gate corresponding region has a first thickness a photoresist, the other region having a second thickness of the photoresist, the first thickness being greater than the second thickness; Etching off the exposed semiconductor film to form a pattern of the semiconductor layer;
  • the photoresist of the second thickness is ashed, and a portion of the photoresist having a first thickness is retained to define a channel region.
  • the photoresist coated on the semiconductor film in this step is a positive photoresist.
  • the pattern width of the semiconductor layer is greater than the pattern width of the gate.
  • the step of forming a pattern of source/drain electrodes, data lines, trenches, passivation layers, and via holes on a substrate on which the gate insulating layer and the semiconductor layer are formed includes : sequentially forming a doped semiconductor film, a source/drain electrode metal film on the substrate on which the gate insulating layer and the semiconductor layer are formed;
  • the photoresist of the drain, the data line and the channel region has a first thickness
  • the photoresist of the pixel electrode and the drain contact region in the drain region at the via has a second thickness, and the second thickness is less than the first thickness Removing a photoresist of other regions by a developing process, and etching away a passivation layer film, a source/drain electrode metal film, and a doped semiconductor film without a photoresist region;
  • the remaining photoresist is ashed, a second thickness of photoresist at the pixel electrode and drain contact regions at the via is removed, the exposed passivation film is etched, and the remaining photoresist is stripped.
  • the step of forming a pattern of source/drain electrodes, data lines, trenches, passivation layers, and via holes on a substrate on which the gate insulating layer and the semiconductor layer are formed includes Forming a doped semiconductor film, a source/drain electrode metal film, and a passivation layer film sequentially on the substrate on which the gate insulating layer and the semiconductor layer are formed;
  • a photoresist remaining over the semiconductor layer to define a channel region, and a doped semiconductor film, a source/drain electrode metal film, and a passivation layer film overlying the photoresist to form a trench;
  • a photoresist is coated on the passivation layer film, and the photoresist on the passivation layer film is exposed and developed with a two-tone mask to make the photoresist of the source, drain and channel regions have a first thickness.
  • the photoresist of the pixel electrode and the drain contact region in the drain region has a second thickness, the second thickness is smaller than the first thickness, the photoresist is removed from other regions by the developing process, and the photoresist-free region is etched away.
  • the remaining photoresist is ashed, a second thickness of the photoresist is removed from the pixel electrode and the drain contact region, the exposed passivation film is etched, and the remaining photoresist is stripped.
  • the step of forming a pattern of the pixel electrode on the substrate on which the source/drain electrode, the data line and the passivation layer are formed includes:
  • Another aspect of the embodiment of the present invention further provides an array substrate fabricated by the above array substrate fabrication method.
  • Still another aspect of an embodiment of the present invention provides a display device including the above array substrate.
  • the gate is exposed from the back of the glass substrate by using the gate as a mask, and the channel region is accurately determined, so that an array of thin film transistors in which the gate and the source and drain electrodes are self-aligned is obtained in the subsequent fabrication process.
  • the substrate makes the alignment between the gate and the source and drain electrodes more accurate, thereby reducing the crosstalk between the source and drain electrodes and the gate, and avoiding the chromaticity unevenness of the liquid crystal display due to the uneven capacitance.
  • the phenomenon Moreover, the method requires only four masking techniques to implement the TFT process, which improves production efficiency and saves costs.
  • FIG. 1 is a cross-sectional view showing a substrate formed by exposing a first mask in an array substrate manufacturing method according to an embodiment of the present invention
  • FIG. 2 is a cross-sectional view showing a structure formed by using a gate as a mask and back exposure on the basis of the substrate of FIG. 1;
  • 3 is a cross-sectional view showing a structure formed by back exposure with a two-tone mask on the basis of the substrate of FIG. 1;
  • 4 is a cross-sectional view showing a doped semiconductor film and a source/drain electrode metal film deposited on the photoresist of the substrate of FIG. 2;
  • Figure 5 is a cross-sectional view showing a structure formed by peeling off the photoresist on the substrate of Figure 4;
  • Figure 6 is a cross-sectional view showing a film of a passivation layer deposited on the substrate of Figure 5;
  • FIG. 7 is a cross-sectional view showing the source/drain electrodes, the data lines, and the passivation layer formed by etching the substrate of FIG. 6 using a two-tone mask;
  • Figure 8 is a cross-sectional view showing the pixel electrode in contact with the source/drain contact region on the substrate of Figure 7; and Figure 9 is a cross-sectional view showing the pixel electrode formed on the substrate of Figure 8.
  • Embodiments of the present invention provide a method for fabricating an array substrate, including the following steps:
  • a pattern including a source/drain electrode, a data line, a channel, a passivation layer, and a via hole on a substrate on which the gate insulating layer and the semiconductor layer are formed;
  • a pattern of pixel electrodes is formed on a substrate on which the source/drain electrodes, the data lines, and the passivation layer are formed.
  • the gate is exposed from the back of the glass substrate by using the gate as a mask, and the channel region is accurately determined, so that an array of thin film transistors in which the gate and the source and drain electrodes are self-aligned is obtained in the subsequent fabrication process.
  • the substrate makes the alignment between the gate and the source and drain electrodes more accurate, thereby reducing the crosstalk between the source and drain electrodes and the gate, and avoiding the chromaticity unevenness of the liquid crystal display due to the uneven capacitance.
  • the phenomenon Moreover, the method requires only four masking techniques to implement the TFT process, which improves production efficiency and saves costs.
  • Step 1 Form a pattern including a gate and a gate line on the substrate.
  • a gate metal film is deposited on the glass substrate 1 (or the quartz substrate) by a magnetron sputtering device (Sputter), the film thickness is 1500 A 2500 A, and the gate metal film may be Mo, Al, Cu or A metal such as W, or a multilayer film formed by multilayer deposition of these metals.
  • a photoresist is coated on the gate metal film, and the photoresist is exposed and developed through the mask to retain the photoresist in the gate pattern region A, and the exposed gate metal film is removed by wet etching, and stripped. The remaining photoresist, as shown in Fig. 1, forms a gate 2 and a gate line (the gate lines are not shown, and a common electrode is usually also formed).
  • Step 2 forming a pattern of a gate insulating layer and a semiconductor layer on the substrate on which the gate electrode 2 and the gate line are formed, and determining a channel region by gate back exposure over the semiconductor layer. Specifically, the following two methods are included:
  • Method 1 includes the following steps:
  • the photoresist of the semiconductor layer pattern region from the back surface of the substrate is specifically deposited by plasma enhanced chemical vapor deposition (PECVD) on the glass substrate 1 on which the gate and gate lines are formed.
  • PECVD plasma enhanced chemical vapor deposition
  • the gate insulating film may be made of a material such as silicon nitride (SiN x ) or silicon oxide (SiO x ), or a multilayer film formed by multilayer deposition of these materials, having a thickness of 2500A 4000A, corresponding to etching.
  • the reaction gas may be Si3 ⁇ 4, N3 ⁇ 4, N 2 or a mixed gas Si3 ⁇ 4Cl 2, N3 ⁇ 4, N 2 gas mixture.
  • the thickness of the semiconductor thin film is 800 A -1500 A, corresponding to the reaction gas during the etching can be Si3 ⁇ 4, or a mixed gas 3 ⁇ 4 Si3 ⁇ 4Cl 2, a mixed gas of 3 ⁇ 4.
  • the remaining photoresist 5 is exposed and developed from the back surface of the glass substrate 1 by using the gate electrode 2 as a mask.
  • the mask is not used in this exposure, and the mask is masked by the opaque action of the gate metal, leaving only the corresponding gate.
  • the photoresist 5 over the pole 2, as shown in FIG. 2 forms the gate insulating layer 3 and the semiconductor layer 4, and also defines a region where the channel is formed later, that is, the gate region A.
  • the pattern width of the semiconductor layer is larger than the pattern width of the gate.
  • a positive photoresist is used, and in the first exposure development of the positive photoresist, the photoresist of the region B is retained; and the photoresist of the region B is gate 2
  • the portion of the region B from which the region A is removed is irradiated to be removed in the developing process.
  • Mode 2 includes the following steps:
  • the second thickness of photoresist is ashed, leaving a first thickness of photoresist to define the channel region.
  • the gate insulating layer film and the semiconductor film are deposited by PECVD on the glass substrate 1 on which the gate electrode and the gate line are formed, and the deposition process of the gate insulating layer film and the semiconductor film are similar in the specific process and deposition.
  • a photoresist 5 is coated on the substrate on which the gate insulating layer and the semiconductor layer film are deposited, and a lithography is performed from the back surface of the substrate by using a two-tone mask (halftone or gray tone mask).
  • the adhesive 5 is exposed and developed, and the two-tone mask completely obscures the entire A region, that is, the A region is a completely reserved region of the photoresist, and at the same time, the photoresist 5 corresponding to the region B of the semiconductor layer pattern is partially retained (the B region other than the A region)
  • the B region other than the A region is a photoresist partial retention region
  • the photoresist other than the A region and the B region is a completely removed region, that is, the photoresist of other regions is completely removed by the development process.
  • a positive photoresist can be used.
  • the glass substrate 1, the gate insulating film, and the semiconductor film are both light-transmitting materials, and the region A is an opaque region, so The photoresist 5 of the gate region A is completely retained, The photoresist 5 having the first thickness; the semi-transmissive region, that is, the region other than the region A in the region B, partially retained as the photoresist 5 having the second thickness, and the first thickness is greater than the second thickness.
  • the gate electrode 2 may be formed of a transparent conductive metal layer or an opaque conductive metal layer. Further, for example, when the gate 2 is transparent or nearly transparent, a negative photoresist can be used in the mode 2.
  • the exposed semiconductor film is etched away to form a pattern of the semiconductor layer, as shown in FIG.
  • the second thickness of the photoresist 5, that is, the photoresist of the B region, is partially ashed, while partially retaining the photoresist of the A region, that is, the photoresist 5 of the first thickness is thinned to be partially retained to determine the channel. region.
  • the pattern width of the semiconductor layer is larger than the pattern width of the gate.
  • Step 3 forming a pattern including source and drain electrodes, data lines, trenches, passivation layers, and via holes on the substrate on which the gate insulating layer 3 and the semiconductor layer 4 are formed. There are two ways to do this:
  • Method 1 includes the following steps:
  • the photoresist of the drain, the data line and the channel region has a first thickness
  • the photoresist of the pixel electrode and the drain contact region in the drain region at the via has a second thickness, and the second thickness is less than the first thickness Removing a photoresist of other regions by a developing process, and etching away a passivation layer film, a source/drain electrode metal film, and a doped semiconductor film without a photoresist region;
  • the remaining photoresist is ashed, a second thickness of photoresist at the pixel electrode and drain contact regions at the via is removed, the exposed passivation film is etched, and the remaining photoresist is stripped.
  • a doped semiconductor film is deposited by PECVD to a thickness of 500 A to 1000 A, and then the source and drain electrode metal are deposited by sputtering or thermal evaporation.
  • the film has a thickness of 2000 ⁇ 3000 ⁇ .
  • the material can be selected from ⁇ , Al, Cu, W, etc., or a multilayer film formed by depositing multiple layers of these metals.
  • the substrate on which the above film layer is formed is as shown in FIG. 4, and a part of the doped semiconductor film and the source/drain electrode metal film are directly deposited on the photoresist 5. Further, the doped semiconductor film is for reducing the ohmic contact resistance of the source electrode, the drain electrode and the semiconductor layer. If the characteristics of the semiconductor material can meet the requirements of the product, the doped semiconductor film can be omitted.
  • the photoresist is stripped, so that the protruding photoresist 5 on the semiconductor layer and facing the gate region A can be removed, so that during the process of removing the photoresist 5, the photolithography is performed.
  • the doped semiconductor film and the source/drain electrode metal film on the paste 5 are also simultaneously removed, thereby obtaining a TFT channel structure of the self-aligned gate, as shown in FIG. The exact alignment of the self-aligned gate with the channel makes the channel region more accurate.
  • a passivation film is deposited by PECVD to a thickness of 1000A 3000A, and the material may be SiN x or SiO x , or multiple layers of these materials.
  • a photoresist is coated on the passivation layer, and the photoresist is exposed and developed by a two-tone mask (gray tone or halftone mask) to make the source region C and the drain region 0.
  • the photoresist of the data line region (not shown) and the channel region A (ie, the gate region) are completely retained, have a first thickness, and the pixel electrode and the drain contact region E in the drain region D
  • the photoresist portion is retained, has a second thickness, and the second thickness is less than the first thickness, and the other regions are photoresist completely removed regions, and the photoresist of other regions is removed by development.
  • the passivation layer film, the source/drain electrode metal film and the doped semiconductor film without the photoresist region are sequentially etched by one wet etching and two dry etching, and the etched substrate is as shown in FIG.
  • a doped semiconductor layer 6, a source 7a, a data line (not shown), a drain 7b, and a passivation layer 8 are formed to protect the channel.
  • the photoresist is ashed on the substrate formed as shown in FIG. 7, and the photoresist having the second thickness of the pixel electrode and the drain contact region E is removed, and then etched, such as The dry etching etches away the passivation layer film of the region E, thereby obtaining a contact surface of the drain electrode 7b and the pixel electrode on the drain, that is, a via hole, so that the subsequently formed pixel electrode is connected to the drain electrode 7b.
  • Mode 2 includes the following steps:
  • the remaining photoresist is ashed, a second thickness of the photoresist is removed from the pixel electrode and the drain contact region, the exposed passivation film is etched, and the remaining photoresist is stripped.
  • a doped semiconductor film is deposited by PECVD on the substrate on which the gate insulating layer 3 and the semiconductor layer 4 are formed; and the source/drain electrode metal film is deposited on the doped semiconductor film by sputtering or thermal evaporation.
  • a passivation film is deposited on the source-drain electrode metal film by PECVD. A total of three layers of film are deposited, and the thickness, material and mode of the deposited film are similar.
  • a partially doped semiconductor film, a source and drain electrode metal film, and a passivation layer film are directly deposited on the photoresist
  • the doped semiconductor film is used for reducing the ohmic contact resistance of the source electrode, the drain electrode and the semiconductor layer. If the characteristics of the semiconductor material can satisfy the requirements of the product, the doped semiconductor film can be omitted.
  • the photoresist is stripped, so that the protruding photoresist 5 on the semiconductor layer and facing the gate region A can be removed, so that during the process of removing the photoresist 5, the photolithography is performed.
  • the doped semiconductor film, the source/drain electrode metal film and the passivation layer film on the paste 5 are also simultaneously removed, thereby obtaining a TFT channel structure of the self-aligned gate.
  • the photoresist (not shown) and the channel region A (ie, the gate region) have a first thickness, and the pixel electrode and the drain contact region E in the drain region D (ie, the photoresist portion retention region)
  • the photoresist has a second thickness, and the second thickness is smaller than the first thickness, and the other regions are photoresist completely removed regions, and the photoresist is removed from other regions by a developing process.
  • the passivation layer film, the source/drain electrode metal film and the doped semiconductor film without the photoresist region are sequentially etched by an etching process, such as one-time wet etching and two dry etching, and the etched substrate Similar to the structure shown in FIG. 7, that is, the doped semiconductor layer 6, the source 7a, the data line (not shown), the drain 7b, and the passivation layer 8 are formed, except that in this mode The medium passivation layer 8 is not present in the channel region A.
  • the partially retained photoresist is ashed to remove the pixel electrode and drain contact region E. a photoresist having a second thickness, and then performing dry etching to etch away the passivation layer film of the region E, thereby obtaining a contact surface of the drain electrode 7b and the pixel electrode on the drain, that is, a via hole, so as to The fabricated pixel electrode is connected to the drain 7b.
  • Step 4 forming a pattern of the pixel electrode on the substrate on which the source electrode 7a, the drain electrode 7b, the data line, the passivation layer 8 and the via hole are formed.
  • a transparent conductive film is deposited by a magnetron sputtering device (Sputter), and the composition may be indium tin oxide (ITO), indium oxide (IZO) or alumina, and the thickness is 500A to 1500A.
  • the photoresist is coated, and the photoresist is exposed and developed by using a common mask, the photoresist of the pixel electrode region F is retained, the photoresist of other regions is removed, and the etching is performed by wet etching.
  • the transparent conductive film is exposed to form the pixel electrode 10, thereby completing the fabrication of the array substrate, and the fabricated array substrate is as shown in FIG.
  • the above fabrication process uses a gate as a mask in Step 2 to expose from the back of the glass substrate, and in step 3, a method of depositing a film layer and then stripping the photoresist is performed to obtain self-aligned gate and source and drain electrodes.
  • the array substrate of the thin film transistor makes the alignment between the gate and the source and drain electrodes more accurate, thereby reducing the crosstalk between the source and drain electrodes and the gate, and avoiding the liquid crystal display caused by the uneven capacitance.
  • the phenomenon of uneven chromaticity is achieved.
  • only four times one in step 1, one in step 2, one in step 3, and one in step 4) mask technology can realize the TFT process, which improves production efficiency and saves cost.
  • This embodiment provides an array substrate prepared by the method of Embodiment 1.
  • the array substrate includes a substrate 1 and a gate electrode, a gate insulating layer, a source/drain, a passivation layer, and a pixel electrode formed over the substrate 1.
  • the self-alignment method is used to make the alignment chromaticity uneven between the gate and the source and drain electrodes, thereby providing the yield of the array substrate.
  • Example 3 The embodiment provides a display device, and the display device includes the array substrate prepared by using the preparation method in Embodiment 1.
  • the display device can be: a liquid crystal panel, an electronic paper, an OLED panel, a liquid crystal television, a liquid crystal display, or a digital photo frame. Any product or component that has a display function, such as a mobile phone or a tablet.
  • the display device of the present embodiment includes the array substrate prepared by the method of the first embodiment.
  • the self-aligned method of gate back exposure is used, and the gate is used as a mask to expose the back surface of the substrate to make the gate and
  • the alignment between the source and drain electrodes is more accurate, and the chromaticity unevenness of the liquid crystal display caused by the uneven capacitance between the source and drain electrodes and the gate is avoided, thereby providing the yield of the array substrate.

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  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
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Abstract

Cette invention concerne un procédé de fabrication d'un substrat de matrice, un substrat de matrice et un dispositif d'affichage. Ledit procédé de fabrication de substrat de matrice comprend les étapes consistant à : former les motifs d'une électrode de grille (2) et d'une ligne de grille sur un panneau de base (1); former le motif d'une couche d'isolation de grille (3) et d'une couche de semi-conducteur (4) sur le panneau de base (1) sur lequel est fixée l'électrode de grille (2) et la ligne de grille, et ménager une région de canal au-dessus de la couche de semi-conducteur (2) par exposition dorsale. Ladite formation de motifs concerne une électrode source et une électrode drain (7a, 7b), une ligne de données, un canal, une couche de passivation (8) et un orifice traversant sur le panneau de base (1) sur lequel est fixée la couche d'isolation de grille (3) et la couche de semi-conducteur (4). Ledit procédé comprend en outre l'étape consistant à former un motif d'électrode de pixel (10).
PCT/CN2012/086987 2012-06-21 2012-12-20 Substrat de matrice, son procédé de fabrication, substrat de matrice de dispositif d'affichage, son procédé de fabrication et son dispositif d'affichage WO2013189160A1 (fr)

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Application Number Priority Date Filing Date Title
CN201210211811.7 2012-06-21
CN201210211811.7A CN102723269B (zh) 2012-06-21 2012-06-21 阵列基板及其制作方法、显示装置

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WO2018178657A1 (fr) * 2017-03-31 2018-10-04 Pragmatic Printing Ltd Structures électroniques et leurs procédés de fabrication
CN111403261A (zh) * 2019-01-03 2020-07-10 上海先进半导体制造股份有限公司 减薄硅片的方法
CN111584523A (zh) * 2020-05-25 2020-08-25 成都中电熊猫显示科技有限公司 阵列基板、显示面板以及阵列基板的制作方法
CN111613577A (zh) * 2020-05-28 2020-09-01 深圳市华星光电半导体显示技术有限公司 阵列基板制备方法和半透光光罩
CN111726101A (zh) * 2019-03-20 2020-09-29 深圳市麦捷微电子科技股份有限公司 一种tc-saw器件及其制造方法
CN111883582A (zh) * 2020-07-30 2020-11-03 北海惠科光电技术有限公司 一种栅极、薄膜晶体管的制作方法和显示面板
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