WO2013170725A1 - 半导体器件制造方法及半导体器件 - Google Patents

半导体器件制造方法及半导体器件 Download PDF

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WO2013170725A1
WO2013170725A1 PCT/CN2013/075453 CN2013075453W WO2013170725A1 WO 2013170725 A1 WO2013170725 A1 WO 2013170725A1 CN 2013075453 W CN2013075453 W CN 2013075453W WO 2013170725 A1 WO2013170725 A1 WO 2013170725A1
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layer
metal layer
semiconductor device
mark
functional
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PCT/CN2013/075453
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English (en)
French (fr)
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杨鑫
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无锡华润上华科技有限公司
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Priority to US14/130,482 priority Critical patent/US9040410B2/en
Publication of WO2013170725A1 publication Critical patent/WO2013170725A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/708—Mark formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to semiconductor technology, and more particularly to a semiconductor device manufacturing method and a semiconductor device. Background technique
  • Marking methods include ink marking and laser marking, which can be formed on the front or back side of the wafer, and the marks formed on the back side of the wafer are easily peeled off or worn out and become unreadable. Therefore, forming a mark on the front side of the wafer is a better solution.
  • the conventional technique Since the mark mark is formed on the front side of the wafer, to keep it readable, the conventional technique also exposes the mark mark in each level of the lithography process. In addition, after the lithography and edge-washing operations of the subsequent layers, the thickness of the area near the mark mark tends to become uneven in thickness, and when the photolithography is performed by the same mask, the pattern projected to the area is focused. The defect (defocus), so that the wafer in this area is very easy to fail.
  • the traditional solution is to fine-tune the exposure of the engraved mark so that it is as close as possible to the edge of the wafer, reducing the area of focus defects.
  • this does not completely solve the problem of focusing defects.
  • a semiconductor device manufacturing method comprising: a deposition step of a dielectric layer of a plurality of functional layers, a forming step of a contact hole or a via hole, and a forming step of a metal layer, the step of forming a contact hole or a via hole and a step of forming a metal layer And the step of performing lithographic exposure on the dielectric layer and the metal layer corresponding to the area of the mark mark lithography, wherein the step of performing lithographic exposure on the area corresponding to the mark mark lithography on the at least one functional layer Only for the metal layer.
  • the lithographic exposure step only for the metal layer is performed on at least two functional layers of the plurality of functional layers sequentially inward from the outermost layer.
  • a semiconductor device comprising a silicon substrate, a silicon oxide layer formed on the silicon substrate, a metal layer formed on the silicon oxide layer, and a plurality of functional layers formed on the metal layer, each functional layer Each includes a dielectric layer and a metal layer which are sequentially stacked, and the silicon substrate is provided with a mark, and among the least one of the plurality of functional layers, only the area corresponding to the mark on the metal layer is Lithography.
  • the functional layer on which only the region corresponding to the engraved mark on the metal layer is photolithographically is at least two functional layers sequentially inward from the outermost layer.
  • the thickness of the corresponding dielectric layer is maintained, so that the device is thinned to a lesser extent, and the focus defect can be reduced.
  • DRAWINGS 1 is a cross-sectional view of a semiconductor device having a two-layer interconnect structure
  • Figure 2 is a schematic diagram showing the principle of thinning of the device in the vicinity of the mark.
  • FIG. 1 a cross-sectional view of a semiconductor device having a two-layer interconnect structure.
  • the semiconductor device 10 includes a first layer 110 and a second layer 120 which are sequentially stacked, and the first layer 110 and the second layer 120 are interconnected.
  • the first layer 110 includes a silicon substrate 111, a silicon oxide layer 112 formed on the surface of the silicon substrate 111, and a first metal layer 113 formed on the silicon oxide layer 112.
  • the silicon oxide layer 112 has a plurality of contact holes 114.
  • the contact holes 114 are filled with a metal filled in the metallization process, so that the first metal layer 113 is electrically connected to the silicon substrate 111.
  • a numbered mark 130 is also disposed on the silicon substrate 111, and the numbered mark 130 may include a plurality of and are generally disposed on the outer edge of the wafer.
  • the second layer 120 includes a first dielectric layer 121 formed on the first metal layer 113 and a second metal layer 122 formed on the first dielectric layer 121.
  • the first dielectric layer 121 has a plurality of vias 123.
  • the vias 123 are filled with a metal filled in the metallization process, so that the second metal layer 122 is electrically connected to the first metal layer 113.
  • dielectric layers and metal layers can be stacked on the basis of the second layer 120, and finally a protective layer is added.
  • a method of fabricating a semiconductor device includes the steps of forming the first layer 110 and the second layer 120 or more described above.
  • the first layer 110, the second layer 120 or more are referred to as functional layers, and the basic structure of the semiconductor device is formed in each functional layer.
  • the surface of the silicon substrate 111 is formed into a silicon oxide layer 112 by a thermal oxidation method or the like.
  • Contact holes 114 are then formed on the silicon oxide layer 112 by photolithographic exposure, followed by metallization to form the first metal layer 113.
  • the second layer 120 includes a dielectric layer (for the second layer 120, the first dielectric layer 121), first a layer of the deposited dielectric, and then exposed to the dielectric layer by lithographic exposure.
  • a via hole 123 is formed thereon, followed by metallization to form the second metal layer 122.
  • the other layers are formed including the deposition step of the dielectric layer, the formation of the via holes, and the formation step of the metal layer.
  • a lithographic exposure operation is required in the area corresponding to the engraved mark 130 on the dielectric layer or the metal layer.
  • the step of performing the lithographic exposure operation on the dielectric layer or the metal layer corresponding to the region of the mark mark 130 is only for the metal layer. That is, when the metal layer pattern is formed, the lithographic exposure operation is also performed on the region of the metal layer corresponding to the mark mark 130, so that the mark mark 130 is not blocked by the metal layer.
  • several layers in the outer layer are selected, ie at least two layers in the plurality of layers, in order from the outermost layer Perform the above steps.
  • the other layers are marked with the mark on the dielectric and metal layers in each layer in the traditional way.
  • the corresponding areas of 130 are subjected to a lithographic exposure operation.
  • This preferred embodiment is capable of balancing the alignment of the indicia 130 and the inconsistency of the silicon substrate 111 near the engraved mark 130. ⁇ ⁇ , to ensure that the mark 130 is accurately read to a large extent, and the thickness is reduced as much as possible.
  • FIG. 2 it is a schematic diagram of the thinning of the device in the vicinity of the mark.
  • the area corresponding to the engraved mark is thinned during lithographic exposure, and the entire device is thinned.
  • the thickness thereof can be maintained, so that the effect of the embodiment is obvious, and since the dielectric layer is transparent, even after the multilayer is superimposed, the reading of the mark mark is affected. Also small.
  • the semiconductor device formed according to the above method has the following features: Among the least one functional layers of the plurality of functional layers, only the region corresponding to the mark mark on the metal layer is photolithographically. And preferably, the functional layer on which only the region corresponding to the engraved mark on the metal layer is photolithographically is at least two functional layers sequentially inward from the outermost layer.
  • the semiconductor device is less likely to fail.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

提供了一种半导体器件（10）的制造方法，该方法包括多个功能层（110、120）的介质层（112、121）的积淀步骤、接触孔（114）或通孔（123）的形成步骤以及金属层（113、122）的形成步骤，所述接触孔（114）或通孔（123）形成步骤和金属层（113、122）的形成步骤中，包括对介质层（112、121）和金属层（113、122）上与刻号标记（130）光刻对应的区域进行光刻曝光的步骤，在至少一个功能层（110、120）上，所述对与刻号标记（130）光刻对应的区域进行光刻曝光的步骤仅针对所述金属层（113、122）。以及由上述方法得到的半导体器件（10）。所述方法及器件既不影响刻号标记（130）的读取，也能够避免刻号标记（130）附近区域聚焦缺陷的问题。

Description

半导体器件制造方法及半导体器件
技术领域
本发明涉及半导体技术， 特别是涉及一种半导体器件制造方法以及一种半导体器件。 背景技术
在半导体的制程中， 特别是在晶圆上的光刻流程中， 为了标记和区分晶圆， 需要在晶圆 上打上刻号标记。 打标的方法包括油墨标记和激光标记， 可以形成在晶圆的正面或背面， 形 成在晶圆背面的标记容易脱落或磨损而变得不可读取。 因此将刻号标记形成在晶圆正面是一 个较好的解决方法。
由于刻号标记是在晶圆正面形成， 要使其保持可读取的状态， 传统技术在每一层次的光 刻制程中， 都对该刻号标记也进行曝光处理。 加上经过后面层次的光刻及洗边等操作， 刻号 标记附近的区域厚度往往会变得厚度不均， 在采用同一掩膜板进行光刻时， 会导致投射到该 区域的图形产生聚焦缺陷 （defocus ) , 从而该区域内的晶片非常容易失效。
传统的解决方法是微调对刻号标记曝光的范围， 使其尽可能靠近晶圆的边缘， 减小聚焦 缺陷的区域。 然而这并没有彻底解决聚焦缺陷的问题。
发明内容
基于此， 有必要提供一种能够减少聚焦缺陷的半导体器件制造方法。
一种半导体器件制造方法， 包括多个功能层的介质层的积淀步骤、 接触孔或通孔的形成 步骤以及金属层的形成步骤， 所述接触孔或通孔形成步骤和金属层的形成步骤中， 包括对介 质层和金属层上与刻号标记光刻对应的区域进行光刻曝光的步骤， 在至少一个功能层上， 所 述对与刻号标记光刻对应的区域进行光刻曝光的步骤仅针对所述金属层。
在其中一个实施例中， 所述多个功能层中从最外层依次向内的至少两层功能层执行所述 仅针对所述金属层的光刻曝光步骤。
一种半导体器件， 包括硅衬底、 形成于硅衬底上的硅氧化层、 形成于硅氧化层上的金属 层以及形成于所述金属层上的多个功能层， 所述每一功能层都包括依次层叠的介质层和金属 层， 所述硅衬底上设有刻号标记， 所述多个功能层中的最少一个功能层中， 仅在金属层上与 刻号标记相应的区域被光刻。
在其中一个实施例中， 所述仅金属层上与刻号标记相应的区域被光刻的功能层为从最外 层依次向内的至少两层功能层。
上述方法和器件， 由于在至少一个功能层上， 仅金属层被光刻曝光， 相应的介质层的厚 度则被维持， 从而器件变薄的程度较小， 能够减少聚焦缺陷。
附图说明 图 1为一种两层互连结构的半导体器件的剖视图；
图 2为器件在刻号标记附近区域变薄的原理示意图。
具体实施方式
如图 1所示， 是一种两层互连结构的半导体器件的剖视图。该半导体器件 10包括依次层 叠的第一层 110及第二层 120， 第一层 110及第二层 120之间互连。
第一层 110包括硅衬底 111、形成于硅衬底 111表面的硅氧化层 112以及形成于硅氧化层 112上的第一金属层 113。 其中硅氧化层 112上具有多个接触孔 （contact) 114, 接触孔 114 中填充有在金属化过程填入的金属，从而第一金属层 113与硅衬底 111电性连接。硅衬底 111 上还设置刻号标记 130， 该刻号标记 130可以包括多个且一般设置在晶圆的外缘。
第二层 120包括形成于第一金属层 113上的第一介质层 121 以及形成于第一介质层 121 上的第二金属层 122。 其中第一介质层 121上具有多个通孔（via) 123, 通孔 123中填充有在 金属化过程填入的金属， 从而第二金属层 122与第一金属层 113电性连接。
对于更多层次的半导体器件， 可以在第二层 120的基础上叠加更多的介质层及金属层， 最后添加保护层等。
提供一种制造半导体器件的方法， 其包括形成上述的第一层 110和第二层 120或者更多 层次的步骤。 第一层 110、 第二层 120或更多层次都称为功能层， 每个功能层中形成半导体 器件的基本结构。
对于第一层 110， 其不包括介质层， 硅衬底 111表面通过热氧化法等方法形成硅氧化层 112。 然后通过光刻曝光的方式在硅氧化层 112上形成接触孔 114， 继而进行金属化形成第一 金属层 113。
对于第二层 120或者其后更多的层次， 其包括介质层 （对第二层 120来说， 是第一介质 层 121 )， 首先是积淀介质层， 然后通过光刻曝光的方式在介质层上形成通孔 123， 继而进行 金属化形成第二金属层 122。
因而上述过程中， 除第一层 110， 其他层次形成时都包括介质层的积淀步骤、 通孔的形 成步骤以及金属层的形成步骤。
为了使刻号标记 130可读取， 在介质层或金属层上与刻号标记 130相应的区域， 需要进 行光刻曝光操作。
本实施例的方法中， 上述在介质层或金属层上与刻号标记 130相应的区域进行光刻曝光 操作的步骤仅针对金属层。 也即， 在形成金属层图形时， 也对金属层上与刻号标记 130相应 的区域进行光刻曝光操作， 从而使得刻号标记 130不被金属层遮挡。
在优选的实施例中， 选择处于外层的几层， 即多个层次中从最外层依次向内的至少两层 执行上述步骤。 而其他的层次则按照传统的方式对每一层中的介质层和金属层上与刻号标记
130相应的区域均进行光刻曝光操作。 该优选的实施例能够平衡刻号标记 130准确读取和硅 衬底 111在刻号标记 130附近变薄的矛盾。 δΡ， 既要在较大程度上满足刻号标记 130被准确 读取， 也要尽可能地减小厚度变薄。
当然， 选择执行单独对金属层进行光刻曝光操作的层次还可以有其他的方式， 例如隔层 选取等。 选择的层次的位置或者数量可以根据实验确定， 并不限于上述的选择方式。
如图 2所示， 是器件在刻号标记附近区域变薄的原理示意图。 多层介质层上在与刻号标 记对应的区域光刻曝光时会变薄， 累积下来整个器件就会变薄。 根据该示意图可知， 如果不 对介质层进行光刻曝光操作， 则可以维持其厚度， 因而本实施例的效果显而易见， 同时由于 介质层为透明， 即使多层叠加后， 对刻号标记的读取影响也较小。
根据上述方法形成的半导体器件则具有如下特点： 在所述多个功能层的最少一个功能层 中， 仅在金属层上与刻号标记相应的区域被光刻。 并且优选地， 所述仅金属层上与刻号标记 相应的区域被光刻的功能层为从最外层依次向内的至少两层功能层。
该半导体器件失效的可能性较小。
以上所述实施例仅表达了本发明的几种实施方式， 其描述较为具体和详细， 但并不能因 此而理解为对本发明专利范围的限制。 应当指出的是， 对于本领域的普通技术人员来说， 在 不脱离本发明构思的前提下， 还可以做出若干变形和改进， 这些都属于本发明的保护范围。 因此， 本发明专利的保护范围应以所附权利要求为准。

Claims

权利要求书
1、 一种半导体器件制造方法， 包括多个功能层的介质层的积淀步骤、接触孔或通孔的形 成步骤以及金属层的形成步骤， 所述接触孔或通孔形成步骤和金属层的形成步骤中， 包括对 介质层和金属层上与刻号标记光刻对应的区域进行光刻曝光的步骤， 其特征在于， 在至少一 个功能层上， 所述对与刻号标记光刻对应的区域进行光刻曝光的步骤仅针对所述金属层。
2、根据权利要求 1所述的半导体器件制造方法， 其特征在于， 所述多个功能层中从最外 层依次向内的至少两层功能层执行所述仅针对所述金属层的光刻曝光步骤。
3、 一种半导体器件， 包括硅衬底、 形成于硅衬底上的硅氧化层、 形成于硅氧化层上的金 属层以及形成于所述金属层上的多个功能层， 所述每一功能层都包括依次层叠的介质层和金 属层， 所述硅衬底上设有刻号标记， 其特征在于， 所述多个功能层中的最少一个功能层中， 仅在金属层上与刻号标记相应的区域被光刻。
4、根据权利要求 3所述的半导体器件， 其特征在于， 所述仅金属层上与刻号标记相应的 区域被光刻的功能层为从最外层依次向内的至少两层功能层。
PCT/CN2013/075453 2012-05-15 2013-05-10 半导体器件制造方法及半导体器件 WO2013170725A1 (zh)

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