WO2013158492A1 - Susceptor assemblies for supporting wafers in a reactor apparatus - Google Patents

Susceptor assemblies for supporting wafers in a reactor apparatus Download PDF

Info

Publication number
WO2013158492A1
WO2013158492A1 PCT/US2013/036381 US2013036381W WO2013158492A1 WO 2013158492 A1 WO2013158492 A1 WO 2013158492A1 US 2013036381 W US2013036381 W US 2013036381W WO 2013158492 A1 WO2013158492 A1 WO 2013158492A1
Authority
WO
WIPO (PCT)
Prior art keywords
susceptor
ring
thickness profile
wafer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2013/036381
Other languages
English (en)
French (fr)
Inventor
John A. Pitney
Manabu Hamano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SunEdison Inc
Original Assignee
SunEdison Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SunEdison Inc filed Critical SunEdison Inc
Priority to JP2015507070A priority Critical patent/JP6291478B2/ja
Publication of WO2013158492A1 publication Critical patent/WO2013158492A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/458Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for supporting substrates in the reaction chamber
    • C23C16/4582Rigid and flat substrates, e.g. plates or discs
    • C23C16/4583Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally
    • C23C16/4584Rigid and flat substrates, e.g. plates or discs the substrate being supported substantially horizontally the substrate being rotated
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/10Heating of the reaction chamber or the substrate
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/12Substrate holders or susceptors
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02Epitaxial-layer growth
    • C30B25/16Controlling or regulating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68785Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by the mechanical construction of the susceptor, stage or support

Definitions

  • the field relates generally to apparatus and methods for wafer processing, and more particularly to apparatus and methods for semiconductor wafer etching or semiconductor chemical vapor deposition processes .
  • Epitaxial chemical vapor deposition is a process for growing a thin layer of material on a semiconductor wafer so that the lattice structure is identical to that of the wafer.
  • Epitaxial CVD is widely used in semiconductor wafer production to build up epitaxial layers such that devices can be fabricated directly on the epitaxial layer.
  • the epitaxial deposition process begins by introducing a cleaning gas, such as hydrogen or a hydrogen and hydrogen chloride mixture, to a front surface of the wafer (i.e., a surface facing away from the susceptor) to pre-heat and clean the front surface of the wafer.
  • a cleaning gas such as hydrogen or a hydrogen and hydrogen chloride mixture
  • the cleaning gas removes native oxide from the front surface, permitting the epitaxial silicon layer to grow continuously and evenly on the surface during a subsequent step of the deposition process.
  • the epitaxial deposition process continues by introducing a vaporous silicon source gas, such as silane or a chlorinated silane, to the front surface of the wafer to deposit and grow an epitaxial layer of silicon on the front surface.
  • a vaporous silicon source gas such as silane or a chlorinated silane
  • semiconductor wafer in the deposition chamber during the epitaxial deposition is rotated during the process to allow the epitaxial layer to grow evenly.
  • One aspect of the present disclosure is directed to a susceptor assembly for supporting a semiconductor wafer during a watering process in a reaction apparatus.
  • the susceptor assembly includes a susceptor having opposing upper and lower surfaces.
  • the upper surface of the body is sized and shaped for
  • the susceptor assembly also includes a ring disposed below the lower surface of the susceptor.
  • Another aspect of the present disclosure is directed to a method for adjusting the thickness profile of a layer deposited on wafers.
  • the layer is deposited by deposition in a reaction apparatus having a susceptor.
  • a layer is deposited on a wafer in the reaction apparatus.
  • the thickness profile of the layer is measured.
  • a thickness profile of the layer is analyzed to determine the radial location of a thickness non- uniformity in the thickness profile.
  • a ring is disposed below the susceptor at a radial location that corresponds to the thickness non-uniformity in the thickness profile to increase or decrease the thickness of the layer in subsequently produced wafers.
  • Figure 1 is a front view of an apparatus for processing a substrate such as a
  • Figure 2 is a perspective view of the apparatus ;
  • Figure 3 is a perspective view of the apparatus with the upper dome removed;
  • Figure 4 is a perspective view of the apparatus with some components including the upper dome, lower dome and pre-heat ring removed;
  • Figure 5 is a top view of a ring of the apparatus ;
  • Figure 6 is a perspective view of a apparatus that includes auxiliary arms with the upper dome, lower dome and pre-heat ring removed;
  • Figure 7 is a graph showing the radial thickness profiles of epitaxial wafers prepared in accordance with Example 1.
  • Figure 8 is a graph showing the radial thickness profiles of epitaxial wafers prepared in accordance with Example 2.
  • an apparatus for etching a semiconductor wafer or for depositing an epitaxial layer on a semiconductor substrate in accordance with an embodiment of the present disclosure is generally referred to as 11.
  • the illustrated apparatus is a single wafer reactor; however, the apparatus and methods disclosed herein for providing a more uniform epitaxial layer are suitable for use in other reactor designs including, for example, multiple wafer reactors.
  • the apparatus 11 includes a reaction chamber 31 comprising an upper dome 20, a lower dome 22, an upper liner 27, and a lower liner 38. Collectively, the upper dome 20, lower dome 22, upper liner 27, and lower liner 38 define an interior space of the reaction chamber 31 in which process gas contacts the semiconductor wafer.
  • a gas manifold 34 is used to direct process gas into the reaction chamber 31.
  • a perspective view of the reaction chamber 31 and gas manifold 34 is shown in Figure 2.
  • the apparatus 11 may be used to process a wafer, including without limitation, depositing any type of material on a wafer by a chemical vapor deposition (CVD) process, such as epitaxial CVD or polycrystalline CVD.
  • CVD chemical vapor deposition
  • epitaxy and/or CVD processes should not be considered limiting as the apparatus 11 may also be used for other purposes such as to perform etching or smoothing processes on the wafer.
  • the wafer shown herein is generally circular in shape, though wafers of other shapes are contemplated within the scope of this disclosure.
  • the apparatus 11 is shown in perspective with the upper dome 20 removed to better illustrate the apparatus in Figure 3.
  • a preheat ring 43 for heating the process gas prior to contact with a
  • the outside circumference of the preheat ring 43 is attached to the inner circumference of the lower liner 38.
  • the preheat ring 43 may be supported by an annular ledge (not shown) of the lower liner 38.
  • a susceptor 47 (which may also be referred to herein as a "susceptor body") traversing the space interior to the preheat ring 43 supports a semiconductor wafer 49.
  • Process gas may be heated prior to contacting the semiconductor wafer 49.
  • Both the preheat ring 43 and the susceptor 47 are generally opaque to absorb radiant heating light produced by high intensity radiant heating lamps (not shown) that may be located above and below the reaction chamber 31. Maintaining the preheat ring 43 and the susceptor 47 at a temperature above ambient allows the preheat ring 43 and the susceptor to transfer heat to the process gas as the process gas passes over the preheat ring and the susceptor.
  • the diameter of the wafer 49 is less than the diameter of the susceptor 47 to allow the susceptor to heat the process gas before it contacts the wafer.
  • the preheat ring 43 and susceptor 47 may suitably be constructed of opaque graphite coated with silicon carbide, though other materials are contemplated.
  • the upper dome 20 and lower dome 22 are typically made of a transparent material to allow radiant heating light to pass into the reaction chamber 31 and onto the preheat ring 43 and the susceptor 47.
  • the upper dome 20 and lower dome 22 may be constructed of transparent quartz. Quartz is generally transparent to infrared and visible light and is chemically stable under the reaction conditions of the deposition reaction.
  • Equipment other than high intensity lamps may be used to provide heat to the reaction chamber such as, for example, resistance heaters and inductive heaters.
  • An infrared temperature sensor such as a pyrometer may be mounted on the reaction chamber 31 to monitor the temperature of the susceptor 47, preheat ring 43, or semiconductor wafer 49 by receiving infrared radiation emitted by the susceptor, preheat ring, or wafer.
  • the apparatus 11 includes a susceptor assembly 55 that includes the susceptor 47 and a ring 50 disposed beneath the susceptor 47.
  • the susceptor 47 is attached to susceptor supporting members 7 that extend upward from a shaft 53.
  • the shaft 53 extends through a central column 40.
  • Each susceptor supporting member 7 includes an arm 14 extending outward from the shaft 53 and a vertical leg 17 attached to the susceptor 47.
  • the susceptor supporting members 7 extend directly to the susceptor 47 (i.e., do not include a separate vertical leg 17) .
  • the shaft 53 is connected to a suitable rotation mechanism (not shown) for rotation of the shaft 53, susceptor 47, and wafer 49 about a
  • the apparatus 11 includes a central post 2 that extends from the shaft 53 to support the susceptor 47. In some embodiments (not shown) , the apparatus 11 does not include a central post 2 (or includes a central post that does not contact the susceptor) .
  • the susceptor 47 shown in Figures 1-4 is merely an example.
  • the susceptor may have other shapes, one or more recesses formed therein, and/or several openings formed in the susceptor. Examples of suitable susceptors for use in accordance with the present disclosure are described in U.S. Patent Nos . 6,652,650; 6,596,095; and 6,444,027 and European Patent No. 1 287 188 Bl .
  • the susceptor 47 is a disk that has a lower surface, and an upper surface with a recess of the susceptor for receiving the wafer 49.
  • suitable receivers may be included in the susceptor for receiving a support.
  • three equally spaced, race-track-shaped openings may extend into the susceptor from the lower surface for receiving the upper ends of susceptor supporting members 7 disposed within the reaction chamber 31. These support openings engage the supporting members 7 to prevent the susceptor from slipping on the supports as they turn during processing.
  • the susceptor 47 may include support bosses that are sized and shaped for receiving the supporting members 7 as disclosed in U.S. Patent Publication No. 2009/0165721.
  • the susceptor supporting members 7 and/or central post 2 may be attached to the susceptor 47 by use of lift pins (e.g., silicon carbide lift pins) that extend through the lower surface of the susceptor 47 into the vertical legs 17 and/or central post 2.
  • lift pins e.g., silicon carbide lift pins
  • the ring 50 is attached to ring supporting members 35.
  • the ring supporting members 35 extend from the arms 14 of the susceptor supporting members 7.
  • the ring supporting members 35 may suitably extend from other portions of the susceptor assembly 55 such as the central shaft 35.
  • the ring may suitably be mounted in other ways, such as by attachment to an open ended cylinder that extends downward to the susceptor supporting members 7 or by use of a downward- facing cone that extends from the ring to the central shaft 53.
  • the ring 50 is suitably made of a transparent material (e.g., quartz) to allow visible and infrared light to pass through the ring.
  • a transparent material e.g., quartz
  • the ring may be made of a translucent material. In other embodiments, the ring may have a transparent first portion and a translucent second portion, among other possible combinations.
  • the ring 50 corrects, affects, or modulates the radial temperature profile of the wafer during processing, such as epitaxial deposition to alleviate non-uniformities.
  • the ring may cause the temperature of the portion of the wafer above the ring to increase (relative to when a ring is not used) thereby increasing the amount of material (e.g., silicon) that deposits in a region of the wafer during epitaxial CVD processes .
  • the ring is suitably disposed below regions of the wafer in which a localized or global minimum layer thickness occurs to increase the deposition at this region and create a more uniform radial deposition profile.
  • this minimum layer thickness may be a local or global minimum, and may generally be referred to as a non-uniformity.
  • the ring 50 is translucent to provide local cooling to the wafer and decrease any local or global maximum epitaxial layer thickness.
  • the ring 50 has an outer edge 44, inner edge 59, and center 61.
  • the ring 50 has an inner radius IR extending from the center 61 of the ring to the inner edge 59 and an outer radius OR extending from the center 61 of the ring to the outer edge 44.
  • the inner radius and outer radius are suitably chosen depending on the location and width of a local or global epitaxial layer thickness minimum or maximum.
  • the ring 50 has an inner radius that is less than about 50 mm, less than about 46 mm, less than about 42 mm, or less than about 38 mm; and an outer radius that is at least about 48 mm, at least about 50 mm, at least about 54 mm, at least about 58 mm, or at least about 62 mm such that the ring 50 is located below the wafer near or at the 50 mm global minimum.
  • the distance between the ring 50 and the susceptor 47 (i.e., from the lowest point of the susceptor if the susceptor does not have a uniform lower surface) that is less than about 100 mm, less than about 75 mm, less than about 50 mm, less than about 25 mm, less than about 10 mm, less than about 5 mm, or even less than about 1 mm.
  • the distance between the ring and the susceptor i.e., from the lowest point of the susceptor
  • the distance between the ring 50 and the susceptor 47 may be bound by any combination of this parameters (e.g., from about 5 mm to about 200 mm or from about 25 mm to about 75 mm) .
  • the amount of material deposited on portions of the wafer above the ring may be adjusted by varying this distance.
  • the ring 50 contacts the lower surface of the susceptor 47.
  • the ring 50 may optionally be attached to the lower surface of the susceptor 47.
  • the outer radius is at least about 20 mm, at least about 40 mm, at least about 60 mm, at least about 80 mm, at least about 100 mm, at least about 200 mm, or at least about 300 mm.
  • the outer radius may suitably be from about 20 mm to about 300 mm, from about 40 mm to about 300 mm, from about 20 mm to about 200 mm, from about 20 mm to about 100 mm, or from about 40 mm to about 80 mm.
  • the inner radius may be at least about 20 mm, at least about 40 mm, at least about 60 mm, at least about 80 mm, at least about 100 mm, at least about 200 mm, at least about 300 mm, from about 20 mm to about 300 mm, from about 40 mm to about 300 mm, from about 20 mm to about 200 mm, from about 20 mm to about 100 mm, or from about 40 mm to about 80 mm.
  • the ring is a disk without the inner radius (i.e., does not have an opening formed therein) .
  • the width of the ring 50 (i.e., the distance between the inner radius and the outer radius) may be at least about 1 mm, at least about 5 mm, at least about 10 mm, at least about 20 mm, at least about 40 mm, at least about 75 mm, at least about 100 mm, at least about 200 mm, from about 1 mm to about 300 mm, from about 1 mm to about 100 mm, from about 10 mm to about 100 mm, or from about 10 mm to about 40 mm.
  • the ring 50 may have a thickness of at least about 0.5 mm, at least about 1 mm, at least about 2 mm, at least about 4 mm, less than about 10 mm, less than about 6 mm, less than about 4 mm, less than about 2 mm, from about 0.5 mm to about 10 mm, from about 0.5 mm to about 6 mm, from about 2 mm to about 10 mm, or from about 2 mm to about 6 mm) .
  • more than one ring 50 is used to mitigate more than two local layer thickness problems or non- uniformities.
  • the susceptor supporting members 7 extend through the opening of the ring 50 rather than outside the outer edge 44 of the ring.
  • the outer edge 44 of the ring 50 has a substantially uniform circular shape.
  • the outer edge 44 of the ring 50 may be shaped to include various projections and/or notches or recesses.
  • the outer edge 44 may also be beveled or rounded. Such non-uniform shapes may lessen the effect of the ring 50 on the thickness profile at the outer edge 47 of the ring (i.e., lessens the falloff effect).
  • the inner edge 59 may have non-uniform shape (e.g., projections and/or notches) and/or may be beveled or rounded.
  • the susceptor supporting members 7 and ring supporting members 35 may be transparent (e.g., made of quartz) to allow infrared and visible light to pass therethrough) . In some embodiments, more than three susceptor supporting members 7 and/or ring supporting members 35 may be used without limitation.
  • the susceptor assembly 55 includes auxiliary arms 70 that extend from the shaft 53 to the ring 50.
  • the auxiliary arms 70 extend toward the susceptor 47, but are not in contact with the susceptor.
  • the auxiliary arms 70 contact the susceptor 47 (in which case the auxiliary arms 70 may be considered to be additional susceptor supporting members 7) .
  • the auxiliary arms 70 may counteract a local increase in the epitaxial layer thickness that occurs on portions of the wafer above the arms 14.
  • the thickness of epitaxial layers may be adjusted by use of the apparatus 11 described above.
  • the thickness profile of one or more epitaxial wafers e.g., the thickness profile of the entire structure or of the epitaxial layer itself
  • the thickness profile is analyzed to determine the radial location of a local or global minimum or maximum thickness.
  • a transparent ring is positioned below the susceptor at a radial location that corresponds to the global or local minimum or maximum thickness in the thickness profile to increase or decrease the thickness of the epitaxial layer at the local or global minimum or maximum.
  • the ring is fixedly attached to the susceptor assembly or, as in other embodiments, is removably attached.
  • a plurality of wafers may be analyzed to determine the thickness profile and/or an average thickness profile may be generated to determine the radial location of a local or global minimum or maximum thickness in the wafer profile.
  • the thickness profile may be determined by use of any suitable method available to those of skill in the art including, for example, use of a Fourier-Transform Infrared (FTIR) spectrometer or use of a wafer flatness tool (e.g., KLA-Tencor Wafersight or
  • the radial thickness profile of the substrate is
  • the thickness profile of the deposited layer may be determined by subtracting the substrate thickness from the layered structure thickness .
  • the epitaxial wafers were prepared by exposing single crystal silicon wafer produced by the Czochralski method to trichlorosilane gas at a wafer temperature between 1100°C to 1150°C.
  • the first ring had an inner diameter of 30 mm and an outer diameter of 50 mm.
  • the second ring had an inner diameter of 40 mm and an outer diameter of 60 mm.
  • the ring supporting members were sized such that the distance between the first ring and the susceptor was 11 mm and the distance between the second ring and the susceptor was 50 mm.
  • a control run was performed in which a ring was not used. Auxiliary arms were not used in the control run or with the runs which included use of a transparent ring. As can be seen from Figure 7, the control resulted in an epitaxial wafer radial thickness profile (which is depicted as an offset from the mean thickness) in which a global thickness minimum of about - 35 nm occurs at about 52 mm from the center of the wafer. Thickness profiles were measured with a KLA-Tencor
  • Wafersight 2 wafer flatness tool Wafersight 2 wafer flatness tool.
  • the second ring reduced the local minimum at about 52 mm by about 5 nm thereby improving the thickness uniformity.
  • the first ring reduced the local minimum to about -20 nm.
  • the first ring resulted in an offset of +30 nm from the center of the wafer to about 30 mm from the center and degraded the uniformity.
  • the target epitaxial layer thickness was 2.75 ⁇ .
  • the tested ring had an inner diameter of 45 mm and an outer diameter of 65 mm.
  • the ring supporting members were sized such that the distance between the ring and the susceptor was 25 mm.
  • the three auxiliary arms were about 80 mm in length (from center) and extended out an angle of about 70° from the vertical axis.
  • a control run was performed in which a ring and auxiliary arms were not used.
  • the run with the ring and auxiliary arms resulted in an epitaxial wafer radial thickness profile (which is depicted as an offset) in which the minimum that occurs between 50 mm and 75 mm was reduced by 5 nm relative to the control.

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Chemical Vapour Deposition (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
PCT/US2013/036381 2012-04-19 2013-04-12 Susceptor assemblies for supporting wafers in a reactor apparatus Ceased WO2013158492A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015507070A JP6291478B2 (ja) 2012-04-19 2013-04-12 リアクタ装置内においてウェハを支持するためのサセプタアセンブリ

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201261635436P 2012-04-19 2012-04-19
US61/635,436 2012-04-19
US13/838,284 US9401271B2 (en) 2012-04-19 2013-03-15 Susceptor assemblies for supporting wafers in a reactor apparatus
US13/838,284 2013-03-15

Publications (1)

Publication Number Publication Date
WO2013158492A1 true WO2013158492A1 (en) 2013-10-24

Family

ID=49378929

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2013/036381 Ceased WO2013158492A1 (en) 2012-04-19 2013-04-12 Susceptor assemblies for supporting wafers in a reactor apparatus

Country Status (4)

Country Link
US (1) US9401271B2 (enExample)
JP (1) JP6291478B2 (enExample)
TW (1) TWI613751B (enExample)
WO (1) WO2013158492A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016519208A (ja) * 2013-03-15 2016-06-30 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Epiプロセスのための均一性調整レンズを有するサセプタ支持シャフト

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9814099B2 (en) * 2013-08-02 2017-11-07 Applied Materials, Inc. Substrate support with surface feature for reduced reflection and manufacturing techniques for producing same
US10184193B2 (en) 2015-05-18 2019-01-22 Globalwafers Co., Ltd. Epitaxy reactor and susceptor system for improved epitaxial wafer flatness
US9721826B1 (en) * 2016-01-26 2017-08-01 Taiwan Semiconductor Manufacturing Co., Ltd. Wafer supporting structure, and device and method for manufacturing semiconductor
JP6864564B2 (ja) * 2017-06-09 2021-04-28 株式会社Screenホールディングス 熱処理方法
KR102370157B1 (ko) * 2017-08-31 2022-03-03 가부시키가이샤 사무코 서셉터, 에피택셜 성장 장치, 에피택셜 실리콘 웨이퍼의 제조 방법, 그리고 에피택셜 실리콘 웨이퍼
DE102017222279A1 (de) * 2017-12-08 2019-06-13 Siltronic Ag Verfahren zum Abscheiden einer epitaktischen Schicht auf einer Vorderseite einer Halbleiterscheibe und Vorrichtung zur Durchführung des Verfahrens
DE102019207772A1 (de) * 2019-05-28 2020-12-03 Siltronic Ag Verfahren zum Abscheiden einer epitaktischen Schicht auf einer Vorderseite einer Halbleiterscheibe und Vorrichtung zur Durchführung des Verfahrens
US11300880B2 (en) * 2019-12-09 2022-04-12 Nanya Technology Corporation Coating system and calibration method thereof
USD1031676S1 (en) * 2020-12-04 2024-06-18 Asm Ip Holding B.V. Combined susceptor, support, and lift system
US20220210872A1 (en) * 2020-12-31 2022-06-30 Globalwafers Co., Ltd. System and methods for a radiant heat cap in a semiconductor wafer reactor
US12252806B2 (en) * 2020-12-31 2025-03-18 Globalwafers Co., Ltd Systems and methods for a preheat ring in a semiconductor wafer reactor
TWI867335B (zh) * 2022-09-07 2024-12-21 晶元光電股份有限公司 用於氣相沉積設備的晶圓承載組件及晶圓固定元件

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710407A (en) * 1993-01-21 1998-01-20 Moore Epitaxial, Inc. Rapid thermal processing apparatus for processing semiconductor wafers
US20010037761A1 (en) * 2000-05-08 2001-11-08 Ries Michael J. Epitaxial silicon wafer free from autodoping and backside halo and a method and apparatus for the preparation thereof
EP1287188B1 (en) 2000-12-29 2007-03-14 MEMC Electronic Materials, Inc. Epitaxial silicon wafer free from autodoping and backside halo
US20070095799A1 (en) * 2005-10-31 2007-05-03 Matsushita Electric Industrial Co., Ltd. Film deposition apparatus, film deposition method, monitoring program for film deposition apparatus, and recording medium thereof
US20090165721A1 (en) 2007-12-27 2009-07-02 Memc Electronic Materials, Inc. Susceptor with Support Bosses
US20100227046A1 (en) * 2009-03-04 2010-09-09 Tokyo Electron Limited Film deposition apparatus, film deposition method, and computer readable storage medium

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0864544A (ja) * 1994-08-22 1996-03-08 Touyoko Kagaku Kk 気相成長方法
US20010001384A1 (en) 1998-07-29 2001-05-24 Takeshi Arai Silicon epitaxial wafer and production method therefor
JP4592849B2 (ja) 1999-10-29 2010-12-08 アプライド マテリアルズ インコーポレイテッド 半導体製造装置
JP2001313329A (ja) * 2000-04-28 2001-11-09 Applied Materials Inc 半導体製造装置におけるウェハ支持装置
US6865490B2 (en) * 2002-05-06 2005-03-08 The Johns Hopkins University Method for gradient flow source localization and signal separation
JP3908112B2 (ja) * 2002-07-29 2007-04-25 Sumco Techxiv株式会社 サセプタ、エピタキシャルウェーハ製造装置及びエピタキシャルウェーハ製造方法
US6833322B2 (en) * 2002-10-17 2004-12-21 Applied Materials, Inc. Apparatuses and methods for depositing an oxide film
US20050016466A1 (en) * 2003-07-23 2005-01-27 Applied Materials, Inc. Susceptor with raised tabs for semiconductor wafer processing
JP4300523B2 (ja) 2004-03-12 2009-07-22 株式会社Sumco エピタキシャル成長装置
TW200802552A (en) 2006-03-30 2008-01-01 Sumco Techxiv Corp Method of manufacturing epitaxial silicon wafer and apparatus thereof
US20090194024A1 (en) 2008-01-31 2009-08-06 Applied Materials, Inc. Cvd apparatus
JP5446760B2 (ja) 2009-11-16 2014-03-19 株式会社Sumco エピタキシャル成長方法
US20120073503A1 (en) 2010-09-24 2012-03-29 Juno Yu-Ting Huang Processing systems and apparatuses having a shaft cover

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5710407A (en) * 1993-01-21 1998-01-20 Moore Epitaxial, Inc. Rapid thermal processing apparatus for processing semiconductor wafers
US20010037761A1 (en) * 2000-05-08 2001-11-08 Ries Michael J. Epitaxial silicon wafer free from autodoping and backside halo and a method and apparatus for the preparation thereof
US6444027B1 (en) 2000-05-08 2002-09-03 Memc Electronic Materials, Inc. Modified susceptor for use in chemical vapor deposition process
US6596095B2 (en) 2000-05-08 2003-07-22 Memc Electronic Materials, Inc. Epitaxial silicon wafer free from autodoping and backside halo and a method and apparatus for the preparation thereof
US6652650B2 (en) 2000-05-08 2003-11-25 Memc Electronic Materials, Inc. Modified susceptor for use in chemical vapor deposition process
EP1287188B1 (en) 2000-12-29 2007-03-14 MEMC Electronic Materials, Inc. Epitaxial silicon wafer free from autodoping and backside halo
US20070095799A1 (en) * 2005-10-31 2007-05-03 Matsushita Electric Industrial Co., Ltd. Film deposition apparatus, film deposition method, monitoring program for film deposition apparatus, and recording medium thereof
US20090165721A1 (en) 2007-12-27 2009-07-02 Memc Electronic Materials, Inc. Susceptor with Support Bosses
US20100227046A1 (en) * 2009-03-04 2010-09-09 Tokyo Electron Limited Film deposition apparatus, film deposition method, and computer readable storage medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016519208A (ja) * 2013-03-15 2016-06-30 アプライド マテリアルズ インコーポレイテッドApplied Materials,Incorporated Epiプロセスのための均一性調整レンズを有するサセプタ支持シャフト

Also Published As

Publication number Publication date
US20130276695A1 (en) 2013-10-24
TW201401422A (zh) 2014-01-01
US9401271B2 (en) 2016-07-26
JP6291478B2 (ja) 2018-03-14
JP2015516685A (ja) 2015-06-11
TWI613751B (zh) 2018-02-01

Similar Documents

Publication Publication Date Title
US9401271B2 (en) Susceptor assemblies for supporting wafers in a reactor apparatus
US10240235B2 (en) Method and apparatus for depositing a material layer originating from process gas on a substrate wafer
JP2015516685A5 (enExample)
US12252806B2 (en) Systems and methods for a preheat ring in a semiconductor wafer reactor
JP5446760B2 (ja) エピタキシャル成長方法
US20230354478A1 (en) Methods for semiconductor wafer processing using a radiant heat cap in a semiconductor wafer reactor
US11538683B2 (en) Method for depositing an epitaxial layer on a front side of a semiconductor wafer and device for carrying out the method
US9234280B2 (en) Epitaxial growth apparatus and epitaxial growth method
JP5754651B2 (ja) 気相成長装置の温度調整方法及びエピタキシャルウェーハの製造方法
KR20140092704A (ko) 서셉터 및 이를 포함하는 에피텍셜 반응기
US12503792B2 (en) Methods for manufacturing a semiconductor wafer using a preheat ring in a wafer reactor
JP7439739B2 (ja) エピタキシャル成長装置の温度管理方法及びシリコン堆積層ウェーハの製造方法
KR20160024165A (ko) 웨이퍼 제조 장치

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13717945

Country of ref document: EP

Kind code of ref document: A1

DPE1 Request for preliminary examination filed after expiration of 19th month from priority date (pct application filed from 20040101)
ENP Entry into the national phase

Ref document number: 2015507070

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13717945

Country of ref document: EP

Kind code of ref document: A1