WO2013121792A1 - 不揮発性記憶素子のデータ読み出し方法及び不揮発性記憶装置 - Google Patents
不揮発性記憶素子のデータ読み出し方法及び不揮発性記憶装置 Download PDFInfo
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- WO2013121792A1 WO2013121792A1 PCT/JP2013/000835 JP2013000835W WO2013121792A1 WO 2013121792 A1 WO2013121792 A1 WO 2013121792A1 JP 2013000835 W JP2013000835 W JP 2013000835W WO 2013121792 A1 WO2013121792 A1 WO 2013121792A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
Definitions
- the present invention relates to a data read method for a resistance change type nonvolatile memory element whose resistance value changes according to an applied electrical signal, and a nonvolatile memory device that implements the method.
- the nonvolatile memory element has a simple structure in which a resistance change layer is sandwiched between a lower electrode and an upper electrode. By applying an electric pulse having a voltage greater than or equal to the threshold voltage to the resistance change layer between the upper and lower electrodes, the resistance change layer is changed to a high resistance state or a low resistance state, and the resistance state corresponds to data. It is an element which records information by doing.
- a conductive filament in the binary transition metal oxide constituting the resistance change layer that is, a current path in which the current density is locally increased. (Conductive path) is formed, and the resistance change is considered to occur due to the change in defect density in the filament due to redox (see, for example, Patent Documents 1 and 2 and Non-Patent Document 1).
- the resistance state once set may change within a finite time of a long time or a short time.
- the inventors have developed a new type of resistance value fluctuation phenomenon in which the resistance value increases or decreases in a short time in addition to the deterioration of information (retention characteristic deterioration) due to the resistance value slowly changing over a relatively long time. (Hereinafter referred to as “resistance fluctuation” or simply “fluctuation”).
- one embodiment of a data reading method for a nonvolatile memory element includes: a first electrode; a second electrode; the first electrode; A variable resistance layer having a minute region that is interposed between the second electrodes and is made of a metal oxide and has a larger oxygen deficiency than the surrounding region, and is provided between the first electrode and the second electrode.
- the resistance change layer has a characteristic that the resistance state of the resistance change layer changes from a high resistance state to a low resistance state, and data is stored according to the resistance state of the resistance change layer.
- the resistance is reduced or reduced.
- the nonvolatile memory element includes a first electrode, a second electrode, and the first electrode and the second electrode. And a variable resistance layer having a minute region that is made of a metal oxide and has a greater oxygen deficiency than the surrounding region, and a first current pulse is provided between the first electrode and the second electrode. Is applied, the resistance state of the variable resistance layer changes from the low resistance state to the high resistance state, and the resistance current layer is applied by applying a second current pulse between the first electrode and the second electrode.
- the resistance state of the change layer has a characteristic of changing from a high resistance state to a low resistance state, and data is stored according to the resistance state of the resistance change layer.
- the first variable resistance layer Applying a third current pulse having an absolute value smaller than that of the first current pulse and the second current pulse between the electrode and the second electrode; and After the applying step, a fourth current pulse having an absolute value smaller than the first current pulse and the second current pulse is applied between the first electrode and the second electrode. Reading the resistance state of the variable resistance layer.
- the nonvolatile memory element is interposed between a first electrode, a second electrode, the first electrode, and the second electrode, and a metal A variable resistance layer made of an oxide and having a minute region with a greater oxygen deficiency than the surrounding region, and applying a first voltage pulse between the first electrode and the second electrode
- the resistance change state of the resistance change layer changes from a low resistance state to a high resistance state by applying a second voltage pulse between the first electrode and the second electrode.
- Has a characteristic of changing from a high resistance state to a low resistance state data is stored in accordance with the resistance state of the resistance change layer, and the first resistance change layer having a high resistance or a low resistance is provided.
- a first voltage applying unit for applying a third voltage pulse having a smaller absolute value than that of the second voltage pulse, and the first variable resistance layer having a high resistance or a low resistance.
- a second voltage applying unit that applies a fourth voltage pulse for reading, which has a smaller absolute value than the first voltage pulse and the second voltage pulse, between the electrode and the second electrode And a fluctuation suppression mode for outputting a control signal for instructing the third voltage application section to apply the third voltage, and the fourth voltage application section after the fluctuation suppression mode, the fourth voltage application section
- a control unit that selectively executes a data read mode for outputting a control signal instructing the application of.
- the nonvolatile memory element is interposed between a first electrode, a second electrode, the first electrode, and the second electrode, and a metal A variable resistance layer made of an oxide and having a minute region with a greater degree of oxygen deficiency than the surrounding region, and applying a first current pulse between the first electrode and the second electrode
- the resistance change state of the resistance change layer changes from a low resistance state to a high resistance state by applying a second current pulse between the first electrode and the second electrode.
- Has a characteristic of changing from a high resistance state to a low resistance state data is stored in accordance with the resistance state of the resistance change layer, and the first resistance change layer of the resistance change layer reduced in resistance or reduced in resistance is stored.
- a second current application unit that applies a fourth current pulse for reading that has a smaller absolute value of the current value than the first current pulse and the second current pulse between the electrode and the second electrode A fluctuation suppression mode for outputting a control signal instructing the third current application unit to apply the third current; and after the fluctuation suppression mode, the fourth current application unit receives the fourth current.
- a control unit that selectively executes a data read mode for outputting a control signal instructing the application of.
- nonvolatile memory element data reading method and nonvolatile memory device of the present invention it is possible to suppress the occurrence of data reading errors due to the influence of fluctuations.
- FIG. 1A is a cross-sectional view illustrating a configuration of a nonvolatile memory element according to Embodiment 1.
- FIG. 1B is a cross-sectional view illustrating a configuration of the nonvolatile memory element according to Embodiment 1.
- FIG. 2 is a diagram for explaining the formation of filaments in the resistance change layer.
- FIG. 3 is a circuit configuration diagram when a voltage pulse is applied to the nonvolatile memory element according to Embodiment 1.
- FIG. 4 is a diagram showing fluctuations in the resistance value of the nonvolatile memory element according to Embodiment 1.
- FIG. 5 is a diagram in which the maximum value and the minimum value of the resistance value variation in the high resistance state of the nonvolatile memory element according to Embodiment 1 are plotted.
- FIG. 1A is a cross-sectional view illustrating a configuration of a nonvolatile memory element according to Embodiment 1.
- FIG. 1B is a cross-sectional view illustrating a configuration of
- FIG. 6 is a diagram showing the relationship between the current value and the normal distribution of the current value when the nonvolatile memory element according to Embodiment 1 is in the high resistance state.
- FIG. 7A is a diagram for describing an example of a voltage pulse application state in the reading method according to the embodiment.
- FIG. 7B is a diagram for describing an example of a voltage pulse application state in the reading method according to the embodiment.
- FIG. 8A is a diagram for explaining another example of a voltage pulse application state in the reading method according to the embodiment.
- FIG. 8B is a diagram for explaining another example of a voltage pulse application state in the reading method according to the embodiment.
- FIG. 9A is a diagram for describing another example of a voltage pulse application state in the reading method according to the embodiment.
- FIG. 9B is a diagram for describing another example of a voltage pulse application state in the reading method according to the embodiment.
- FIG. 10A is a diagram for describing another example of a voltage pulse application state in the reading method according to the embodiment.
- FIG. 10B is a diagram for describing another example of a voltage pulse application state in the reading method according to the embodiment.
- FIG. 11 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 2.
- FIG. 12 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 3.
- FIG. 13A is a cross-sectional view showing a configuration of a nonvolatile memory element that is a basis of the present invention.
- FIG. 13B is a cross-sectional view showing the configuration of the nonvolatile memory element that is the basis of the present invention.
- FIG. 14 is a diagram showing fluctuations in the resistance value of the nonvolatile memory element that is the basis of the present
- the variable resistance nonvolatile memory element has a simple structure in which a variable resistance layer is sandwiched between a lower electrode and an upper electrode. Then, by applying a predetermined electrical pulse having a voltage greater than a certain threshold value to the resistance change layer between the upper and lower electrodes, the resistance change layer is changed to a high resistance state or a low resistance state. Information is recorded by associating these different resistance states with data. Since the variable resistance nonvolatile memory element has a simple structure and operation, further miniaturization, large capacity, low cost, and the like are expected. In addition, the resistance change type nonvolatile memory element is attracting attention from the viewpoint of high-speed operation because the state change between the high resistance state and the low resistance state can occur on the order of 100 ns or less.
- nonvolatile memory elements are roughly classified into two types depending on the material (resistance change material) used for the resistance change layer.
- One of them is a resistance to perovskite materials (for example, Pr (1-x) Ca x MnO 3 (PCMO), LaSrMnO 3 (LSMO), GdBaCo x O y (GBCO)) disclosed in Patent Document 1 and the like.
- PCMO Pr (1-x) Ca x MnO 3
- LSMO LaSrMnO 3
- GdBaCo x O y (GBCO) a nonvolatile memory element used for the change material.
- the other is a nonvolatile memory element using a binary transition metal oxide as a variable resistance material. Since the binary transition metal oxide has a simple composition and structure as compared with the perovskite material described above, composition control and film formation in the manufacturing process are easy, and compatibility with the semiconductor manufacturing process is relatively high. It is good.
- FIG. 13A and FIG. 13B are cross-sectional views showing the configuration of a conventional nonvolatile memory element.
- FIG. 13A shows a general structure of a nonvolatile memory element 1400 having a first electrode 1403, a second electrode 1406, and a transition metal oxide layer (resistance change layer) 1405 interposed between the electrodes. .
- a voltage initial break voltage
- FIG. 13B By applying a voltage (initial break voltage) between the first electrode 1403 and the second electrode 1406 to this structure, as shown in FIG. 13B, the first electrode 1403 and the second electrode 1406 A filament 1405c is formed between the two.
- the filament 1405c corresponds to a current path in which the current density of the current flowing between the first electrode 1403 and the second electrode 1406 is locally increased.
- the resistance value once set may change within a finite time of a long time or a short time.
- the stored resistance state changes from the high resistance state to the low resistance state or from the low resistance state to the high resistance without performing a new write operation.
- a phenomenon is known in which stored information deteriorates by gradually changing to a state.
- the embodiment of the present invention described below provides a data reading method and a nonvolatile memory device for a nonvolatile memory element that can suppress the occurrence of a read error due to the influence of the above-described fluctuation.
- This nonvolatile memory element is a resistor having a bipolar switching characteristic that increases in resistance when a positive voltage is applied to the upper electrode with respect to the lower electrode and decreases in resistance when a negative voltage is applied. This is a change-type nonvolatile memory element.
- Fig. 14 shows the measurement results.
- a load resistance of 6.4 k ⁇ is connected in series to the manufactured nonvolatile memory element
- an electrical pulse of +2.5 V and 100 ns and an electrical pulse of ⁇ 2.0 V and 100 ns are alternately used.
- a high resistance state (about 120 k ⁇ ) was set by applying an electric pulse of 100 ns at + 2.5V.
- the nonvolatile memory element was kept at room temperature, and how the resistance value changed with time was examined.
- the resistance value of the nonvolatile memory element repeatedly increases and decreases repeatedly even though the voltage is maintained at room temperature and a voltage large enough to cause a resistance change is not applied. I understand. Specifically, the resistance value drastically decreases to about 50 k ⁇ after the first 200 seconds, and then increases after 1000 seconds and reaches 200 k ⁇ .
- a nonvolatile memory element having a set resistance value of 120 k ⁇ whose measurement results are shown in FIG. 14 will be described as an example.
- 60 k ⁇ which is half of the set resistance value, is set as a threshold value (data judgment point, reference level), and the case where it is 60 k ⁇ or more is defined as a high resistance state, and the case where it is smaller than 60 k ⁇ is defined as a low resistance state.
- the resistance value of the nonvolatile memory element when the resistance value of the nonvolatile memory element is read at about 1000 seconds after the resistance value is set, the resistance value is 50 k ⁇ , so that it is determined to be in the low resistance state. On the other hand, when reading out after 2000 seconds, the resistance value exceeds 200 k ⁇ , so that it is determined to be in the high resistance state. As described above, depending on the data read timing, the data in the same nonvolatile memory element becomes “1” or “0”.
- Non-Patent Document 2 The same phenomenon has been reported in a resistance change type nonvolatile memory element using nickel (Ni) oxide (Daniele lellimini et al., Appl. Phys. Lett., Vol. 96, 2010, pp. 199). 53503 (Non-Patent Document 2)).
- the present inventors have devised a data reading method and the like that can suppress the influence of fluctuation and improve the data retention characteristics in the resistance change type nonvolatile memory element by repeating experiments and considerations.
- a data reading method and the like that can suppress the influence of fluctuation and improve the data retention characteristics in the resistance change type nonvolatile memory element by repeating experiments and considerations.
- it explains as an embodiment of the present invention.
- the nonvolatile memory element includes a first electrode, a second electrode, and between the first electrode and the second electrode. And a variable resistance layer having a minute region that is made of a metal oxide and has a greater oxygen deficiency than the surrounding region, and a first voltage pulse is provided between the first electrode and the second electrode. Is changed from a low resistance state to a high resistance state, and the resistance change is applied by applying a second voltage pulse between the first electrode and the second electrode.
- the resistance state of the layer has a characteristic of changing from a high resistance state to a low resistance state, and data is stored according to the resistance state of the resistance change layer.
- the first variable resistance layer formed Applying a third voltage pulse having an absolute voltage value smaller than that of the first voltage pulse and the second voltage pulse between the electrode and the second electrode; and After the applying step, a fourth voltage pulse having a smaller absolute value than the first voltage pulse and the second voltage pulse is applied between the first electrode and the second electrode. Reading the resistance state of the variable resistance layer.
- the first electrode, the second electrode, the first electrode, and the second electrode are interposed between the first electrode and the second electrode, and are formed of a metal oxide.
- the minute region has a larger oxygen deficiency than the surrounding region.
- changing the resistance state of the resistance change layer from the low resistance state to the high resistance state by applying a first current pulse between the first electrode and the second electrode.
- a resistance state of the variable resistance layer changes from a high resistance state to a low resistance state by applying a second current pulse between the first electrode and the second electrode, and the resistance Data is stored in accordance with the resistance state of the change layer, and the data reading method is configured such that the high resistance or low resistance between the first electrode and the second electrode of the resistance change layer More current than the first current pulse and the second current pulse.
- the first current pulse is interposed between the first electrode and the second electrode.
- applying a fourth current pulse whose absolute value is smaller than that of the second current pulse, and reading the resistance state of the variable resistance layer.
- the minute region may be formed from the second electrode toward the first electrode, and may have a shape in contact with the second electrode but not in contact with the first electrode.
- the resistance change layer may have a fluctuation characteristic in which the resistance value changes randomly with time.
- the variable resistance layer includes a first oxide layer and a second oxide layer having a larger degree of oxygen deficiency than the first oxide layer, and the minute region includes the first oxide layer.
- the degree of oxygen deficiency may be greater than that of the layer.
- the first oxide layer is in contact with the second electrode, the minute region is in contact with the second electrode, and the first oxide layer extends from the second electrode through the first oxide layer. It may be formed toward the electrode.
- the nonvolatile memory element may have a plurality of times when the step of reading the resistance state is repeated a plurality of times after the data is stored and before the next step of changing the resistance state is executed.
- the step of applying the third voltage pulse may be executed before each of the steps of reading the resistance state.
- the nonvolatile memory element is a bipolar drive element. Thereby, even when the nonvolatile memory element is a bipolar drive element, stable and accurate reading can be performed.
- the third voltage pulse having an absolute value greater than that of the fourth voltage pulse is applied between the first electrode and the second electrode. May be. Further, in the step of applying the third current pulse, the third current pulse having an absolute value larger than that of the fourth current pulse is applied between the first electrode and the second electrode. May be. Thereby, the power consumption of the fourth voltage pulse for reading (or the fourth current pulse) can be suppressed while enhancing the fluctuation suppressing effect in the third voltage pulse (or the third current pulse).
- first voltage pulse and the third voltage pulse may have the same polarity.
- first current pulse and the third current pulse may have the same polarity.
- the polarity of the third voltage pulse (or third current pulse) is the same as the polarity of the first voltage pulse (or first current pulse) that changes the resistance change layer from the low resistance state to the high resistance state in normal operation. By making them the same, for example, it is possible to suppress the occurrence of data read errors with respect to fluctuations in the direction in which the resistance value decreases.
- the second voltage pulse and the third voltage pulse may have the same polarity.
- the second current pulse and the third current pulse may have the same polarity.
- the polarity of the third voltage pulse (or third current pulse) is the same as the polarity of the second voltage pulse (or second current pulse) that changes the resistance change layer from the high resistance state to the low resistance state in normal operation.
- the metal oxide may be a tantalum oxide. Thereby, stable resistance change can be performed.
- the nonvolatile memory element includes a first electrode, a second electrode, and the first electrode and the second electrode.
- a variable resistance layer made of an oxide and having a minute region with a greater oxygen deficiency than the surrounding region, and applying a first voltage pulse between the first electrode and the second electrode
- the resistance change state of the resistance change layer changes from a low resistance state to a high resistance state by applying a second voltage pulse between the first electrode and the second electrode.
- Has a characteristic of changing from a high resistance state to a low resistance state data is stored in accordance with the resistance state of the resistance change layer, and the first resistance change layer having a high resistance or a low resistance is provided. Between the first electrode and the second electrode.
- a first voltage applying unit for applying a third voltage pulse having a smaller absolute value than the second voltage pulse, and the first variable resistance layer having a high resistance or a low resistance.
- a second voltage application for applying a fourth voltage pulse for reading, whose absolute value is smaller than that of the first voltage pulse and the second voltage pulse, between the first electrode and the second electrode And a fluctuation suppression mode for outputting a control signal for instructing the third voltage application section to apply the third voltage, and after the fluctuation suppression mode, the fourth voltage application section receives the fourth voltage
- a control unit that selectively executes a data read mode for outputting a control signal instructing application of a voltage.
- the non-volatile memory element is interposed between the first electrode, the second electrode, the first electrode and the second electrode, and is made of a metal oxide, compared to the surrounding region.
- a resistance change layer having a minute region with a large degree of oxygen deficiency and applying a first current pulse between the first electrode and the second electrode to change the resistance state of the resistance change layer to a low resistance state.
- the resistance change state of the resistance change layer changes from the high resistance state to the low resistance state by applying a second current pulse between the first electrode and the second electrode.
- a second current applying unit that applies a fourth current pulse for reading, the absolute value of which is smaller than that of the first current pulse and the second current pulse, and the third current applying unit.
- a fluctuation suppression mode for outputting a control signal for instructing application of a current 3
- data reading for outputting a control signal for instructing application of the fourth current to the fourth current application unit after the fluctuation suppression mode.
- a control unit that selectively executes the mode. Since the third voltage pulse (or the third current pulse) can be applied in the fluctuation suppressing mode before the reading mode, it is possible to suppress the occurrence of data reading errors due to the influence of fluctuation.
- the minute region may be formed from the second electrode toward the first electrode, and may have a shape in contact with the second electrode and not in contact with the first electrode.
- the resistance change layer may have a fluctuation characteristic in which the resistance value changes randomly with time.
- control unit may execute the fluctuation suppressing mode each time before executing each of the read modes a plurality of times. Thereby, stable and accurate reading can be performed.
- the nonvolatile memory element is a bipolar drive element. Thereby, even when the nonvolatile memory element is a bipolar drive element, stable and accurate reading can be performed.
- the variable resistance layer includes a first oxide layer and a second oxide layer having a greater degree of oxygen deficiency than the first oxide layer.
- the resistance value of the resistance change layer can be changed by changing the resistance value of the minute region.
- the first oxide layer is in contact with the second electrode, the minute region is in contact with the second electrode, and the first oxide layer extends from the second electrode through the first oxide layer. It may be formed toward the electrode.
- the first voltage application unit may apply the third voltage pulse having a larger absolute voltage value than the fourth voltage pulse between the first electrode and the second electrode. It may be configured.
- the first current application unit may apply the third current pulse having a larger absolute value of the current value than the fourth current pulse between the first electrode and the second electrode. It may be configured. Thereby, the power consumption of the fourth voltage pulse for reading (or the fourth current pulse) can be suppressed while enhancing the fluctuation suppressing effect in the third voltage pulse (or the third current pulse).
- first voltage pulse and the third voltage pulse may have the same polarity.
- first current pulse and the third current pulse may have the same polarity.
- the polarity of the third voltage pulse (or third current pulse) is the same as the polarity of the first voltage pulse (or first current pulse) that changes the resistance change layer from the low resistance state to the high resistance state in normal operation. By making them the same, for example, it is possible to suppress the occurrence of data read errors with respect to fluctuations in the direction in which the resistance value decreases.
- the second voltage pulse and the third voltage pulse may have the same polarity.
- the second current pulse and the third current pulse may have the same polarity.
- the polarity of the third voltage pulse (or third current pulse) is the same as the polarity of the second voltage pulse (or second current pulse) that changes the resistance change layer from the high resistance state to the low resistance state in normal operation.
- the metal oxide may be a tantalum oxide. Thereby, stable resistance change can be performed.
- FIG. 1A and 1B are cross-sectional views illustrating the configuration of the nonvolatile memory element according to Embodiment 1.
- FIG. 1A and 1B are cross-sectional views illustrating the configuration of the nonvolatile memory element according to Embodiment 1.
- the nonvolatile memory element 100 of this embodiment includes a substrate 101, an interlayer insulating film 102 formed on the substrate 101, and a first electrode formed on the interlayer insulating film 102. 103, a second electrode 105, and a resistance change layer 104 sandwiched between the first electrode 103 and the second electrode 105.
- the nonvolatile memory element 100 stores data according to the resistance state of the resistance change layer 104.
- the resistance change layer 104 has a stacked structure of a first oxide layer 104a containing a first transition metal oxide and a second oxide layer 104b containing a second transition metal oxide.
- the first oxide layer 104a includes oxygen-deficient tantalum oxide
- the second oxide layer 104b also includes tantalum oxide.
- the oxygen content of the second oxide layer 104b is higher than the oxygen content of the first oxide layer 104a.
- the oxygen deficiency of the first oxide layer 104a is greater than the oxygen deficiency of the second oxide layer 104b. Therefore, the resistance value (more specifically, specific resistance) of the second oxide layer 104b is larger than the resistance value (more specifically, specific resistance) of the first oxide layer 104a.
- the electric field applied to the resistance change layer 104 tends to concentrate on the second oxide layer 104b. Therefore, as shown in FIG. 1B, a structure in which the microregion 106 is not in contact with the first electrode 103 can be easily formed.
- the resistance change layer 104 includes a minute region 106 in the vicinity of the interface between the first oxide layer 104a and the second oxide layer 104b.
- the oxygen deficiency of the microregion 106 is larger than the oxygen deficiency of the second oxide layer 104b and is different from the oxygen deficiency of the first oxide layer 104a.
- the microregion 106 is a region having a larger oxygen deficiency than the surrounding region, and when a voltage is applied between the first electrode 103 and the second electrode 105 in the resistance change layer 104, It means the region where current flows predominantly.
- the micro region 106 means a region including a set of filaments (conductive paths) formed in the resistance change layer 104. That is, the resistance change in the resistance change layer 104 appears through the microregion 106. Therefore, when a drive voltage is applied to the resistance change layer 104 in the low resistance state, a current flows predominantly through the microregion 106 including the filament.
- the resistance change layer 104 transitions between a high resistance state and a low resistance state in the minute region 106.
- the minute region 106 is formed by applying an initial break voltage to the resistance change layer 104 having a stacked structure of the first oxide layer 104a and the second oxide layer 104b.
- the initial break voltage may be a low voltage.
- the initial break comes into contact with the second electrode 105, penetrates the second oxide layer 104b, and partially penetrates the first oxide layer 104a.
- a minute region 106 that is not in contact with the electrode 103 is formed.
- the size of the minute region 106 may be small, and the size is such that the lower end thereof does not contact the first electrode 103. Thereby, the variation in resistance change is reduced by reducing the size of the minute region 106. However, the minute region 106 is large enough to secure at least a filament necessary for flowing current.
- the resistance change layer 104 has a fluctuation that is a characteristic that the resistance value changes randomly with time. That is, the resistance change layer 104 has fluctuations in which the resistance value increases or decreases in a short time in addition to the deterioration of information (retention characteristic deterioration) due to the resistance value slowly changing over a relatively long time.
- the oxygen deficiency refers to the stoichiometric composition of each transition metal (if there are multiple stoichiometric compositions, the stoichiometric composition having the highest resistance value among them). It refers to the proportion of oxygen that is deficient with respect to the amount of oxygen that constitutes the oxide.
- a metal oxide having a stoichiometric composition is more stable and has a higher resistance value than a metal oxide having another composition.
- the stoichiometric oxide composition is Ta 2 O 5 , which can be expressed as TaO 2.5 .
- the degree of oxygen deficiency of TaO 2.5 is 0%.
- the oxygen content of TaO 2.5 is the ratio of oxygen to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0% and less than 71.4 atm%.
- the oxygen-deficient metal oxide has a negative oxygen deficiency. In this specification, unless otherwise specified, the oxygen deficiency is described as including a positive value, 0, and a negative value.
- the composition of the first oxide layer 104a is TaO x and the second oxide layer 104b is TaO y , 0 ⁇ x ⁇ 2.5 and x ⁇ y may be satisfied. In order to stably realize the resistance change operation, 2.1 ⁇ y and 0.8 ⁇ x ⁇ 1.9 may be satisfied.
- the composition of the metal oxide layer can be measured using Rutherford backscattering method or the like.
- the resistance change layer 104 may be configured using a metal oxide other than tantalum. Typically, a transition metal oxide or an oxide of aluminum (Al) is used for the resistance change layer 104.
- a transition metal oxide for example, tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), nickel (Ni ) And the like, or an oxide of transition metal selected from the above or an oxide of aluminum (Al) can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions.
- the composition of the first hafnium oxide layer is HfO x
- x is 0.9 or more and 1.6 or less
- the composition of the second hafnium oxide layer is It has been confirmed that the resistance value of the variable resistance layer can be stably changed at high speed when y is larger than the value of x when HfO y is used.
- the thickness of the second hafnium oxide layer may be about 3 to 4 nm.
- x is 0.9 or more and 1.4 or less when the composition of the first zirconium oxide layer is ZrO x, and the composition of the second zirconium oxide layer It is confirmed that the resistance value of the variable resistance layer can be stably changed at a high speed when y is larger than the value of x where is ZrO y .
- the thickness of the second zirconium oxide layer may be about 1 to 5 nm.
- the first transition metal constituting the first oxide layer 104a and the second transition metal constituting the second oxide layer 104b may be different transition metals.
- the second oxide layer 104b may have a lower degree of oxygen deficiency, that is, higher resistance than the first oxide layer 104a.
- the voltage applied between the first electrode 103 and the second electrode 105 during resistance change is more distributed to the second oxide layer 104b, and as a result, the second A redox reaction is more likely to occur in the oxide layer 104b.
- the standard electrode potential of the second transition metal may be lower than the standard electrode potential of the first transition metal.
- the resistance change phenomenon occurs when the resistance value changes due to a change in the filament (conducting path) caused by an oxidation-reduction reaction in a minute region formed in the second oxide layer 104b having a high resistance. This is because it is considered.
- the second oxide layer 104b is made of a metal oxide having a standard electrode potential lower than that of the first oxide layer 104a. A redox reaction is more likely to occur in the physical layer 104b.
- aluminum oxide (Al 2 O 3 ) can be used for the high-concentration oxide layer 522 to be a high resistance layer.
- oxygen-deficient tantalum oxide (TaO x ) may be used for the low-concentration oxide layer 521
- aluminum oxide (Al 2 O 3 ) may be used for the high-concentration oxide layer 522.
- the second electrode 105 connected to the second oxide layer 104b having a lower oxygen deficiency is, for example, platinum (Pt), iridium (Ir), or the like, the second oxide layer 104b and the first electrode 103.
- You may comprise by the material whose standard electrode potential is higher compared with the material which comprises. With such a structure, a redox reaction occurs selectively in the second oxide layer 104b in the vicinity of the interface between the second electrode 105 and the second oxide layer 104b, and stable resistance is achieved. A change phenomenon is obtained.
- the dielectric constant of the second oxide layer 104b may be larger than the dielectric constant of the first oxide layer 104a.
- the band gap of the second oxide layer 104b may be smaller than the band gap of the first oxide layer 104a.
- a material with a high relative dielectric constant is more likely to break down than a material with a lower relative dielectric constant
- a material with a lower band gap is more likely to break down than a material with a larger band gap. Break voltage can be lowered.
- the dielectric breakdown electric field strength of the second oxide layer 104b is less than that of the first oxide layer 104a. Compared to this, it becomes smaller and the initial break voltage can be reduced. This is for example described in J. McPherson et al. , IEDM 2002, p.
- the dielectric breakdown field strength increases as the dielectric constant increases between the dielectric breakdown electric field strength (Breakdown Strength) of the oxide layer. This is because there is a correlation that becomes smaller.
- FIG. 2 there is a correlation between the breakdown electric field strength of the oxide layer and the band gap that the breakdown electric field strength increases as the band gap increases. is there.
- FIG. 2 is a diagram for explaining the formation of the filament described above, and shows an example of a result of simulation using a percolation model.
- a filament is formed by connecting oxygen defect sites in the variable resistance layer 104 (particularly, in a minute region of the second oxide layer 104b).
- the percolation model assumes a random distribution such as oxygen defect sites (hereinafter simply referred to as “defect sites”) in the resistance change layer 104. If the density of defect sites exceeds a certain threshold, the defect sites are connected.
- This model is based on the theory that the probability of formation increases.
- “defect” means that oxygen is deficient in the transition metal oxide, and “density of defect sites” corresponds to the degree of oxygen deficiency. That is, as the oxygen deficiency increases, the density of defect sites also increases.
- the oxygen ion sites of the resistance change layer 104 are approximately assumed as regions (sites) partitioned in a lattice shape, and the filaments formed by the defect sites formed stochastically are obtained by simulation.
- a site including “0” represents a defect site formed in the resistance change layer 104.
- a blank site represents a site occupied by oxygen ions, which means a high resistance region.
- a cluster of defect sites indicated by arrows is a filament formed in the resistance change layer 104 when a voltage is applied in the vertical direction in the figure, that is, a current. Shows the path that flows. As shown in FIG.
- the filament that allows current to flow between the lower surface and the upper surface of the resistance change layer 104 is formed of a cluster of defect sites that connect from the upper end to the lower end of randomly distributed defect sites. Based on this percolation model, the number and shape of filaments are formed stochastically. The distribution of the number and shape of the filaments causes variations in the resistance value of the resistance change layer 104.
- an interlayer insulating film 102 having a thickness of 200 nm is formed on a substrate 101 made of single crystal silicon by a thermal oxidation method. Then, a Pt thin film having a thickness of 100 nm is formed on the interlayer insulating film 102 as the first electrode 103 by a sputtering method. Note that an adhesion layer or a barrier layer of Ti, TiN, or the like may be formed between the first electrode 103 and the interlayer insulating film 102 by a sputtering method. Thereafter, an oxygen-deficient first oxide layer 104a is formed on the first electrode 103 by a reactive sputtering method using a Ta target, for example.
- the first oxide layer 104a is formed on the surface of the first oxide layer 104a by, for example, modification of the outermost surface of the first oxide layer 104a by oxidation or reactive sputtering using a Ta target. Then, the second oxide layer 104b having a lower oxygen deficiency is formed.
- the variable resistance layer 104 is configured by a stacked structure of the first oxide layer 104a and the second oxide layer 104b.
- the thickness of the second oxide layer 104b may be about 8 nm or less. In order to obtain a stable resistance change, the thickness of the second oxide layer 104b may be about 1 nm or more. For example, the thickness of the second oxide layer 104b is 6 nm.
- a 150 nm-thick Pt thin film is formed as the second electrode 105 on the second oxide layer 104b by a sputtering method.
- the nonvolatile memory element 100 in which the variable resistance layer 104 using an oxygen-deficient Ta oxide is sandwiched between the first electrode 103 and the second electrode 105 can be manufactured.
- the initial break process is performed when the second oxide layer 104b is an insulator layer or a semiconductor layer having a very high resistance value.
- the initial state variable resistance layer 104 is changed to another state by applying an initial voltage pulse between the first electrode 103 and the second electrode 105. Thereby, it is considered that a minute region having a conductive path (filament) is formed in a part of the region having a high resistance value in the resistance change layer 104.
- variable resistance layer 104 includes the first oxide layer 104a and the second oxide layer 104b
- the oxygen deficiency is larger in the second oxide layer than the second oxide layer.
- the micro region typically includes an assembly of a plurality of filaments.
- the “initial state” here means a state from immediately after the nonvolatile memory element 100 is manufactured to before a voltage pulse for changing the resistance state of the nonvolatile memory element 100 is applied.
- the “initial resistance value” means a resistance value in an initial state.
- the absolute value of the voltage value of the initial voltage pulse may be larger than the voltage pulse of the normal write voltage.
- ⁇ Resistance value setting> The resistance change was caused by applying an electrical pulse signal to the first electrode 103 and the second electrode 105 of the nonvolatile memory element 100.
- an electrical pulse signal to the first electrode 103 and the second electrode 105 of the nonvolatile memory element 100.
- the positive and negative voltages are expressed with reference to the first electrode 103. That is, the voltage when a high voltage is applied to the second electrode 105 is “positive” with respect to the first electrode 103, and the voltage when a low voltage is applied to the second electrode 105 is also “negative”. ".
- the nonvolatile memory element 100 increases in resistance when a positive voltage is applied, and decreases in resistance when a negative voltage is applied.
- positive polarity can be read as “the same polarity as a voltage for increasing the resistance of a nonvolatile memory element (high resistance writing voltage)”, and “negative polarity” is referred to as “nonvolatile memory”. It can be read as “the same polarity as the voltage for reducing the resistance of the element (the low resistance writing voltage)”.
- the load resistor 202 is connected for the following two reasons. One is that by connecting the load resistor 202, the set resistance value of the nonvolatile memory element 201 is changed, and information on a wide resistance range can be obtained.
- the sample used in this embodiment has a characteristic that the low resistance value of the nonvolatile memory element 201 is equivalent to the load resistance 202, and the high resistance value is about 10 to 100 times the low resistance value. I often take it. Therefore, if the load resistance 202 is reduced, the resistance value of the nonvolatile memory element 201 to be set can be reduced. Conversely, if the load resistance 202 is increased, the resistance value of the nonvolatile memory element 201 can be increased.
- the second reason is that it is assumed to grasp the fluctuation phenomenon of the resistance value when the nonvolatile memory element 201 is actually used.
- a variable resistance nonvolatile memory element it is not used alone in actual use, but is used in a state where a transistor, a diode, and the like having a certain resistance value are connected.
- the load resistor 202 is connected assuming these external load resistors that occur during actual use.
- the resistance value of the nonvolatile memory element 201 was set to the high resistance state (resistance value RH) and the low resistance state (resistance value RL).
- RH high resistance state
- RL low resistance state
- +2.5 V and ⁇ 2.0 B voltage pulses were alternately applied 100 times, and finally a +2.5 V voltage pulse was applied once.
- a voltage pulse of ⁇ 2.0 V was finally applied once.
- the pulse width here is 100 ns.
- the nonvolatile memory element 201 having the resistance value set as described above was held at room temperature, and a voltage of 50 mV was applied every 20 seconds to measure the resistance value of the nonvolatile memory element 201. Note that the resistance value of the nonvolatile memory element 201 does not change at such a low voltage of about 50 mV.
- FIG. 4 is a diagram illustrating a change in the resistance value of the nonvolatile memory element 201 from 0 seconds to 50000 seconds after the nonvolatile memory element 201 is set to a high resistance state with a 6.4 k ⁇ load resistance connected. It is.
- the resistance value of the nonvolatile memory element 201 immediately after setting the nonvolatile memory element 201 to the high resistance state is referred to as a set resistance value.
- the set resistance value was about 170 k ⁇ . Referring to FIG. 4, it can be seen that this resistance value increases and decreases with time and causes a fluctuation phenomenon.
- the minimum value is 150 k ⁇ in about 2000 seconds from the start of measurement, and the maximum value is 250 k ⁇ in about 20000 seconds.
- FIG. 4 shows the change in resistance value after the high resistance state is set.
- the inventors have similar resistance value fluctuation (fluctuation) phenomenon even when the low resistance state is set. It was confirmed.
- the same measurement as described above was performed by connecting load resistances of 0 ⁇ (no load), 1700 ⁇ , 2150 ⁇ , 3850 ⁇ , 4250 ⁇ , and 6400 ⁇ to a plurality of elements.
- the results are summarized in FIG.
- the horizontal axis represents the set (initial) resistance value of the nonvolatile memory element 201.
- the vertical axis represents the maximum value or the minimum value among the resistance values of the nonvolatile memory element 201 that have fluctuated between 0 seconds and 50000 seconds after the high resistance state is set.
- the present inventors have newly found the following properties relating to the fluctuation phenomenon.
- the amount of fluctuation in the resistance value can be reduced by intentionally capturing and releasing these electrons. It can be suppressed. Specifically, it is considered that electrons can be captured by dangling bonds in the filament by applying a negative voltage pulse between both electrodes to inject electrons into the filament. As a result, when the conduction path (filament) is interrupted, the resistance value increases. On the other hand, it is considered that electrons can be emitted from the filament by applying a positive voltage pulse between both electrodes. As a result, when the conduction path (filament) recovers, the resistance value decreases.
- the amount of fluctuation can be suppressed by injecting electrons into the filament so as to change the resistance value in the direction opposite to the direction in which the resistance value fluctuates, or by emitting electrons from the filament. That is, the fluctuation amount is changed by changing the resistance value so that the resistance value becomes high for the fluctuation phenomenon where the resistance value becomes low, or by changing the resistance value so that the resistance value becomes low for the fluctuation phenomenon where the resistance value becomes high. It can be suppressed.
- the voltage pulse for suppressing the fluctuation amount as described above is expressed as “fluctuation suppression voltage pulse”.
- the “fluctuation suppression voltage pulse” means a voltage pulse that can suppress the fluctuation amount when there is fluctuation.
- FIG. 6 shows an example of how the resistance value changes due to the fluctuation suppression voltage pulse.
- the left side of FIG. 6 shows that by setting a plurality of nonvolatile memory elements 100 to a high resistance state, applying fluctuation suppression voltage pulses (+700 mV, 0 V, and ⁇ 700 mV) of different voltages and then performing a reading process. It is a figure which shows the relationship between the obtained electric current value and the normal distribution of an electric current value.
- a voltage pulse of 200 ns at +700 mV was used as a fluctuation suppression voltage pulse for decreasing the resistance value
- a voltage pulse of 200 ns at ⁇ 700 mV was used as a fluctuation suppression voltage pulse for increasing the resistance value.
- FIG. 6 also shows a case where a reading process is performed without applying a fluctuation suppression voltage pulse (a set of plots labeled “0 V” in the figure) as a comparison target.
- a fluctuation suppression voltage pulse (a set of plots labeled “0 V” in the figure) as a comparison target.
- the current value is increased by applying the +700 mV fluctuation suppression voltage pulse (that is, the resistance value of the nonvolatile memory element 100 is increased). (Decrease).
- the current value is decreased by applying the fluctuation suppressing voltage pulse of ⁇ 700 mV (that is, the resistance value of the nonvolatile memory element 100 is increased). Can be confirmed.
- the resistance value of the nonvolatile memory element can be varied by using the fluctuation suppressing voltage pulse.
- the resistance value can be varied in the direction opposite to the direction in which the resistance value fluctuates, and the fluctuation amount can be suppressed. As a result, it is possible to suppress the occurrence of data read errors caused by fluctuations.
- the resistance value can be decreased with respect to fluctuation in the direction in which the resistance value increases.
- the resistance value can be increased with respect to the fluctuation in the direction in which the resistance value decreases by using the negative polarity fluctuation suppression voltage pulse.
- the polarity of the fluctuation suppression voltage pulse may be set according to whether the non-volatile memory element is likely to fluctuate in a high resistance state or a low resistance state. And in which of these states the fluctuation is likely to occur is considered to have a correlation with the diameter of the filament formed in the resistance change layer of the nonvolatile memory element. Generally, when the filament diameter is large, the set resistance value is low, and when the filament diameter is small, the set resistance value is large.
- a negative fluctuation suppression voltage pulse may be used to increase the resistance value
- a non-volatile memory having a relatively small filament diameter is used.
- a positive fluctuation suppression voltage pulse may be used to reduce the resistance value.
- a positive fluctuation suppression voltage pulse may be used when a nonvolatile memory element having a small filament diameter is formed for the purpose of realizing low power consumption or the like.
- the polarity of the suppression voltage pulse may be set according to the diameter of the filament.
- the fluctuation characteristics are affected by the writing conditions. For example, when the absolute value, the pulse width, or the number of pulses of the high resistance write voltage pulse is small compared to the low resistance write voltage pulse, the fluctuation in the direction of decreasing the resistance value in the high resistance state is significant. Therefore, in this case, in order to increase the resistance value, a negative polarity fluctuation suppression voltage pulse may be used.
- a positive fluctuation suppression voltage pulse may be used.
- the resistance value may greatly change from the set resistance value due to a fluctuation phenomenon, which may cause a data read error.
- the nonvolatile memory element is interposed between the first electrode, the second electrode, and the first electrode and the second electrode, and the metal oxide And a resistance change layer having a minute region with a greater degree of oxygen deficiency than the surrounding region, and resistance change by applying a first voltage pulse between the first electrode and the second electrode
- the resistance state of the layer changes from the low resistance state to the high resistance state
- the resistance state of the resistance change layer is changed from the high resistance state to the low resistance by applying a second voltage pulse between the first electrode and the second electrode.
- the data is stored in accordance with the resistance state of the resistance change layer, and the data reading method includes the first electrode and the second electrode of the resistance change layer having a high resistance or a low resistance. From the first voltage pulse and the second voltage pulse between the electrodes After the step of applying the third voltage pulse having a small absolute value of the voltage value and the step of applying the third voltage pulse, the first voltage pulse and the second voltage are applied between the first electrode and the second electrode. Applying a fourth voltage pulse whose absolute value is smaller than that of the voltage pulse, and reading the resistance state of the resistance change layer.
- the initial break voltage is applied to the nonvolatile memory element 100 before the data reading method is executed, and as a result, a filament is formed in the resistance change layer 104.
- the HR write voltage shown below corresponds to an example of a first voltage pulse
- the LR write voltage corresponds to an example of a second voltage pulse
- the fluctuation suppression pulse corresponds to an example of a third voltage pulse
- the read voltage corresponds to an example of a fourth voltage pulse.
- FIGS. 7A to 10B are diagrams for explaining an example of a voltage pulse application state in the reading method of the present embodiment.
- FIGS. 7A, 8A, 9A, and 10A perform HR writing (high-resistance writing), and then perform multiple readings
- FIG. 7B, FIG. 8B, and FIG. 9B and FIG. 10B schematically show waveforms of applied voltages when LR writing (low-resistance writing) is performed and then reading is performed a plurality of times.
- the voltage values described in the drawings are merely examples.
- data is read using a read voltage of +0.4 V for a nonvolatile memory element that is HR written with a write voltage of +2.0 V or LR written with a write voltage of ⁇ 2.4 V.
- a negative fluctuation suppression voltage pulse having a smaller absolute value than the HR write voltage is applied between both electrodes.
- the resistance value of the nonvolatile memory element can be increased by using the negative-polarity fluctuation suppressing voltage pulse before the read voltage is applied. Therefore, this read operation may be adopted for a nonvolatile memory element having a relatively large filament diameter or a high defect site density where the resistance value tends to decrease due to fluctuations.
- a positive fluctuation suppression voltage pulse is used before the read voltage is applied.
- the resistance value of the nonvolatile memory element can be reduced. Therefore, this read operation may be adopted for a nonvolatile memory element having a relatively small filament diameter or a low defect site density where the resistance value tends to increase due to fluctuations.
- the fluctuation suppression voltage pulse is applied each time before the data read voltage is applied.
- the influence of fluctuation can be suppressed for each reading process, stable and accurate reading can be realized.
- reading is performed immediately after the fluctuation suppressing voltage pulse is applied, stable and accurate reading can be realized even when the resistance value changes with time after the fluctuation suppressing voltage pulse is applied.
- the fluctuation suppression voltage pulse is applied only before the first read process. You may make it perform. In this case, an increase in current consumption can be suppressed as compared with the case where a fluctuation suppression voltage pulse is applied for each reading process.
- the fluctuation suppression voltage pulse may be applied every specific period, and a plurality of read processes may be performed during that period. In this case, stable data reading can be realized while suppressing an increase in current consumption in the reading process.
- the data reading method of the present embodiment is not limited to this. If the fluctuation suppressing voltage pulse and the reading voltage pulse are applied at least once in this order after the writing voltage pulse is applied and before the next writing voltage pulse is applied, at least the fluctuation suppressing effect is obtained.
- a nonvolatile memory device including a plurality of nonvolatile memory elements
- so-called block reading may be performed in which data is read in units of memory blocks including a predetermined number of nonvolatile memory elements.
- a stable and high-speed reading is realized by applying a fluctuation suppression voltage pulse to all the nonvolatile memory elements constituting the memory block before performing the block reading and then executing the block reading. It becomes possible.
- + 2.0V and ⁇ 2.4V write voltage pulses are used as write voltage pulses for HR write and LR write, respectively, and a voltage of + 0.7V or ⁇ 0.7V is used as a fluctuation suppression voltage pulse.
- a pulse is used.
- the absolute value of the voltage value of the fluctuation suppressing voltage pulse must be at least smaller than the absolute value of the voltage value of the write voltage pulse. This is to prevent the resistance state of the nonvolatile memory element from changing from high to low or from low to high by applying the fluctuation suppression voltage pulse.
- the voltage value of the fluctuation suppression voltage pulse is set to a value that is smaller in absolute value than the voltage value required for the resistance state of the nonvolatile memory element to transition from high to low or from low to high. May be.
- a voltage pulse of +0.4 V is used as a voltage pulse for reading.
- the voltage value of the fluctuation suppressing voltage pulse may be larger in absolute value than the voltage value of the reading voltage pulse. Even if the voltage value of the fluctuation suppressing voltage pulse is a small value in absolute value, the effect of suppressing the fluctuation amount is recognized by increasing the pulse width. However, the pulse width may be short in order to realize a high-speed read operation.
- the voltage value of the fluctuation suppression voltage pulse may be set to a value that is larger in absolute value than the voltage value of the voltage pulse for reading.
- a voltage pulse is applied to suppress fluctuations, but the same effect can be obtained by applying a current pulse.
- the fluctuation phenomenon is considered to be caused by electrons being captured or released by dangling bonds existing in a minute filament.
- fluctuation of the resistance value of the resistance change element is suppressed by intentionally capturing and emitting the electrons.
- a dangling bond in a filament captures electrons by injecting electrons into the filament by applying a negative voltage pulse between both electrodes.
- electrons can be similarly injected into the filament.
- the second embodiment is a one-transistor / 1-nonvolatile memory unit type (1T1R type) nonvolatile memory device configured using the nonvolatile memory element described in the first embodiment.
- the configuration and operation of this nonvolatile memory device will be described below.
- FIG. 11 is a block diagram showing an example of the configuration of the nonvolatile memory device according to the second embodiment.
- the nonvolatile memory device 300 of this embodiment includes a memory cell array 301 including nonvolatile memory elements R311 to R322, an address buffer 302, a control unit 303, a row decoder 304, a word line A driver 305, a column decoder 306, and a bit line / plate line driver 307 are provided.
- the bit line / plate line driver 307 includes a sense circuit (sense amplifier), and can measure a current flowing through the bit line or the plate line.
- the memory cell array 301 includes two word lines W1 and W2 extending in parallel with each other, two bit lines B1 and B2 extending in parallel with each other across the word lines W1 and W2, and the bit lines B1 and B2.
- Four memory cells provided in a matrix corresponding to the intersections of two plate lines P1, P2 provided in one-to-one correspondence with B2, and word lines W1, W2 and bit lines B1, B2.
- MC311, MC312, MC321, and MC322 are provided.
- the memory cells MC311, MC312, MC321, and MC322 include a selection transistor T311 and a nonvolatile memory element R311, a selection transistor T312 and a nonvolatile memory element R312, a selection transistor T321 and a nonvolatile memory element R321, and a selection transistor T322 and a nonvolatile memory, respectively.
- the memory element R322 is constituted.
- the nonvolatile memory elements R311 to R322 correspond to the nonvolatile memory element 100 according to the first embodiment.
- the number or number of each of these components is not limited to the above.
- the number of memory cells included in the memory cell array 301 is not limited to the above four, and may be five or more.
- the plate line is arranged in parallel with the bit line, but the plate line may be arranged in parallel with the word line.
- the plate line is configured to apply a common potential to the connected transistors, but has a source line selection circuit and a driver having the same configuration as the row decoder 304 and the word line driver 305, and the selected source line and A configuration may be adopted in which the non-selected source line is driven with a different voltage (including polarity).
- the configuration of the memory cell array 301 will be further described.
- the memory cell MC311 selection transistor T311 and nonvolatile memory element R3111 is provided between the bit line B1 and the plate line P1, and the source of the selection transistor T311 and the nonvolatile memory cell MC311 are nonvolatile.
- the memory elements R311 are arranged in series to be connected. More specifically, the selection transistor T311 is connected to the bit line B1 and the nonvolatile memory element R311 between the bit line B1 and the nonvolatile memory element R311.
- the nonvolatile memory element R311 is connected to the selection transistor T311 and the plate.
- a selection transistor T311 and a plate line P1 are connected to the line P1.
- the gate of the selection transistor T311 is connected to the word line W1. Since the other memory cells MC312, MC321, and MC322 have the same configuration, description thereof is omitted.
- the address buffer 302 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 304 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 306.
- the address signal ADDRESS is a signal indicating the address of the selected memory cell among the memory cells MC311 to MC322.
- the row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS
- the column address signal COLUMN is also a signal indicating a column address.
- the control unit 303 selects any one of the LR write mode, the HR write mode, the fluctuation suppression mode, and the data read mode according to the mode selection signal MODE received from the external circuit, and selects the selected mode.
- the control corresponding to is performed.
- the LR write mode means that the nonvolatile memory element is brought into a low resistance state
- the HR write mode means that the nonvolatile memory element is brought into a high resistance state.
- the fluctuation suppression mode refers to applying a voltage pulse that suppresses fluctuation of the nonvolatile memory element
- the read mode reads data from the nonvolatile memory element (determines the resistance state of the nonvolatile memory element).
- the LR write mode and the HR write mode may be collectively referred to simply as “write mode”.
- each voltage is applied with reference to the plate line.
- control unit 303 In the LR write mode, the control unit 303 outputs a control signal CONT instructing “LR write voltage pulse application” to the bit line / plate line driver 307 in accordance with the input data Din received from the external circuit.
- control unit 303 In the HR write mode, the control unit 303 outputs a control signal CONT instructing “HR write voltage pulse application” to the bit line / plate line driver 307.
- the control unit 303 In the read mode, the control unit 303 outputs a control signal CONT instructing “fluctuation suppression voltage application” and “read voltage application” to the bit line / plate line driver 307. In this read mode, the control unit 303 further receives a signal I READ output from the bit line / plate line driver 307 and outputs output data Dout indicating a bit value corresponding to the signal I READ to an external circuit.
- This signal I READ is a signal indicating the current value of the current flowing through the plate lines P1 and P2 in the read mode.
- the row decoder 304 receives the row address signal ROW output from the address buffer 302, and selects one of the two word lines W1 and W2 according to the row address signal ROW.
- the word line driver 305 applies an activation voltage to the word line selected by the row decoder 304 based on the output signal of the row decoder 304.
- the column decoder 306 receives the column address signal COLUMN output from the address buffer 302, selects one of the two bit lines B1 and B2 according to the column address signal COLUMN, and selects the selected bit line. One of the two plate lines P1 and P2 corresponding to is selected.
- bit line / plate line driver 307 When the bit line / plate line driver 307 receives the control signal CONT instructing “LR write voltage pulse application” from the control unit 303 in the LR write mode, the bit line / plate line driver 307 selects it based on the output signal of the column decoder 306. An LR write voltage V WRITE (write voltage pulse) is applied between the selected bit line and the selected plate line. As a result, the nonvolatile memory element of the memory cell designated by the address buffer 302 enters a low resistance state.
- V WRITE write voltage pulse
- the column decoder 306 When the bit line / plate line driver 307 receives the control signal CONT instructing “HR write voltage pulse application” from the control unit 303 in the HR write mode, the column decoder 306 is based on the output signal of the column decoder 306. An HR write voltage V RESET (write voltage pulse) is applied between the selected bit line and the selected plate line. As a result, the nonvolatile memory element of the memory cell designated by the address buffer 302 enters a high resistance state.
- V RESET write voltage pulse
- bit line / plate line driver 307 receives the control signal CONT instructing “fluctuation suppression voltage application” and “read voltage application” from the control unit 303 in the fluctuation suppression mode and the read mode, and outputs the column decoder 306. Based on the signal, a fluctuation suppression voltage V FLUC (fluctuation suppression voltage pulse) and a read voltage V READ (read voltage pulse) are applied between the bit line selected by the column decoder 306 and the selected plate line.
- V FLUC fluctuation suppression voltage pulse
- V READ read voltage pulse
- the timing for performing the fluctuation suppression mode has various modes.
- the fluctuation suppression mode may be executed each time before performing the read mode, or the fluctuation suppression mode may be executed only before executing the first read mode among the read modes to be executed a plurality of times. Or you may perform fluctuation suppression mode for every specific period.
- the fluctuation suppression voltage V FLUC may be applied collectively to the plurality of nonvolatile memory elements at the block reading timing described above.
- the bit line / plate line driver 307 After applying the read voltage V READ , the bit line / plate line driver 307 outputs a signal I READ indicating the current value of the current flowing through the plate line to the control unit 303.
- the control unit 303 determines whether the resistance state of the nonvolatile memory element is high or low according to the signal I READ and outputs output data Dout indicating the bit value obtained as a result.
- the voltage values of the LR write voltage V WRITE and the HR write voltage V RESET are set to, for example, ⁇ 2.4 V and +2.0 V, respectively, and their pulse widths are set to 100 ns.
- the voltage value of the read voltage V READ is set to + 0.4V, for example.
- the voltage value of the fluctuation suppression voltage V FLUC is set to, for example, +0.7 V or ⁇ 0.7 V, and the pulse width is set to 100 ns.
- the present embodiment is not limited to this.
- an HR write voltage application unit that applies an HR write voltage pulse, an LR write voltage application unit that applies an LR write voltage pulse, and a fluctuation suppression voltage application unit (first voltage application unit) that applies a fluctuation suppression voltage pulse may be a separate circuit, or a part thereof may be shared.
- a voltage pulse is applied to suppress fluctuations, but the same effect can be obtained by applying a current pulse.
- the fluctuation phenomenon is caused by the fact that electrons are captured or released by dangling bonds existing in a minute filament.
- the amount of fluctuation of the resistance value is suppressed by intentionally capturing and emitting the electrons.
- a dangling bond in a filament captures electrons by injecting electrons into the filament by applying a negative voltage pulse between both electrodes.
- electrons can be similarly injected into the filament.
- the third embodiment is a cross-point type nonvolatile memory device configured using the nonvolatile memory element described in the first embodiment.
- the cross-point type nonvolatile storage device is a storage device in a mode in which an active layer is interposed at an intersection (a three-dimensional intersection) between a word line and a bit line. The configuration and operation of this nonvolatile memory device will be described below.
- FIG. 12 is a block diagram showing an example of the configuration of the nonvolatile memory device according to Embodiment 3.
- the nonvolatile memory device 400 of this embodiment includes a memory cell array 401 including nonvolatile memory elements R11 to R33, an address buffer 402, a control unit 403, a row decoder 404, a word A line driver 405, a column decoder 406, and a bit line driver 407 are provided.
- the bit line driver 407 includes a sense circuit and can measure a current flowing through the bit line.
- Memory cell array 401 includes a plurality of word lines W1, W2, and W3 formed so as to extend in parallel with each other, and bit lines formed so as to cross these word lines W1, W2, and W3 and extend in parallel with each other.
- B1, B1, and B3 are provided.
- the word lines W1, W2, and W3 are formed in a first plane parallel to the main surface of the substrate (not shown), and the bit lines B1, B1, and B3 are formed from the first plane. It is formed in a second plane located above or below and substantially parallel to the first plane.
- the word lines W1, W2, W3 and the bit lines B1, B1, B3 are three-dimensionally crossed, and a plurality of memory cells MC11, MC12, MC13, MC21, MC22, MC23, MC31 corresponding to the three-dimensional intersection.
- MC32, MC33 (hereinafter referred to as “memory cells MC11, MC12,...”) are provided.
- Each of the memory cells MC11, MC12,... Has a non-volatile memory element R11, R12, R13, R21, R22, R23, R31, R32, R33 connected in series and a current composed of, for example, a bidirectional diode.
- Control elements D11, D12, D13, D21, D22, D23, D31, D32, and D33 are provided.
- These nonvolatile memory elements R11 to R33 are connected to bit lines B1, B1, and B3, and current control elements D11 to D33 are connected to the nonvolatile memory elements and word lines W1, W2, and W3.
- the nonvolatile memory elements R11 to R22 correspond to the nonvolatile memory element 100 according to the first embodiment.
- MIM Metal-Insulator-Metal
- MSM Metal-Semiconductor-Metal
- the address buffer 402 receives an address signal ADDRESS from an external circuit (not shown), outputs a row address signal ROW to the row decoder 404 based on the address signal ADDRESS, and outputs a column address signal COLUMN to the column decoder 406.
- the address signal ADDRESS is a signal indicating the address of the selected memory cell among the memory cells MC11, MC12,.
- the row address signal ROW is a signal indicating a row address among the addresses indicated by the address signal ADDRESS, and the column address signal COLUMN is also a signal indicating a column address.
- the control unit 403 selects one of the LR write mode, the HR write mode, and the read mode according to the mode selection signal MODE received from the external circuit, and performs control corresponding to the selected mode.
- each voltage is applied with reference to the bit line.
- the control unit 403 In the LR write mode and the HR write mode, the control unit 403 outputs an LR write voltage pulse and an HR write voltage pulse to the word line driver 405 according to the input data Din received from the external circuit. As a result, the nonvolatile memory element of the memory cell designated by the address buffer 402 enters a low resistance state or a high resistance state.
- the control unit 403 In the read mode, the control unit 403 outputs the fluctuation suppression voltage pulse and the read voltage pulse to the word line driver 405. It should be noted that the timing at which the fluctuation suppression voltage V FLUC is applied is similar to the second embodiment in that various modes are assumed. In this read mode, the control unit 403 further detects the current value of the current flowing between the bit line B2 and the word line W2, and outputs the output data Dout indicating the bit value corresponding to the current value to the external circuit. Output.
- the row decoder 404 receives the row address signal ROW output from the address buffer 402, and selects any one of the word lines W1, W2, and W3 according to the row address signal ROW.
- the word line driver 405 applies a predetermined voltage to the word line selected by the row decoder 404 based on the output signal of the row decoder 404.
- the column decoder 406 receives the column address signal COLUMN output from the address buffer 402, and selects any one of the bit lines B1, B2, and B3 according to the column address signal COLUMN.
- the bit line driver 407 sets the bit line selected by the column decoder 406 to the ground state based on the output signal of the column decoder 406.
- nonvolatile memory element data read method and nonvolatile memory device have been described based on the first to third embodiments. However, the present invention is limited to these embodiments. is not. A form obtained by subjecting each embodiment to various modifications conceived by those skilled in the art without departing from the gist of the present invention, and a form realized by arbitrarily combining the components in each embodiment Included in the invention.
- the nonvolatile memory device does not necessarily include a word line driver and a bit line driver.
- a 1T1R type nonvolatile memory device having a memory cell including a transistor and a nonvolatile memory element may be used.
- the nonvolatile memory device may include an offset current detection cell having a resistance value higher than the resistance value of the memory element in a high resistance state when the memory element performs a memory operation.
- a multilayer cross-point nonvolatile memory device may be formed by stacking memory cell arrays.
- the positional relationship between the nonvolatile memory element and the current control element may be interchanged. That is, the word line may be connected to the nonvolatile memory element, and the bit line may be connected to the current control element.
- bit line and / or the word line may also serve as an electrode in the nonvolatile memory element.
- the circuit for writing to the memory cell and the circuit for performing the initial break operation are not clearly shown, but such a circuit may be provided.
- the nonvolatile memory element data reading method and nonvolatile memory device of the present invention are useful as a nonvolatile memory element data reading method and memory device used for various electronic devices such as personal computers and portable telephones, respectively. .
- Nonvolatile memory element 101
- Substrate 102
- First electrode 104
- Variable resistance layer 104a
- First oxide layer 104b
- Second oxide layer 105
- Micro area 202 Load resistance 203, 204 Terminal 300, 400
Abstract
Description
まず、本発明の実施の形態を説明する前に、本発明の基礎となった技術について説明する。
[不揮発性記憶素子の構成]
図1A及び図1Bは、実施の形態1に係る不揮発性記憶素子の構成を示す断面図である。
次に、本実施の形態の不揮発性記憶素子100の製造方法について説明する。なお、以下で説明する、各工程における手法、材料、膜厚、その他の条件等についてはあくまでも例示であり、本実施の形態はこれに限定されない。
以下では、上述のようにして作製された不揮発性記憶素子100の抵抗状態の保持特性について、本発明者等が実験によって新たに見出した知見について詳細に説明する。なお、以下で説明する、電圧値、パルス幅、印加回数、抵抗値等はあくまでも、当該知見を説明する実験例を示すものであり、本実施の形態はこれに限定されない。
不揮発性記憶素子100の第1の電極103及び第2の電極105に電気的パルス信号を与えることにより抵抗変化を起こさせた。以下では、電気的パルス信号として電圧パルスを用いた場合について説明する。なお、本明細書では、第1の電極103を基準にして電圧の正負を表現する。すなわち、第1の電極103に対して、高い電圧を第2の電極105に印加した場合の電圧は“正”であり、同じく低い電圧を第2の電極105に印加した場合の電圧は“負”である。不揮発性記憶素子100は、正の電圧が与えられた場合に高抵抗化し、負の電圧が与えられた場合に低抵抗化する。なお、本明細書中において、“正極性”は“不揮発性記憶素子を高抵抗化する電圧(高抵抗化書き込み電圧)と同極性”に読み替え可能であり、“負極性”は“不揮発性記憶素子を低抵抗化する電圧(低抵抗化書き込み電圧)と同極性”に読み替え可能である。
上述したようにして抵抗値を設定した不揮発性記憶素子201を室温に保持し、20秒毎に50mVの電圧を印加して不揮発性記憶素子201の抵抗値を測定した。なお、このような50mV程度の低い電圧では、不揮発性記憶素子201の抵抗値は変化しない。
上述したように、抵抗変化現象は、抵抗変化層104中に微小なフィラメントが形成され、この微小なフィラメント中で酸化還元反応が起こり、その抵抗値が変化することによって発生すると考えられる。したがって、今回発明者等が発見した揺らぎ現象も、この微小なフィラメント中の導通状態が何らかの影響で変化することにより発生していると考えられる。具体的には、酸素原子が不完全な結合をしたり、乖離をしたりすることで揺らぎが発生している可能性があると考えられる。また、微小なフィラメント内に存在するダングリングボンドに電子が捕獲されたり、放出されたりすることで、電気的なポテンシャルが変化して抵抗状態が揺らいでいる可能性も考えられる。したがって、微小なフィラメントが関係して抵抗値が増減するような構造を有する抵抗変化型の不揮発性記憶素子であれば、その程度の大小はあるものの、揺らぎ現象は必然的に発生するものであると推測される。
上述したように、正極性の揺らぎ抑制電圧パルスを用いることにより、抵抗値が増大する方向の揺らぎに対して、抵抗値を減少させることができる。他方、負極性の揺らぎ抑制電圧パルスを用いることにより、抵抗値が減少する方向の揺らぎに対して、抵抗値を増大させることができる。
不揮発性記憶素子に対して書き込みを行った後、揺らぎ現象によって抵抗値が設定抵抗値から大きく変化して、データの読み出し誤りが生じる可能性がある。このような不都合を回避するために、本実施の形態では、不揮発性記憶素子は、第1の電極と、第2の電極と、第1の電極及び第2の電極間に介在し、金属酸化物から構成され、周囲の領域に比べて酸素不足度の大きい微小領域を有する抵抗変化層とを備え、第1の電極及び第2の電極間に第1の電圧パルスを印加することにより抵抗変化層の抵抗状態が低抵抗状態から高抵抗状態へ変化し、第1の電極及び第2の電極間に第2の電圧パルスを印加することにより抵抗変化層の抵抗状態が高抵抗状態から低抵抗状態へ変化する特性を有し、抵抗変化層の抵抗状態に応じてデータが記憶されており、データ読み出し方法は、高抵抗化又は低抵抗化された抵抗変化層の第1の電極及び第2の電極間に、第1の電圧パルス及び第2の電圧パルスよりも電圧値の絶対値が小さい第3の電圧パルスを印加するステップと、第3の電圧パルスを印加するステップの後に、第1の電極及び第2の電極間に、第1の電圧パルス及び第2の電圧パルスよりも電圧値の絶対値が小さい第4の電圧パルスを印加して、抵抗変化層の抵抗状態を読み出すステップと、を含む。
以下、揺らぎ抑制電圧パルスの電圧値の範囲の一例について説明する。
実施の形態2は、実施の形態1において説明した不揮発性記憶素子を用いて構成される、1トランジスタ/1不揮発性記憶部型(1T1R型)の不揮発性記憶装置である。以下、この不揮発性記憶装置の構成及び動作について説明する。
実施の形態3は、実施の形態1において説明した不揮発性記憶素子を用いて構成される、クロスポイント型の不揮発性記憶装置である。ここで、クロスポイント型の不揮発性記憶装置とは、ワード線とビット線との交点(立体交差点)にアクティブ層を介在させた態様の記憶装置である。以下、この不揮発性記憶装置の構成及び動作について説明する。
101 基板
102 層間絶縁膜
103 第1の電極
104 抵抗変化層
104a 第1の酸化物層
104b 第2の酸化物層
105 第2の電極
106 微小領域
202 負荷抵抗
203,204 端子
300,400 不揮発性記憶装置
301,401 メモリセルアレイ
302,402 アドレスバッファ
303,403 制御部
304,404 行デコーダ
305,405 ワード線ドライバ
306,406 列デコーダ
307 ビット線/プレート線ドライバ
407 ビット線ドライバ
MC11~MC33,MC311~MC322 メモリセル
T311~T322 選択トランジスタ
D11~D33 電流制御素子
Claims (42)
- 抵抗変化型の不揮発性記憶素子のデータ読み出し方法であって、
前記不揮発性記憶素子は、
第1の電極と、第2の電極と、前記第1の電極及び前記第2の電極間に介在し、金属酸化物から構成され、周囲の領域に比べて酸素不足度の大きい微小領域を有する抵抗変化層とを備え、
前記第1の電極及び前記第2の電極間に第1の電圧パルスを印加することにより前記抵抗変化層の抵抗状態が低抵抗状態から高抵抗状態へ変化し、前記第1の電極及び前記第2の電極間に第2の電圧パルスを印加することにより前記抵抗変化層の抵抗状態が高抵抗状態から低抵抗状態へ変化する特性を有し、
前記抵抗変化層の抵抗状態に応じてデータが記憶されており、
前記データ読み出し方法は、
高抵抗化又は低抵抗化された前記抵抗変化層の前記第1の電極及び前記第2の電極間に、前記第1の電圧パルス及び前記第2の電圧パルスよりも電圧値の絶対値が小さい第3の電圧パルスを印加するステップと、
前記第3の電圧パルスを印加するステップの後に、前記第1の電極及び前記第2の電極間に、前記第1の電圧パルス及び前記第2の電圧パルスよりも電圧値の絶対値が小さい第4の電圧パルスを印加して、前記抵抗変化層の抵抗状態を読み出すステップと、
を含む、不揮発性記憶素子のデータ読み出し方法。 - 前記微小領域は、前記第2の電極から前記第1の電極に向けて形成され、前記第2の電極と接し前記第1の電極と接しない形状を有している、
請求項1に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記抵抗変化層は、抵抗値が時間経過に従ってランダムに変化する、揺らぎの特性を有する、
請求項1又は2に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記抵抗変化層は、第1の酸化物層と、前記第1の酸化物層よりも酸素不足度の大きい第2の酸化物層とを備え、前記微小領域は前記第1の酸化物層よりも酸素不足度が大きい、
請求項1乃至3の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第1の酸化物層は前記第2の電極と接し、
前記微小領域は、前記第2の電極と接し、前記第2の電極から前記第1の酸化物層を貫いて前記第1の電極に向けて形成されている、
請求項4に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記不揮発性記憶素子は、データが記憶された後であって、次に抵抗状態を変化させるステップが実行されるまでの間に、前記抵抗状態を読み出すステップを複数回繰り返す場合、複数回の前記抵抗状態を読み出すステップのそれぞれを実行する前に、その都度前記第3の電圧パルスを印加するステップを実行する、
請求項1乃至5の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第1の電圧パルスと前記第2の電圧パルスとは異なる極性である、
請求項1乃至6の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第3の電圧パルスを印加するステップにおいて、前記第1の電極及び前記第2の電極間に前記第4の電圧パルスよりも電圧値の絶対値が大きい前記第3の電圧パルスを印加する、
請求項1乃至7の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第1の電圧パルスと前記第3の電圧パルスとは同じ極性である、
請求項1乃至8の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第2の電圧パルスと前記第3の電圧パルスとは同じ極性である、
請求項1乃至8の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 抵抗変化型の不揮発性記憶素子のデータ読み出し方法であって、
前記不揮発性記憶素子は、
第1の電極と、第2の電極と、前記第1の電極及び前記第2の電極間に介在し、金属酸化物から構成され、周囲の領域に比べて酸素不足度の大きい微小領域を有する抵抗変化層とを備え、
前記第1の電極及び前記第2の電極間に第1の電流パルスを印加することにより、前記抵抗変化層の抵抗状態が低抵抗状態から高抵抗状態へ変化し、前記第1の電極及び前記第2の電極間に第2の電流パルスを印加することにより前記抵抗変化層の抵抗状態が高抵抗状態から低抵抗状態へ変化する特性を有し、
前記抵抗変化層の抵抗状態に応じてデータが記憶されており、
前記データ読み出し方法は、
高抵抗化又は低抵抗化された前記抵抗変化層の前記第1の電極及び前記第2の電極間に、前記第1の電流パルス及び前記第2の電流パルスよりも電流値の絶対値が小さい第3の電流パルスを印加するステップと、
前記第3の電流パルスを印加するステップの後に、前記第1の電極及び前記第2の電極間に、前記第1の電流パルス及び前記第2の電流パルスよりも電流値の絶対値が小さい第4の電流パルスを印加して、前記抵抗変化層の抵抗状態を読み出すステップと、
を含む、不揮発性記憶素子のデータ読み出し方法。 - 前記微小領域は、前記第2の電極から前記第1の電極に向けて形成され、前記第2の電極と接し前記第1の電極と接しない形状を有している、
請求項11に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記抵抗変化層は、抵抗値が時間経過によってランダムに変化する、揺らぎの特性を有する、
請求項11又は12に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記抵抗変化層は、第1の酸化物層と、前記第1の酸化物層よりも酸素不足度の大きい第2の酸化物層とを備え、前記微小領域は前記第1の酸化物層よりも酸素不足度が大きい、
請求項11乃至13の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第1の酸化物層は前記第2の電極と接し、
前記微小領域は、前記第2の電極と接し、前記第2の電極から前記第1の酸化物層を貫いて前記第1の電極に向けて形成されている、
請求項14に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記不揮発性記憶素子は、データが記憶された後であって、次に抵抗状態を変化させるステップが実行されるまでの間に、前記抵抗状態を読み出すステップを複数回繰り返す場合、複数回の前記抵抗状態を読み出すステップのそれぞれを実行する前に、その都度前記第3の電流パルスを印加するステップを実行する、
請求項11乃至15の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第1の電流パルスと前記第2の電流パルスとは異なる極性である、
請求項11乃至16の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第3の電流パルスを印加するステップにおいて、前記第1の電極及び前記第2の電極間に前記第4の電流パルスよりも電流値の絶対値が大きい前記第3の電流パルスを印加する、
請求項11乃至17の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第1の電流パルスと前記第3の電流パルスとは同じ極性である、
請求項11乃至18の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記第2の電流パルスと前記第3の電流パルスとは同じ極性である、
請求項11乃至18の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 前記金属酸化物は、タンタル酸化物である、
請求項1乃至20の何れか1項に記載の不揮発性記憶素子のデータ読み出し方法。 - 抵抗変化型の不揮発性記憶素子を有する不揮発性記憶装置であって、
前記不揮発性記憶素子は、
第1の電極と、第2の電極と、前記第1の電極及び前記第2の電極間に介在し、金属酸化物から構成され、周囲の領域に比べて酸素不足度の大きい微小領域を有する抵抗変化層とを備え、
前記第1の電極及び前記第2の電極間に第1の電圧パルスを印加することにより前記抵抗変化層の抵抗状態が低抵抗状態から高抵抗状態へ変化し、前記第1の電極及び前記第2の電極間に第2の電圧パルスを印加することにより前記抵抗変化層の抵抗状態が高抵抗状態から低抵抗状態へ変化する特性を有し、
前記抵抗変化層の抵抗状態に応じてデータが記憶されており、
高抵抗化又は低抵抗化された前記抵抗変化層の前記第1の電極及び前記第2の電極間に、前記第1の電圧パルス及び前記第2の電圧パルスよりも電圧値の絶対値が小さい第3の電圧パルスを印加する第1の電圧印加部と、
高抵抗化又は低抵抗化された前記抵抗変化層の前記第1の電極及び前記第2の電極間に、前記第1の電圧パルス及び前記第2の電圧パルスよりも電圧値の絶対値が小さい、読み出し用の第4の電圧パルスを印加する第2の電圧印加部と、
前記第3の電圧印加部に前記第3の電圧の印加を指示する制御信号を出力する揺らぎ抑制モードと、前記揺らぎ抑制モードの後に、前記第4の電圧印加部に前記第4の電圧の印加を指示する制御信号を出力するデータ読み出しモードとを選択的に実行する制御部と、
を備える、
不揮発性記憶装置。 - 前記微小領域は、前記第2の電極から前記第1の電極に向けて形成され、前記第2の電極と接し前記第1の電極と接しない形状を有している、
請求項22に記載の不揮発性記憶装置。 - 前記抵抗変化層は、抵抗値が時間経過に従ってランダムに変化する、揺らぎの特性を有する、
請求項22又は23に記載の不揮発性記憶装置。 - 前記制御部は、
前記読み出しモードが複数回実行される場合、複数回の前記読み出しモードのそれぞれを実行する前にその都度、前記揺らぎ抑制モードを実行する、
請求項22乃至24の何れか1項に記載の不揮発性記憶装置。 - 前記第1の電圧パルスと前記第2の電圧パルスとは異なる極性である、
請求項22乃至25の何れか1項に記載の不揮発性記憶装置。 - 前記抵抗変化層は、第1の酸化物層と、前記第1の酸化物層よりも酸素不足度の大きい第2の酸化物層とを含み、
前記第1の酸化物層中に、前記第1の酸化物層よりも酸素不足度の大きい微小領域を有する、
請求項22乃至26の何れか1項に記載の不揮発性記憶装置。 - 前記第1の酸化物層は前記第2の電極と接し、
前記微小領域は、前記第2の電極と接し、前記第2の電極から前記第1の酸化物層を貫いて前記第1の電極に向けて形成されている、
請求項27に記載の不揮発性記憶装置。 - 前記第1の電圧印加部が、前記第1の電極及び前記第2の電極間に前記第4の電圧パルスよりも電圧値の絶対値が大きい前記第3の電圧パルスを印加するように構成されている、
請求項22乃至27の何れか1項に記載の不揮発性記憶装置。 - 前記第1の電圧パルスと前記第3の電圧パルスとは同じ極性である、
請求項22乃至29の何れか1項に記載の不揮発性記憶装置。 - 前記第2の電圧パルスと前記第3の電圧パルスとは同じ極性である、
請求項22乃至29の何れか1項に記載の不揮発性記憶装置。 - 抵抗変化型の不揮発性記憶素子を有する不揮発性記憶装置であって、
前記不揮発性記憶素子は、
第1の電極と、第2の電極と、前記第1の電極及び前記第2の電極間に介在し、金属酸化物から構成され、周囲の領域に比べて酸素不足度の大きい微小領域を有する抵抗変化層とを備え、
前記第1の電極及び前記第2の電極間に第1の電流パルスを印加することにより前記抵抗変化層の抵抗状態が低抵抗状態から高抵抗状態へ変化し、前記第1の電極及び前記第2の電極間に第2の電流パルスを印加することにより前記抵抗変化層の抵抗状態が高抵抗状態から低抵抗状態へ変化する特性を有し、
前記抵抗変化層の抵抗状態に応じてデータが記憶されており、
高抵抗化又は低抵抗化された前記抵抗変化層の前記第1の電極及び前記第2の電極間に、前記第1の電流パルス及び前記第2の電流パルスよりも電流値の絶対値が小さい第3の電流パルスを印加する第1の電流印加部と、
高抵抗化又は低抵抗化された前記抵抗変化層の前記第1の電極及び前記第2の電極間に、前記第1の電流パルス及び前記第2の電流パルスよりも電流値の絶対値が小さい、読み出し用の第4の電流パルスを印加する第2の電流印加部と、
前記第3の電流印加部に前記第3の電流の印加を指示する制御信号を出力する揺らぎ抑制モードと、前記揺らぎ抑制モードの後に、前記第4の電流印加部に前記第4の電流の印加を指示する制御信号を出力するデータ読み出しモードとを選択的に実行する制御部と、
を備える、
不揮発性記憶装置。 - 前記微小領域は、前記第2の電極から前記第1の電極に向けて形成され、前記第2の電極と接し前記第1の電極と接しない形状を有している、
請求項32に記載の不揮発性記憶装置。 - 前記抵抗変化層は、抵抗値が時間経過に従ってランダムに変化する、揺らぎの特性を有する、
請求項32又は33に記載の不揮発性記憶装置。 - 前記制御部は、
前記読み出しモードが複数回実行される場合、複数回の前記読み出しモードのそれぞれを実行する前にその都度、前記揺らぎ抑制モードを実行する、
請求項32乃至34の何れか1項に記載の不揮発性記憶装置。 - 前記第1の電流パルスと前記第2の電流パルスとは異なる極性である、
請求項32乃至35の何れか1項に記載の不揮発性記憶装置。 - 前記抵抗変化層は、第1の酸化物層と、前記第1の酸化物層よりも酸素不足度の大きい第2の酸化物層とを含み、
前記第1の酸化物層中に、前記第1の酸化物層よりも酸素不足度の大きい微小領域を有する、
請求項32乃至36の何れか1項に記載の不揮発性記憶装置。 - 前記第1の酸化物層は前記第2の電極と接し、
前記微小領域は、前記第2の電極と接し、前記第2の電極から前記第1の酸化物層を貫いて前記第1の電極に向けて形成されている、
請求項37に記載の不揮発性記憶装置。 - 前記第1の電流印加部が、前記第1の電極及び前記第2の電極間に前記第4の電流パルスよりも電流値の絶対値が大きい前記第3の電流パルスを印加するように構成されている、
請求項32乃至38の何れか1項に記載の不揮発性記憶装置。 - 前記第1の電流パルスと前記第3の電流パルスとは同じ極性である、
請求項32乃至39の何れか1項に記載の不揮発性記憶装置。 - 前記第2の電流パルスと前記第3の電流パルスとは同じ極性である、
請求項32乃至39の何れか1項に記載の不揮発性記憶装置。 - 前記金属酸化物は、タンタル酸化物である、
請求項32乃至41の何れか1項に記載の不揮発性記憶装置。
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JP2017198661A (ja) * | 2016-04-26 | 2017-11-02 | パナソニックIpマネジメント株式会社 | 気体検出装置及び気体検出方法 |
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