WO2013107320A1 - 浪涌保护电路 - Google Patents

浪涌保护电路 Download PDF

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Publication number
WO2013107320A1
WO2013107320A1 PCT/CN2013/070318 CN2013070318W WO2013107320A1 WO 2013107320 A1 WO2013107320 A1 WO 2013107320A1 CN 2013070318 W CN2013070318 W CN 2013070318W WO 2013107320 A1 WO2013107320 A1 WO 2013107320A1
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WO
WIPO (PCT)
Prior art keywords
circuit
diode
field effect
effect transistor
surge protection
Prior art date
Application number
PCT/CN2013/070318
Other languages
English (en)
French (fr)
Inventor
彭学文
曹文宗
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP13738500.1A priority Critical patent/EP2706639B1/en
Publication of WO2013107320A1 publication Critical patent/WO2013107320A1/zh
Priority to US14/145,067 priority patent/US9350164B2/en

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
    • H02H9/025—Current limitation using field effect transistors
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/041—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage using a short-circuiting device
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H02H11/002—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
    • H02H9/047—Free-wheeling circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H1/00—Details of emergency protective circuit arrangements
    • H02H1/04—Arrangements for preventing response to transient abnormal conditions, e.g. to lightning or to short duration over voltage or oscillations; Damping the influence of dc component by short circuits in ac networks
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/005—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection avoiding undesired transient conditions

Definitions

  • the present invention relates to the field of power electronics, and more particularly to a surge protection circuit.
  • a surge protection circuit is usually provided between the DC input terminal and the rear-stage circuit, and a negative wave occurs.
  • the power supply of the latter circuit is turned off in time, through the varistor
  • the (VR) or transient voltage suppressor (TVS) bleeds the inrush current to provide surge protection for the downstream circuitry.
  • the surge protection circuit includes a shutdown circuit and a bleeder circuit.
  • the shutdown circuit is specifically configured to: a diode D1 and a D2 are respectively disposed at the positive and negative terminals of the DC input terminal, wherein the anode of the D1 is connected to the anode of the DC input, the cathode of the D2 is connected to the cathode of the DC input, and the diodes D1 and D2 are connected.
  • a capacitor C is also disposed between the latter circuits, and the two ends of the capacitor C are respectively connected to the cathode of D1 and the anode of D2.
  • the diodes D1 and D2 of the shutdown circuit can also be replaced with the FETs M1 and M2.
  • the bleeder circuit is a VR or TVS connected between the positive and negative terminals of the DC input.
  • the working principle of the existing surge protection circuit is as follows: In normal operation, the diode (or FET) of the shutdown circuit is in a forward conduction state, and the current flows from the positive pole of the DC input to the DC input through the rear stage circuit. negative electrode. When a negative surge occurs, the current flows briefly from the negative pole to the positive pole. At this time, D1 and D2 (or Ml and M2) are reverse-cut, achieving the shutdown function. Protect the rear stage circuit. VR can vent the inrush current according to the voltage regulation resistor; TVS can convert the inrush current into heat dissipation, which acts as a bleed.
  • diodes D1 and D2 will experience a high reverse voltage when turned off (the reverse voltage is equal to the sum of the varistor clamp voltage and capacitor C).
  • the reverse voltage is equal to the sum of the varistor clamp voltage and capacitor C.
  • the diode or FET of the shutdown circuit can only select a higher specification model.
  • the higher clamping voltage severely limits the selection of the electronic device, and the diode D1 is likely to cause a negative surge due to the higher clamping voltage.
  • D2 (or FETs Ml and M2) failure, damage.
  • Embodiments of the present invention provide a surge protection circuit that can reduce the clamping voltage of a negative surge, thereby facilitating device selection and avoiding device damage caused by negative surge.
  • the embodiment of the present invention adopts the following technical solutions:
  • a surge protection circuit includes: an input terminal for providing a DC power source, an output terminal for connecting the rear stage circuit, and a shutdown circuit connected to the output terminal, the surge protection circuit further comprising: a bleeder circuit between the input terminal and the shutdown circuit;
  • the bleeder circuit comprises: a diode and a field effect transistor
  • a cathode of the diode is connected to a positive pole of the input end, an anode of the diode is connected to a source of the FET; a gate of the FET is connected to a positive pole of the input end, the field effect transistor The drain is connected to the negative terminal of the input terminal, and the parasitic diode of the FET is opposite to the direction of the diode.
  • the surge protection circuit provided by the embodiment of the invention passes through a diode and a field effect transistor Compared with the technology of venting surge current, the diode and FET have a low conduction voltage drop, which can effectively suppress the clamp voltage of the negative surge, thereby facilitating device selection of the shutdown circuit and avoiding negative waves.
  • the surge causes damage to the device.
  • FIG. 1 is a schematic diagram of a surge protection circuit in the prior art
  • FIG. 2 is a schematic diagram of a surge protection circuit according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of another surge protection circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram of another surge protection circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic diagram of another surge protection circuit according to an embodiment of the present invention.
  • An embodiment of the present invention provides a surge protection circuit, as shown in FIG. 2, including: an input terminal for providing a DC power supply, an output terminal for connecting the rear stage circuit 13, and a shutdown connected to the output terminal a circuit 11 and a bleeder circuit 12 coupled between the input terminal and the shutdown circuit.
  • the bleeder circuit 12 includes: a diode D and a field effect transistor Q.
  • a cathode of the diode D is connected to the anode of the input terminal, an anode of the diode D is connected to a source of the field effect transistor Q, and a gate of the field effect transistor Q is connected to the anode of the input terminal.
  • the drain of the field effect transistor Q is connected to the negative terminal of the input terminal, and the parasitic diode of the field effect transistor Q is opposite to the direction of the diode D.
  • the input end of the surge protection circuit includes the positive side of the input terminal and the negative side of the input terminal, and is the power source of the rear stage circuit 13, for example, the positive terminal of the input terminal is connected to the positive pole of the power source, and the negative pole of the input terminal is connected to the negative pole of the power source.
  • the output of the surge protection circuit also includes two sides of the positive pole and the negative pole for connecting the rear stage circuit 13 to supply power to the rear stage circuit 13.
  • the break circuit 11 is disposed between the bleeder circuit 12 and the rear stage circuit 13.
  • the specific composition of the turn-off circuit 11 can be referred to the prior art.
  • a diode D1 and a D2 are respectively disposed at the positive and negative terminals of the DC input terminal, wherein the anode of D1 is connected to the anode of the DC input, and the cathode of D1 is connected to the anode of the output terminal.
  • the anode of D2 is connected to the negative terminal of the output terminal, and the cathode of D2 is connected to the negative electrode of the DC input.
  • a capacitor C may be disposed between the diodes D1 and D2 and the subsequent stage circuit, and the two ends of the capacitor C are respectively connected to the cathode of D1 and the anode of D2.
  • the diodes D1 and D2 in the above-mentioned shutdown circuit 13 can also be replaced with the field effect transistors M1 and M2, and the connection direction of the parasitic diodes of the field effect transistors M1 and M2 is the same as the connection direction of D1 and D2.
  • the field effect transistor Q in the bleeder circuit 12 may be an N-Metal-Oxide-Semiconductor (NMOS), and the connection direction of the parasitic diode of the field effect transistor Q is opposite to the connection direction of the diode D.
  • NMOS N-Metal-Oxide-Semiconductor
  • the FET Q In the initial state, the FET Q is not charged, and the FET Q can play the role of anti-reverse connection. If the positive and negative terminals of the input terminal are reversed, the parasitic diode of the FET Q will be in the off state, and there will be no current flow. Preventing a reverse current from being supplied to the input terminal causes a large reverse current to flow into the bleeder circuit 12, damaging the electronics in the bleeder circuit 12.
  • the diode in the shutdown circuit 11 When in normal operation, the diode in the shutdown circuit 11 is turned on, and the shutdown circuit 11 is turned on, which can normally supply power to the subsequent circuit 13.
  • the parasitic diode of the field effect transistor Q is reverse-cut, and there is no current in the bleeder circuit 12.
  • the forward voltage applied between the gate and the drain of the field effect transistor Q causes an electric potential to be formed between the gate and the source of the field effect transistor Q to complete charging of the field effect transistor Q.
  • an instantaneous reverse voltage appears in the surge protection circuit.
  • the diodes D1 and D2 in the shutdown circuit 11 are reversely turned off, and the shutdown circuit 11 implements a shutdown function to prevent the negative surge current from entering.
  • the FET Q since the FET Q has been charged, the previously stored potential can be released when a reverse surge occurs, and the FET Q is turned on, so that the negative surge current flows from the drain of the FET Q. , and the source flows out, and flows through the diode D to complete the discharge of the negative surge.
  • the field effect transistor Q can use the effect tube of the large current and low voltage field as much as possible, thereby providing a large bleeder current, providing a venting path for the negative surge quickly and effectively, and ensuring a better bleed path.
  • the low voltage drop clamps the voltage during negative surges to very low.
  • the bleeder circuit 12 of the surge protection circuit further includes: a resistor R.
  • the resistor R is connected between the gate of the field effect transistor Q and the anode of the input terminal.
  • a resistor R may be added between the gate of the field effect transistor Q and the positive terminal of the input terminal to share the load when the surge or voltage is unstable. Part of the voltage, reducing the voltage that the field effect transistor Q is subjected to, protects the field effect transistor Q.
  • the bleeder circuit 12 of the surge protection circuit further includes: a Zener diode Z1.
  • the Zener diode Z1 is connected between the source and the gate of the FET Q.
  • a Zener Z1 is added between the gate and the drain of the FET Q, the anode of the Zener Z1 is connected to the source of the FET Q, and the cathode of the Zener Z1 and the FET Q
  • the voltage value can have more room for adjustment. For example, the voltage E between the positive and negative terminals of the input can be increased to 220v.
  • the bleeder circuit 12 of the surge protection circuit further includes: a capacitor Cl.
  • the capacitor C1 is connected in parallel with the Zener diode Z1 and connected between the source and the gate of the field effect transistor Q.
  • a capacitor C1 is connected between the source and the gate of the field effect transistor Q, and the potential stored in the normal operation of the field effect transistor Q can be temporarily stored, and the potential between the gate and the source of the field effect transistor Q is slowed down.
  • the drain can maintain the conduction state of the FET Q, prolong the time when the bleeder circuit 12 7 is subjected to a negative surge, thereby fully venting the negative surge and protecting the rear stage circuit 13.
  • the voltage (clamping voltage) of the shutdown circuit is the conduction voltage drop of the FET Q and the forward guidance of the diode D.
  • the sum of the voltage drop for example, on the premise of the input voltage of 220V, if the conduction voltage drop of the negative surge FET Q is about 60v, and the forward voltage drop of the diode D is only O. lv,
  • the clamp voltage can be controlled to a low voltage state of about 60. lv. Therefore, it provides a reliable bleed path for negative surges, clamps to a low level in the case of negative surges, reduces the voltage specifications of diodes and FETs in the shutdown circuit, and reduces the surge protection circuit. cost.
  • the surge protection circuit provided by the embodiment of the invention realizes the discharge of the negative surge current through a diode and a field effect tube, and the rushing of the surge current through the varistor or the transient voltage suppressor in the prior art.
  • the diode and the FET have a low conduction voltage drop, the clamping voltage of the negative surge can be effectively reduced, thereby facilitating the device selection of the shutdown circuit and avoiding device damage caused by the negative surge.
  • the present invention can be implemented by means of software plus necessary general hardware, and of course, by hardware, but in many cases, the former is a better implementation. .
  • the technical solution of the present invention which is essential or contributes to the prior art, may be embodied in the form of a software product stored in a readable storage medium, such as a floppy disk of a computer.
  • a hard disk or optical disk or the like includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the methods described in various embodiments of the present invention.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Emergency Protection Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Protection Of Static Devices (AREA)

Abstract

一种浪涌保护电路，包括：用于提供直流电源的输入端、用于连接后级电路（13）的输出端、与输出端相连的关断电路（11）以及连接于输入端和关断电路之间的泄放电路（12）；该泄放电路包括：一个二极管（D）和一个场效应管（Q），二极管的阴极连接于输入端的正极，二极管的阳极连接于场效应管的源极，场效应管的栅极连接于输入端的正极，场效应管的漏极连接于输入端的负极，场效应管的寄生二极管与二极管的方向相反。该浪涌保护电路可以降低负向浪涌的钳位电压，从而方便器件选型，避免负向浪涌导致器件损坏。

Description

浪涌保护电路
技术领域
本发明涉及电力电子领域， 尤其涉及一种浪涌保护电路。
背景技术
目前， 在直流电源输入或相关电力系统中， 为了防止负向浪涌导致后 级电路和设备的损坏，通常会在直流输入端与后级电路之间设置浪涌保护 电路， 在发生负向浪涌时及时关断后级电路的电源供给， 通过压敏电阻
(VR)或瞬态电压抑制器（TVS )将浪涌电流泄放， 实现对后级电路的浪涌 保护。
具体的， 如图 1 ( a ) 所示， 浪涌保护电路包括关断电路和泄放电路。 其中关断电路具体为：在直流输入端的正极和负极分别设置有一个二极管 D1和 D2 , 其中 D1的阳极与直流输入的正极相连， D2的阴极与直流输入 的负极相连， 在二极管 D1和 D2与后级电路之间还设置有一个电容 C , 电容 C的两端分别连接 D1的阴极和 D2的阳极。 当然， 如图 1 ( b )所示， 关断电路的二级管 D1和 D2也可以替换为场效应管 Ml和 M2。 其中， 泄 放电路为连接于直流输入的正极与负极之间的 VR或 TVS。
现有浪涌保护电路的工作原理为： 在正常工作时， 关断电路的二极管 (或场效应管）都是处于正向导通状态， 电流从直流输入的正极流经后级 电路流向直流输入的负极。 当发生负向浪涌时， 电流出现短暂的从负极流 向正极， 此时 D1和 D2 (或 Ml和 M2 ) 是反向截止的， 实现关断功能， 保护后级电路。 VR可以根据电压调节电阻， 泄放浪涌电流； TVS可以将 浪涌电流转换为热量耗散， 起到泄放作用。
但是， 以图 1(a)为例， 二极管 D1和 D2关断后会承受很高的反向电 压 （反向电压等于压敏电阻钳位电压与电容 C 的电压之和）。 例如对于 38.4 ~ 72V 直流输入， 由于压敏电阻钳位电压高达 130V 左右， 导致 D1 和 D2承受的反向电压通常在 170V 以上。 因此关断电路的二极管或场效 应管只能选择规格较高的型号， 较高的钳位电压严重限制电子器件的选 型， 并且由于钳位电压较高容易造成负向浪涌时二极管 D1 和 D2 (或场 效应管 Ml和 M2 ) 失效、 损坏的问题。
发明内容
本发明的实施例提供一种浪涌保护电路，可以降低负向浪涌的钳位电 压， 从而方便器件选型， 避免负向浪涌导致器件损坏。
为解决上述技术问题， 本发明的实施例采用如下技术方案：
一种浪涌保护电路， 包括： 用于提供直流电源的输入端、 用于连接后 级电路的输出端以及与所述输出端相连的关断电路，所述浪涌保护电路还 包括： 连接于所述输入端和所述关断电路之间的泄放电路；
所述泄放电路包括： 一个二极管和一个场效应管；
所述二极管的阴极连接于所述输入端的正极，所述二极管的阳极连接 于所述场效应管的源极； 所述场效应管的栅极连接于所述输入端的正极， 所述场效应管的漏极连接于所述输入端的负极，所述场效应管的寄生二极 管与所述二极管的方向相反。
本发明实施例提供的浪涌保护电路，通过一个二极管和一个场效应管 泄放浪涌电流的技术相比， 由于二极管和场效应管的导通压降很低， 能够 有效压低负向浪涌的钳位电压， 从而方便关断电路的器件选型， 避免负向 浪涌导致器件损坏。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对 实施例或现有技术描述中所需要使用的附图作筒单地介绍， 显而易见地， 下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员 来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附 图。
图 1为现有技术中一种浪涌保护电路示意图；
图 2为本发明实施例中一种浪涌保护电路的示意图；
图 3为本发明实施例中另一种浪涌保护电路的示意图；
图 4为本发明实施例中另一种浪涌保护电路的示意图；
图 5为本发明实施例中另一种浪涌保护电路的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进 行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例， 而不是全部的实施例。 基于本发明中的实施例， 本领域普通技术人员在没 有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的 范围。
本发明实施例提供了一种浪涌保护电路， 如图 2所示， 包括： 用于提 供直流电源的输入端、 用于连接后级电路 13的输出端、 与所述输出端相 连的关断电路 11 , 以及连接于所述输入端和所述关断电路之间的泄放电 路 12。
其中， 所述泄放电路 12包括： 一个二极管 D和一个场效应管 Q。 所述二极管 D的阴极连接于所述输入端的正极， 所述二极管 D的阳 极连接于所述场效应管 Q的源极； 所述场效应管 Q的栅极连接于所述输 入端的正极， 所述场效应管 Q 的漏极连接于所述输入端的负极， 所述场 效应管 Q的寄生二极管与所述二极管 D的方向相反。
其中， 浪涌保护电路的输入端包括输入端正极和输入端负极两侧， 是 后级电路 13的电源来源， 例如输入端正极与电源正极相连， 输入端负极 与电源负极相连。对应的，浪涌保护电路的输出端也包括正极和负极两侧， 用于连接后级电路 13 , 为后级电路 13提供电源。
其中， 在泄放电路 12与后级电路 13之间设置有关断电路 11 , 所述 关断电路 11的具体组成可以参考现有技术。 例如， 在泄放电路 12与后级 电路 13之间， 在直流输入端的正极和负极分别设置有一个二极管 D1 和 D2 , 其中 D1 的阳极与直流输入的正极相连， D1 的阴极与输出端正极相 连， D2的阳极与输出端负极相连， D2的阴极与直流输入的负极相连。 在 二极管 D1和 D2与后级电路之间还可以设置有一个电容 C, 电容 C的两 端分别连接 D1的阴极和 D2的阳极。 当然， 上述关断电路 13中的二级管 D1和 D2也可以替换为场效应管 Ml和 M2 , 场效应管 Ml和 M2的寄生 二极管的连接方向与 D1和 D2的连接方向相同。 具体的，泄放电路 12中的场效应管 Q可以为 N型金属氧化物半导体 ( N-Metal-Oxide-Semiconductor, NMOS ), 场效应管 Q 的寄生二极管的 连接方向与二极管 D的连接方向相反。在初始状态下场效应管 Q未充电， 场效应管 Q 可以起到防反接的作用， 若发生输入端正负极反接的状况， 场效应管 Q 的寄生二极管将处于截止状态， 不会有电流流过防止输入端 电源反接导致较大的反向电流流入泄放电路 12 , 损坏泄放电路 12中的电 子器件。
当正常工作时， 关断电路 11 中的二极管正向导通， 关断电路 11处于 开启状态， 可以为后级电路 13正常提供电源。 场效应管 Q的寄生二极管 反向截止， 泄放电路 12中没有电流。 加在场效应管 Q的栅极和漏极之间 的正向电压使得场效应管 Q的栅极和源极之间形成电势，完成场效应管 Q 的充电。 当发生负向浪涌时， 浪涌保护电路中出现瞬间的反向电压， 关断 电路 11 中的二极管 D1和 D2反向截止， 关断电路 11 实现关断功能， 防 止负向浪涌电流进入后级电路 13。 此时， 由于场效应管 Q已被充电， 发 生反向浪涌时可以释放之前已存储的电势， 场效应管 Q 形成导通状态， 使得负向浪涌电流由场效应管 Q 的漏极流入， 并由源极流出， 并流经二 极管 D完成负向浪涌的泄放。
在本实施例中， 场效应管 Q可以尽量采用大电流低电压场的效应管， 从而既能提供较大的泄放电流， 迅速有效的为负向浪涌提供泄放路径， 又 能保证较低的压降， 将负向浪涌时的电压钳位到很低。
进一步的可选的， 如图 3所示， 该浪涌保护电路的泄放电路 12还包 括： 一个电阻 R。 所述电阻 R连接于所述场效应管 Q的栅极与所述输入 端的正极之间。 其中， 为了防止场效应管 Q的栅极和漏极之间的电压发生剧烈振荡， 可以在场效应管 Q 的栅极与输入端正极之间添加一个电阻 R, 在浪涌或 电压不稳定时分担部分电压， 减小场效应管 Q承受的电压， 起到保护场 效应管 Q的作用。
进一步的可选的， 如图 4所示， 该浪涌保护电路的泄放电路 12还包 括： 一个稳压管 Zl。 所述稳压管 Zl , 连接于所述场效应管 Q的源极和栅 极之间。
其中， 在场效应管 Q的栅极和漏极之间添加一个稳压管 Z1 , 该稳压 管 Z1的阳极与场效应管 Q的源极相连， 稳压管 Z1的阴极与场效应管 Q 的栅极相连， 将场效应管 Q的栅极和漏极之间的电压钳位到 Z1的工作电 压。 由于稳压管 Z1可以将场效应管 Q的栅极和漏极之间的电压钳位到一 个较低的电压值， 例如栅极和漏极之间的电压 e=60v, 因此输入端接入的 电压值就可以有更大的调整空间， 例如输入端正负极之间的电压 E 可以 增加到 220v。
进一步的可选的， 如图 5所示， 该浪涌保护电路的泄放电路 12还包 括： 一个电容 Cl。 所述电容 C1 , 与所述稳压管 Z1并联， 连接于所述场 效应管 Q的源极和栅极之间。
其中， 在场效应管 Q的源极和栅极之间连接一个电容 C1 , 可以暂时 存储场效应管 Q释放的在正常工作时所存储的电势， 减緩场效应管 Q栅 源极之间电势的流失， 可以维持场效应管 Q 的导通状态， 延长泄放电路 12 7 受负向浪涌的时间， 从而充分泄放负向浪涌， 保护后级电路 13。
综上， 通过二极管和场效应管的巧妙连接， 在负向浪涌时， 关断电路 承受的电压 （钳位电压） 为场效应管 Q的导通压降与二极管 D的正向导 通压降之和， 例如在 220v输入电压的前提下， 若发生负向浪涌场效应管 Q的导通压降约 60v左右， 而二极管 D的正向导通压降仅为 O. lv , 因此 钳位电压可以被控制到 60. lv左右的低压状态。 从而既为负向浪涌提供了 可靠的泄放路径， 又能在负向浪涌时将钳位到很低， 降低关断电路中二极 管、 场效应管的电压规格， 降低浪涌保护电路的成本。
本发明实施例提供的浪涌保护电路，通过一个二极管和一个场效应管 实现负向浪涌电流的泄放，与现有技术中通过压敏电阻或瞬态电压抑制器 泄放浪涌电流的技术相比， 由于二极管和场效应管的导通压降很低， 能够 有效压低负向浪涌的钳位电压， 从而方便关断电路的器件选型， 避免负向 浪涌导致器件损坏。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到 本发明可借助软件加必需的通用硬件的方式来实现， 当然也可以通过硬 件， 但很多情况下前者是更佳的实施方式。 基于这样的理解， 本发明的技 术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式 体现出来， 该计算机软件产品存储在可读取的存储介质中， 如计算机的软 盘， 硬盘或光盘等， 包括若干指令用以使得一台计算机设备（可以是个人 计算机， 服务器， 或者网络设备等） 执行本发明各个实施例所述的方法。 以上所述，仅为本发明的具体实施方式， 但本发明的保护范围并不局限于 此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可轻易 想到变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明的保 护范围应以所述权利要求的保护范围为准。

Claims

权 利 要 求 书
1、 一种浪涌保护电路， 包括： 用于提供直流电源的输入端、 用于连接 后级电路的输出端以及与所述输出端相连的关断电路， 其特征在于， 所述 浪涌保护电路还包括：连接于所述输入端和所述关断电路之间的泄放电路； 所述泄放电路包括： 一个二极管和一个场效应管；
所述二极管的阴极连接于所述输入端的正极， 所述二极管的阳极连接 于所述场效应管的源极； 所述场效应管的栅极连接于所述输入端的正极， 所述场效应管的漏极连接于所述输入端的负极， 所述场效应管的寄生二极 管与所述二极管的方向相反。
2、 根据权利要求 1所述的浪涌保护电路， 其特征在于， 所述泄放电路 还包括： 一个电阻， 连接于所述场效应管的栅极与所述输入端的正极之间。
3、 根据权利要求 2所述的浪涌保护电路， 其特征在于， 所述泄放电路 还包括： 一个稳压管， 连接于所述场效应管的源极和栅极之间。
4、 根据权利要求 3所述的浪涌保护电路， 其特征在于， 所述泄放电路 还包括： 一个电容， 与所述稳压管并联， 连接于所述场效应管的源极和栅 极之间。
PCT/CN2013/070318 2012-01-20 2013-01-10 浪涌保护电路 WO2013107320A1 (zh)

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