WO2013102416A1 - 像素单元驱动电路、像素单元和显示装置 - Google Patents

像素单元驱动电路、像素单元和显示装置 Download PDF

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Publication number
WO2013102416A1
WO2013102416A1 PCT/CN2012/087715 CN2012087715W WO2013102416A1 WO 2013102416 A1 WO2013102416 A1 WO 2013102416A1 CN 2012087715 W CN2012087715 W CN 2012087715W WO 2013102416 A1 WO2013102416 A1 WO 2013102416A1
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WIPO (PCT)
Prior art keywords
transistor
capacitor
source
pixel unit
driving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2012/087715
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English (en)
French (fr)
Inventor
谭文
祁小敬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US13/996,138 priority Critical patent/US9019178B2/en
Publication of WO2013102416A1 publication Critical patent/WO2013102416A1/zh
Anticipated expiration legal-status Critical
Priority to US14/674,581 priority patent/US9311854B2/en
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/60—Circuit arrangements for operating LEDs comprising organic material, e.g. for operating organic light-emitting diodes [OLED] or polymer light-emitting diodes [PLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes

Definitions

  • Pixel unit drive circuit circuit, pixel unit and display device
  • the present invention relates to the technical field of organic electroluminescent devices, and in particular to a pixel unit driving circuit, a pixel unit, and a display device. Background technique
  • An electroluminescent display device such as an Organic Light-Emitting Diode (OLED) display is different from a conventional liquid crystal display.
  • the OLED display does not require a backlight, so the OLED display device can be made lighter and thinner.
  • OLED display technology is becoming more and more popular.
  • the OLED display includes a driving circuit, an OLED light emitting device, and the like, and outputs a current to the light emitting device through the driving circuit to drive the light emitting device to emit light of different brightness.
  • 1 is a pixel structure in an OLED display of the prior art. As shown in FIG. 1 , the OLED pixel in the prior art includes a first signal line CN1, a second signal line CN2, a driving circuit, and an OLED light emitting device, wherein the driving circuit includes a capacitor Cst, a driving transistor T1, and a second transistor ⁇ 2.
  • the three transistors ⁇ 3 and the fourth transistor ⁇ 4, the capacitor Cst is connected in series between the gate and the source of the driving transistor T1, and the third transistor T3 and the fourth transistor T4 are connected in series between the gate and the drain of the driving transistor T1, and the driving transistor T1 is driven.
  • the drain is connected to the source of the second transistor T2.
  • the first signal line CN1 is connected to the gate of the third transistor T3 and the gate of the fourth transistor T4, respectively, and the second signal line CN2 is connected to the gate T2 of the second transistor.
  • the driving circuit receives the externally input data current l data , the data current I data will be stored in the capacitor Cst, and the capacitor Cst generates a driving current I that drives the OLED to emit light.
  • the data current I data in the prior art is equal to the drive current I. Ied.
  • the led is relatively small, so the data current I data is also relatively small.
  • the capacitance Cst is large, the smaller data current I data takes a longer time to charge the capacitor Cst. In the case of the low data current I data , the capacitor Cst Charging time can be long, causing the OLED display to refresh slowly.
  • the present invention provides a pixel unit driving circuit, a pixel unit, and a display device for solving the problem that the pixel unit refresh rate is slow in the prior art.
  • the present invention provides a pixel unit driving circuit, which includes: a switching unit, the first end of which is connected to the high voltage signal end, the second end is connected to the light emitting device, the third end is connected to the first control line, and the fourth end is connected to the second control line;
  • a driving transistor having a drain connected to the switching unit and a source connected to the low voltage signal terminal; a capacitor storage unit having a first end connected to a gate of the driving transistor, a second end and a source of the driving transistor The pole is connected, and the third end is connected to the second control line.
  • the capacitor storage unit includes: a first capacitor, a second capacitor, and a fifth transistor;
  • One end of the first capacitor is connected to the gate of the driving transistor, and the other end is connected to the source of the driving transistor;
  • One end of the second capacitor is connected to a gate of the driving transistor, and the other end is connected to a drain of the fifth transistor;
  • a gate of the fifth transistor is coupled to the second control line, and a source is coupled to a source of the drive transistor.
  • the capacitor storage unit includes: a first capacitor, a second capacitor, and a fifth transistor;
  • One end of the first capacitor is connected to the gate of the driving transistor, and the other end is connected to one end of the second capacitor;
  • the other end of the second capacitor is connected to a source of the driving transistor
  • the drain of the fifth transistor is connected between the first capacitor and the second capacitor, the gate is connected to the second control line, and the source is connected to the source of the driving transistor.
  • the switching unit includes: a second transistor and a fourth transistor;
  • the drain of the second transistor is connected to the high voltage signal end, the gate is connected to the second control line, and the source is connected to the drain of the driving transistor;
  • the source of the fourth transistor is connected to the gate of the driving transistor, the gate is connected to the first control line, and the drain is connected to the high voltage signal terminal.
  • the switch unit further includes:
  • the third transistor has a source connected to the drain of the driving transistor, a drain connected to the high voltage signal terminal, and a gate connected to the first control line.
  • the driving transistor, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are n-type thin film transistors.
  • the present invention provides a pixel unit, which includes an OLED and any of the above pixel unit driving The circuit, the pixel unit driving circuit is connected to a cathode of the OLED, and an anode of the OLED is connected to a high voltage signal end.
  • the present invention provides a display device including the above pixel unit.
  • the invention has the following beneficial effects:
  • the pixel unit driving circuit controls the driving current I through the switching unit.
  • the change in led becomes a change in the opposite trend, ensuring that regardless of the drive current: [.
  • the size of the led the data current I data can quickly charge the capacitor storage unit quickly.
  • the pixel unit and the display device provided by the present invention control the driving current I through the switching unit.
  • the change in led becomes a change in the opposite trend, ensuring that regardless of the drive current: [. Led size, data current I data can quickly charge the first capacitor quickly, improve the refresh rate of the pixel unit, help to achieve high-resolution display image, while reducing the power consumption of the power supply when displaying high-brightness images, but also
  • the drive current I is controlled by controlling the value of the externally input data current 1 ⁇ . Led , thereby controlling the display brightness of the light emitting device.
  • the source and drain are not strictly separated, and the source and drain are interchangeable.
  • FIG. 2 is a schematic structural view of a first embodiment of a pixel unit driving circuit of the present invention
  • FIG. 3 is a schematic structural view of a second embodiment of a pixel unit driving circuit of the present invention.
  • FIG. 4 is a timing signal diagram of the pixel unit driving circuit shown in FIG. 3;
  • FIG. 5 is an equivalent circuit diagram of the prime unit driving circuit shown in FIG. 3 in the first timing stage
  • FIG. 6 is an equivalent circuit diagram of the prime unit driving circuit shown in FIG. 3 in the second timing stage
  • FIG. 7 is a pixel unit driving of the present invention
  • FIG. 8 is an equivalent circuit diagram of the prime unit driving circuit of FIG. 7 at a second timing stage.
  • the pixel unit driving circuit of the embodiment includes a switching unit 201, a capacitor storage unit 202, and a driving transistor T1.
  • the first end of the switching unit 201 is connected to the high voltage signal end, and the second end of the switching unit 201 is connected.
  • the third end of the switch unit 201 is connected to the first control line CN1, and the fourth end of the switch unit 201 is connected to the second control line CN2.
  • the first end of the capacitor storage unit 202 and the gate of the driving transistor T1 are connected. Connected, the second end of the capacitor storage unit 202 is connected to the source of the driving transistor T1, the third end of the capacitor storage unit 202 is connected to the second control line CN2; the source of the driving transistor T1 is connected to the switching unit 201, and the driving transistor T1 is connected. The source is connected to the low voltage signal terminal Vss.
  • the first control line CN1 outputs a high level control signal to the switching unit 201, the switching unit 201 is turned on, and outputs a low level signal to the switching unit 201 and the capacitor storage unit 202 through the second control line CN2, respectively, and the high potential Vdd output of the power supply
  • the signal outputs a high level signal to the switching unit 201 and the capacitor storage unit 202 through the second control line CN2, respectively, and the voltage of the capacitor storage unit 202 is lowered, and the
  • the voltage of the capacitor storage unit 202 is equal to the voltage V s between the gate and the source of the driving transistor T1, and the driving current I of the power source to the OLED.
  • Led is equal to the drain and source currents flowing through the drive transistor 1 ⁇ 1, so the data current Idata is less than the drive current I.
  • Led and the magnitude of the data current I data varies less than the drive current I.
  • the range of change of led is in the current scaling ratio I data /I. i ed with I. The changes led simultaneously from opposite trend change, regardless of the drive current I.
  • the size of the led the data current I data is not too small, to ensure that the data current I data can quickly charge the capacitor storage unit quickly.
  • the capacitor storage unit in the pixel unit driving circuit of the embodiment includes a first capacitor Cstl, a second capacitor Cst2, and a fifth transistor T5; wherein, one end of the first capacitor Cstl is connected to the gate of the driving transistor T1.
  • the other end of the first capacitor Cstl is connected to the source of the driving transistor T1, one end of the second capacitor Cst2 is connected to the gate of the driving transistor T1, and the other end of the second capacitor Cst2 is connected to the drain of the fifth transistor T5.
  • the gate of the five transistor T5 is connected to the second control line CN2, the source of the fifth transistor T5 is connected to the source of the driving transistor T1, and the switching unit includes the second transistor T2 and the fourth The transistor T4, the drain of the second transistor T2 is connected to the high voltage signal terminal Vdd, the gate of the second transistor T2 is connected to the second control line CN2, and the source of the second transistor T2 is connected to the drain of the driving transistor T1.
  • the drain of the four transistor T4 is connected to the gate of the driving transistor T1, the gate of the fourth transistor T4 is connected to the first control line CN1, and the drain of the fourth transistor T4 is connected to the high voltage signal terminal Vdd.
  • the switching unit in the pixel unit driving circuit of the embodiment further includes: a third transistor T3, a source of the third transistor T3 is connected to a drain of the driving transistor T1, and a drain and a high voltage signal end of the third transistor T3 Vdd is connected, the gate of the third transistor T3 is connected to the first control line CN1, and when the fourth transistor T4 is broken, the first control line CN1 can still control the switching unit 201 through the third transistor T3, and is enhanced.
  • the stability of the switch unit is provided.
  • FIG. 4 is a timing signal diagram of the pixel unit driving circuit shown in FIG. 3
  • FIG. 5 is an equivalent circuit diagram of the pixel unit driving circuit shown in FIG. 3 in the first timing stage
  • FIG. 6 is a pixel unit driving circuit shown in FIG.
  • a high level control signal, a third transistor T3 and a fourth transistor are respectively output to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the first control line CN1.
  • T4 is turned on; a low level control signal is output to the gate of the second transistor T2 and the gate T5 of the fifth transistor through the second control line, and the second transistor and the fifth transistor are turned off.
  • the equivalent circuit of the driving circuit is as shown in FIG. 5.
  • the high potential Vdd of the power supply outputs the data current I data
  • the data current I data is stored in the first capacitor Cstl
  • the driving transistor T1 is in a saturated state.
  • the current between the drain and the source of the driving transistor T1 is I dsl
  • I data I ds i
  • the amount of electricity stored in the first capacitor Cstl is Q, and the voltage of the first capacitor Cstl is equal to the voltage Vgs between the gate and the source of the transistor T1, according to the formula:
  • a low-level control signal is output to the gate of the third transistor T3 and the gate of the fourth transistor T4 through the first control line CN1, respectively, so that the third transistor T3 And the fourth transistor T4 is turned off; a high level control signal is output to the gate of the second transistor T2 and the gate T5 of the fifth transistor through the second control line, respectively, to turn on the second transistor and the fifth transistor.
  • the power source will output a current I to the OLED. Led , the drive current I of the power supply to the OLED.
  • Led is equal to the drain and source current flowing through the driving transistor T1; when the fifth transistor T5 is turned on, the first capacitor Cstl and the second capacitor Cst2 are connected in parallel, and the parallel circuit is connected to the gate and the source of the driving transistor T1 At this time, the amount of electricity Q stored in the first capacitor Cstl will be distributed between the first capacitor Cstl and the second capacitor Cst2, so that the voltages on the first capacitor Cstl and the second capacitor Cst2 are equal, the first capacitor Cstl and The voltage on the second capacitor Cst2 is equal to the voltage gs between the gate and the source of the driving transistor T1, wherein the voltage between the gate and the source of the driving transistor T1 is as shown in the formula (5):
  • V' _ 0_ (5)
  • Equation (8) is as follows:
  • the current scaling between led is shown by Ida ta /I led (9):
  • the current scaling ratio I data /I. i ed with I becomes a change in the opposite trend, when a larger drive current I is required.
  • the current scaling is relatively small, thus reducing the power consumption of the power supply when displaying high-brightness images, and having a larger data current I data to quickly charge the first capacitor Cstl; when a smaller driving current Ioled is required.
  • the current scaling is relatively large, a relatively large data current I data can be maintained to charge the first capacitor Cstl, thereby ensuring that the data current I data quickly charges the first capacitor Cstl and improves the refresh rate of the pixel unit. Helps achieve high resolution display images.
  • the drive current I is controlled by controlling the value of the externally input data current I data . Led , so that the display brightness of the light-emitting device can be precisely controlled.
  • FIG. 7 is a schematic structural view of a third embodiment of a pixel unit driving circuit of the present invention.
  • the storage unit includes a first capacitor Cstl, a second capacitor Cst2, and a fifth transistor T5
  • the switch unit includes a second transistor T2 and a fourth transistor T4; wherein, one end of the first capacitor Cstl Connected to the gate of the driving transistor T1, the other end of the first capacitor Cstl is connected to one end of the second capacitor Cst2, the other end of the second capacitor Cst2 is connected to the source of the driving transistor T1; the drain of the fifth transistor T5 is connected Between the first capacitor Cstl and the second capacitor Cst2, the gate of the fifth transistor T5 is connected to the second control line CN2, the source of the fifth transistor T5 is connected to the source of the driving transistor T1; the source of the second transistor T2 Connected to the high voltage signal terminal Vdd, the gate of the second transistor T2 is connected to the second control
  • the switching unit further includes a third transistor T3, the source of the third transistor T3 is connected to the drain of the driving transistor T1, and the drain of the third transistor T3 is connected to the high voltage signal terminal Vdd. Connected, the gate of the third transistor T3 is connected to the first control line CN1 Pick up.
  • the functions of the source and the drain of the second transistor T2, the third transistor ⁇ 3, and the fourth transistor ⁇ 4 are the same, so that the source and the drain of the transistor can be exchange-connected to the driving circuit.
  • the effect is the same.
  • the driving transistor T1, the second transistor ⁇ 2, the third transistor ⁇ 3, the fourth transistor ⁇ 4, and the fifth transistor ⁇ 5 are n-type thin film transistors.
  • FIG. 8 is an equivalent circuit diagram of the pixel unit driving circuit shown in FIG. 7 in the second timing stage shown in FIG.
  • the equivalent circuit of the pixel unit driving circuit in the first timing phase is as shown in FIG. 5.
  • the equivalent circuit of the pixel unit driving circuit in the second timing phase is as shown in FIG. 8. As shown in FIG.
  • the first capacitor Cstl and the second capacitor Cst2 are connected in series, and the first capacitor Cstl is charged at the first capacitor Cstl and
  • the second capacitor Cst2 is distributed to equalize the voltages on the first capacitor Cstl and the second capacitor Cst2, and the voltages on the first capacitor Cstl and the second capacitor Cst2 are equal to the voltage gs between the gate and the source of the driving transistor T1.
  • the voltage between the gate and the source of the driving transistor T1 is as shown in the formula (5). Therefore, in the second embodiment of the pixel unit driving circuit of the present invention, the data current I data and the driving current I.
  • the electrical parameters such as led and current scaling ratio Idata/Ided are the same as those of the equations (1)-(10) in the first embodiment of the pixel unit driving circuit, and are not described herein again.
  • the driving current I is controlled by the switching unit.
  • the change in led becomes a change in the opposite trend, ensuring that regardless of the drive current: [. Led size, data current I data can quickly charge the first capacitor quickly, improve the refresh rate of the pixel unit drive circuit, help to achieve high-resolution display image, while reducing the power consumption of the power supply when displaying high-brightness images, and It is also possible to control the drive current I by controlling the value of the externally input data current I data . Led , thereby controlling the display brightness of the light emitting device.
  • the present invention also provides a pixel unit comprising an OLED light emitting device and any one of the pixel unit driving circuits described above, wherein the pixel unit driving circuit is connected to a cathode of the OLED, and an anode of the OLED is connected to the high voltage signal terminal Vdd.
  • the present invention also provides a display device comprising the pixel unit in the above embodiment. It is to be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the invention, but the invention is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and scope of the invention. These modifications and improvements are also considered to be within the scope of the invention.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素单元驱动电路、像素单元和显示装置，其中所述的像素单元驱动电路包括：开关单元（201），其第一端与高电压信号端（Vdd）连接，第二端与发光器件(OLED）连接，第三端与第一控制线（CN1）连接，第四端与第二控制线（CN2）连接；驱动晶体管（T1），其漏极与所述开关单元（201）连接，源极与低电压信号端(Vss）连接；电容存储单元（202），其第一端与所述驱动晶体管（T1）的栅极连接，第二端与所述驱动晶体管（T1）的源极连接，第三端与第二控制线（CN2）连接。通过开关单元（201）控制驱动电流Ioled和数据电流Idata的大小及其通断，以使电流缩放比Idata/Ioled随着Ioled的变化而成相反趋势的变化，确保无论驱动电流Ioled大小，数据电流Idata都能够快速对电容存储单元快速充电。

Description

像素单元驱动电路、 像素单元和显示装置 技术领域
本发明涉及有机电致发光装置的技术领域， 具体地， 涉及一种像素单元 驱动电路、 像素单元和显示装置。 背景技术
有机发光二极管 (Organic Light-Emitting Diode , OLED)显示器等电致发 光显示装置与传统的液晶显示器的显示方式不同， OLED显示器不需背光源， 因此 OLED显示装置可以做得更轻、 更薄， 可视角度更大， 并且能够显著节 省电能， 所以， OLED显示技术越来越多普及。
OLED显示器包括驱动电路和 OLED发光器件等， 通过驱动电路向发光 器件输出电流以驱动发光器件发出不同亮度的光。 图 1为现有技术中 OLED 显示器中的像素结构。 如图 1所示， 现有技术中 OLED像素包括第一信号线 CN1、 第二信号线 CN2、 驱动电路和 OLED发光器件， 其中， 驱动电路包括 电容 Cst、驱动晶体管 Tl、第二晶体管 Τ2、第三晶体管 Τ3和第四晶体管 Τ4, 驱动晶体管 T1的栅极和源极之间串联电容 Cst, 驱动晶体管 T1的栅极和漏 极之间串联第三晶体管 T3和第四晶体管 T4,驱动晶体管 T1的漏极与第二晶 体管 T2的源极连接，第一信号线 CN1分别连接第三晶体管 T3的栅极和第四 晶体管 T4的栅极， 第二信号线 CN2连接第二晶体管的栅极 T2。 驱动电路接 收外部输入的数据电流 ldata, 数据电流 Idata将存储在电容 Cst中， 电容 Cst产 生驱动 OLED发光的驱动电流 I。led,现有技术中的数据电流 Idata等于驱动电流 I。ied。 由于 OLED发光时所需要的驱动电流 I。led比较小， 因此数据电流 Idata也 比较小， 当电容 Cst较大时， 较小的数据电流 Idata需较长的时间对电容 Cst 充电， 在低数据电流 Idata的情况下， 对电容 Cst充电时间会很长， 导致 OLED 显示器的刷新速度慢。 发明内容
为解决上述问题， 本发明提供一种像素单元驱动电路、 像素单元和显示 装置， 用于解决现有技术中像素单元刷新速度慢的问题。
为此， 本发明提供一种像素单元驱动电路， 其中， 包括： 开关单元， 其第一端与高电压信号端连接， 第二端与发光器件连接， 第 三端与第一控制线连接， 第四端与第二控制线连接；
驱动晶体管， 其漏极与所述开关单元连接， 源极与低电压信号端连接； 电容存储单元， 其第一端与所述驱动晶体管的栅极连接， 第二端与所述 驱动晶体管的源极连接， 第三端与第二控制线连接。
其中， 所述电容存储单元包括： 第一电容、 第二电容和第五晶体管； 其 中
所述第一电容一端与所述驱动晶体管的栅极连接， 另一端与所述驱动晶 体管的源极连接；
所述第二电容的一端与所述驱动晶体管的栅极连接， 另一端与所述第五 晶体管的漏极连接；
所述第五晶体管的栅极与所述第二控制线连接， 源极与所述驱动晶体管 的源极连接。
其中， 所述电容存储单元包括： 第一电容、 第二电容和第五晶体管； 其 中
所述第一电容一端与所述驱动晶体管的栅极连接， 另一端与所述第二电 容的一端连接；
所述第二电容的另一端与所述驱动晶体管的源极连接；
所述第五晶体管的漏极连接在所述第一电容和第二电容之间， 栅极与第 二控制线连接， 源极与所述驱动晶体管的源极连接。
其中， 所述开关单元包括： 第二晶体管、 第四晶体管；
所述第二晶体管的漏极与高电压信号端连接， 栅极与第二控制线连接， 源极与所述驱动晶体管的漏极连接；
所述第四晶体管的源极与所述驱动晶体管的栅极连接， 栅极与第一控制 线连接， 漏极与高电压信号端连接。
其中， 所述开关单元还包括：
第三晶体管， 其源极与所述驱动晶体管漏极连接， 漏极与高电压信号端 连接， 栅极与第一控制线连接。
其中， 所述驱动晶体管、 第二晶体管、 第三晶体管、 第四晶体管、 第五 晶体管为 n型薄膜晶体管。
本发明提供一种像素单元， 其中， 包括 OLED和上述任一像素单元驱动 电路， 所述像素单元驱动电路与所述 OLED的阴极连接 , 所述 OLED的阳极 与高电压信号端连接。
本发明提供一种显示装置， 其中， 包括上述的像素单元。 本发明具有下述有益效果：
本发明提供的像素单元驱动电路， 通过开关单元控制驱动电流 I。ied和数 据电流 Idata的大小以及其通断， 以使电流缩放比 Idata/I。led随着 I。led的变化而成 相反趋势的变化，确保无论驱动电流: [。led大小，数据电流 Idata都能够快速对电 容存储单元快速充电。
本发明提供的像素单元和显示装置， 通过开关单元控制驱动电流 I。led和 数据电流 Idata的大小以及其通断， 以使电流缩放比 Idata/I。ied随着 I。led的变化而 成相反趋势的变化，确保无论驱动电流: [。led大小，数据电流 Idata都能够快速对 第一电容快速充电， 提高像素单元的刷新速度， 有助于实现高分辨率显示图 像， 同时降低电源在显示高亮度图像时的功耗， 而且还可以通过控制外部输 入的数据电流 1^的数值来控制驱动电流 I。led,从而控制发光器件的显示亮度。
由于晶体管源极和漏极结构对称的特性， 本发明中有些情况下不严格区 分源极和漏极， 源极和漏极可以互换。 附图说明
图 1为现有技术中 OLED显示器中的像素结构；
图 2为本发明像素单元驱动电路第一实施例的结构示意图；
图 3为本发明像素单元驱动电路第二实施例的结构示意图；
图 4为图 3所示像素单元驱动电路的时序信号图；
图 5为图 3所示素单元驱动电路在第一时序阶段的等效电路图； 图 6为图 3所示素单元驱动电路在第二时序阶段的等效电路图； 图 7为本发明像素单元驱动电路第三实施例的结构示意图； 以及 图 8为图 7所示素单元驱动电路在第二时序阶段的等效电路图。 具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案， 下面结合附图对 本发明提供的像素单元驱动电路、 像素单元和显示装置进行详细描述。 图 2为本发明像素单元驱动电路第一实施例的结构示意图。如图 2所示， 本实施例像素单元驱动电路包括开关单元 201、 电容存储单元 202和驱动晶 体管 T1 , 其中， 开关单元 201的第一端与高电压信号端连接， 开关单元 201 的第二端与发光器件连接， 开关单元 201的第三端与第一控制线 CN1连接， 开关单元 201的第四端与第二控制线 CN2连接； 电容存储单元 202的第一端 与驱动晶体管 T1的栅极连接， 电容存储单元 202的第二端与驱动晶体管 T1 的源极连接， 电容存储单元 202的第三端与第二控制线 CN2连接； 驱动晶体 管 T1的源极与开关单元 201连接，驱动晶体管 T1的源极与低电压信号端 Vss 连接。
第一控制线 CN1向开关单元 201输出高电平控制信号， 开关单元 201导 通， 通过第二控制线 CN2分别向开关单元 201和电容存储单元 202输出低电 平信号， 电源的高电位 Vdd输出数据电流 Idata,数据电流 Idata将存储在电容存 储单元 202中，存储在电容存储单元 202中的电量为 Q; 驱动晶体管 T1的漏 极和源极之间的电流为 Ids 1 , 则 Idata =Idsi , 此时， 驱动晶体管 Τ 1栅极和源极 之间的电压 Vgs; 存储在电容存储单元 202中的电量为 Q; 通过第一控制线 CN1向开关单元 201输出低电平控制信号，通过第二控制线 CN2分别向开关 单元 201和电容存储单元 202输出高电平信号， 电容存储单元 202的电压将 降低， 电源向 OLED输出驱动电流 I。led, 此时电容存储单元 202的电压等于 驱动晶体管 T1的栅极和源极之间的电压 V s, 电源向 OLED输出的驱动电 流 I。led等于流经驱动晶体管的漏极和源极电流 1^1 , 所以， 数据电流 Idata小于 驱动电流 I。led,并且数据电流 Idata的变化幅度要小于驱动电流 I。led的变化幅度， 在电流缩放比 Idata/I。ied随着 I。led的变化而成相反趋势的变化的同时， 无论驱动 电流 I。led大小， 数据电流 Idata都不会太小， 确保数据电流 Idata都能够快速对电 容存储单元快速充电。
图 3为本发明像素单元驱动电路第二实施例的结构示意图。如图 3所示， 本实施例像素单元驱动电路中的电容存储单元包括第一电容 Cstl、 第二电容 Cst2和第五晶体管 T5; 其中， 第一电容 Cstl的一端与驱动晶体管 T1的栅极 连接， 第一电容 Cstl的另一端与驱动晶体管 T1的源极连接， 第二电容 Cst2 的一端与驱动晶体管 T1的栅极连接， 第二电容 Cst2的另一端与第五晶体管 T5的漏极连接， 第五晶体管 T5的栅极与第二控制线 CN2连接， 第五晶体管 T5的源极与驱动晶体管 T1的源极连接；开关单元包括第二晶体管 T2和第四 晶体管 T4, 第二晶体管 Τ2的漏极与高电压信号端 Vdd连接， 第二晶体管 T2 的栅极与第二控制线 CN2连接，第二晶体管 T2的源极与驱动晶体管 T1的漏 极连接， 第四晶体管 T4的漏极与驱动晶体管 T1的栅极连接， 第四晶体管 T4 的栅极与第一控制线 CN1连接， 第四晶体管 T4的漏极与高电压信号端 Vdd 连接。
进一步的， 本实施例像素单元驱动电路中的开关单元还包括： 第三晶体 管 T3 , 第三晶体管 T3的源极与驱动晶体管 T1的漏极连接， 第三晶体管 T3 的漏极与高电压信号端 Vdd连接， 第三晶体管 T3的栅极与第一控制线 CN1 连接， 当第四晶体管 T4的出现断路故障时， 第一控制线 CN1仍可通过第三 晶体管 T3实现对开关单元 201的控制， 增强了开关单元的稳定性。
图 4为图 3所示像素单元驱动电路的时序信号图， 图 5为图 3所示像素 单元驱动电路在第一时序阶段的等效电路图， 图 6为图 3所示像素单元驱动 电路在第二时序阶段的等效电路图。 如图 4所示， 在第一时序阶段， 通过第 一控制线 CN1分别向第三晶体管 T3的栅极和第四晶体管 T4的栅极输出高电 平控制信号， 第三晶体管 T3和第四晶体管 T4导通； 通过第二控制线分别向 第二晶体管 T2的栅极和第五晶体管的栅极 T5输出低电平控制信号， 第二晶 体管和第五晶体管截止。 第一时序阶段中， 驱动电路的等效电路如图 5所示， 电源的高电位 Vdd输出数据电流 Idata, 数据电流 Idata将存储在第一电容 Cstl 中， 同时， 驱动晶体管 T1处于饱和状态， 驱动晶体管 T1的漏极和源极之间 的电流为 Idsl , 则 Idata =Idsi , 此时， 驱动晶体管 Tl栅极和源极之间的电压 Vgs=Va-Vss, 其中， Va为 A处的电平， Vss为电源的低电平。
第一时序阶段结束时， 存储在第一电容 Cstl中的电量为 Q, 第一电容 Cstl的电压等于动晶体管 T1栅极和源极之间的电压 Vgs, 根据公式可得：
其中， 驱动晶体管 T1源极和漏极之间的电流 Idsl如公式 (2)所示
Ids i =\ kl(Vgs - Vth)2 (2) 由于 Idata =Idsl , 根据公式 (2)可得公式 (3) , 公式 (3)如下所示：
Adata = ids l = ^ki(vgs - vth)2 (3) 根据公式 (1)、 公式 (2) 和公式 (3)可得公式 (4), 公式 (4)如下所示： Idata = kl(Vgs - Vth)2 = -kl(-^ - Vth)2 (4) 其中， Kl为驱动晶体管的电流参数。
如图 4、 图 6所示， 在第二时序阶段， 通过第一控制线 CN1分别向第三 晶体管 T3的栅极和第四晶体管 T4的栅极输出低电平控制信号， 使第三晶体 管 T3和第四晶体管 T4截止； 通过第二控制线分别向第二晶体管 T2的栅极 和第五晶体管的栅极 T5输出高电平控制信号，使第二晶体管和第五晶体管导 通。 当第二晶体管 T2导通时， 电源将向 OLED输出电流 I。led , 电源向 OLED 输出的驱动电流 I。led等于流经驱动晶体管 T1的漏极和源极电流 ； 当第五 晶体管 T5导通时， 第一电容 Cstl和第二电容 Cst2并联， 该并联电路连接在 驱动晶体管 T1的栅极和源极之间， 此时， 存储在第一电容 Cstl中的电量 Q 将在第一电容 Cstl和第二电容 Cst2之间分配， 使第一电容 Cstl和第二电容 Cst2上的电压相等， 第一电容 Cstl和第二电容 Cst2上的电压等于驱动晶体 管 T1的栅极和源极之间的电压 gs , 其中， 驱动晶体管 T1的栅极和源极之 间的电压 如公式 (5)所示：
V' = _ 0_ (5)
gs Cstl + Cst2 )
其中， 驱动晶体管 T1源极和漏极之间的电流 如公式 (6)所示：
Figure imgf000008_0001
由于 I ied= I7dsi , 根据公式 (6)可得公式 (7), 公式 (7)如下所示：
Ioied =
Figure imgf000008_0002
根据公式 (5)、 公式 (6) 和公式 (7)可得公式 (8), 公式 (8)如下所示：
Ioied = ^ kl(Vgs - Vth)2 = ^kl(— -5- ~ - Vth)2 (8) 根据公式 (4；)和公式 8) , 对数据电流 Idata与驱动电流 I。led之间的电流缩放 比 Idata/I led (9)所示：
th
Figure imgf000008_0003
，2
Cst2 Vth kl \ _ kl .Cst2Vth.2
Cst l ' 2I Cst 2 ) ~ 2 ^ Cst l ^ V d" Cst2; vth kT
Figure imgf000009_0001
kl Cst 2-Vth \ z Λ ( ■ Cst l\
2 V Cst l ) V CCsstt 22// Vth kT
根据公式 (9)可知，电流缩放比 Idata/I。ied随着 I。ied的变化而成相反趋势的变 化， 当需要较大的驱动电流 I。led时， 电流缩放比较小， 因此降低了电源在显 示高亮度图像时的功耗， 同时有较大的数据电流 Idata来对第一电容 Cstl进行 快速充电； 当需要较小的驱动电流 Ioled时， 由于电流缩放比较大， 因此仍然 可以维持一个相对较大的数据电流 Idata来对第一电容 Cstl充电， 从而保证数 据电流 Idata对第一电容 Cstl进行快速充电， 提高像素单元的刷新速度， 有助 于实现高分辨率显示图像。
根据公式 (9)可得公式 (10), 公式 (10)如下所示：
Figure imgf000009_0002
" Wa -； (10)
根据公式 (10)得知，通过控制外部输入的数据电流 Idata的数值来控制驱动 电流 I。led , 从而可以精确控制发光器件的显示亮度。
图 7为本发明像素单元驱动电路第三实施例的结构示意图。如图 7所示， 本实施例中， 存储单元包括第一电容 Cstl、 第二电容 Cst2和第五晶体管 T5 , 开关单元包括第二晶体管 T2和第四晶体管 T4; 其中， 第一电容 Cstl的一端 与驱动晶体管 T1的栅极连接， 第一电容 Cstl的另一端与第二电容 Cst2的一 端连接， 第二电容 Cst2的另一端与驱动晶体管 T1的源极连接； 第五晶体管 T5的漏极连接在第一电容 Cstl和第二电容 Cst2之间，第五晶体管 T5的栅极 与第二控制线 CN2连接，第五晶体管 T5的源极与驱动晶体管 T1的源极连接； 第二晶体管 T2的源极与高电压信号端 Vdd连接，第二晶体管 T2的栅极与第 二控制线 CN2连接， 第二晶体管 T2的源极与驱动晶体管 T1的漏极连接， 第 四晶体管 T4的源极与驱动晶体管 T1的栅极连接， 第四晶体管 T4的栅极与 第一控制线 CN1连接， 第四晶体管 T4的漏极与高电压信号端 Vdd连接。
进一步的， 本实施例像素单元驱动电路中， 开关单元还包括第三晶体管 T3 , 第三晶体管 T3的源极与驱动晶体管 T1的漏极连接， 第三晶体管 T3的 漏极与高电压信号端 Vdd连接， 第三晶体管 T3的栅极与第一控制线 CN1连 接。
在实际应用中， 第二晶体管 T2、第三晶体管 Τ3和第四晶体管 Τ4的源极 和漏极的功能是相同的， 所以， 可以将上述晶体管的源极和漏极交换连接， 对驱动电路的作用是相同的。 驱动晶体管 Tl、 第二晶体管 Τ2、 第三晶体管 Τ3、 第四晶体管 Τ4、 第五晶体管 Τ5为 η型薄膜晶体管。
图 8为图 7所示像素单元驱动电路在图 4所示第二时序阶段的等效电路 图。 本实施例中， 当向像素单元驱动电路中施加如图 4所示的时序信号， 第 一时序阶段时像素单元驱动电路的等效电路如图 5所示。 第二时序阶段时像 素单元驱动电路的等效电路如图 8所示， 如图 8所示， 第一电容 Cstl和第二 电容 Cst2串联， 第一电容 Cstl上电量 Q将在第一电容 Cstl和第二电容 Cst2 之间分配， 使第一电容 Cstl和第二电容 Cst2上的电压相等， 第一电容 Cstl 和第二电容 Cst2上的电压等于驱动晶体管 T1的栅极和源极之间的电压 gs, 其中， 驱动晶体管 T1的栅极和源极之间的电压 如公式 (5)所示。 因此， 本 发明像素单元驱动电路第二实施例中， 数据电流 Idata、驱动电流 I。led和电流缩 放比 Idata/Ided等电学参数与像素单元驱动电路第一实施例中公式 (1)-(10)的运 算过程相同， 在此不再赘述。
上述像素单元驱动电路实施例中， 通过开关单元控制驱动电流 I。led和数 据电流 Idata的大小以及其通断， 以使电流缩放比 Idata/I。led随着 I。led的变化而成 相反趋势的变化，确保无论驱动电流: [。led大小，数据电流 Idata都能够快速对第 一电容快速充电， 提高像素单元驱动电路的刷新速度， 有助于实现高分辨率 显示图像， 同时降低电源在显示高亮度图像时的功耗， 而且还可以通过控制 外部输入的数据电流 Idata的数值来控制驱动电流 I。led,从而控制发光器件的显 示亮度。
本发明还提供一种像素单元， 包括 OLED发光器件和上述的任意一种像 素单元驱动电路，其中，所述像素单元驱动电路与 OLED的阴极连接， OLED 的阳极与高电压信号端 Vdd连接。
本发明还提供一种显示装置， 其中， 包括上述实施例中的像素单元。 可以理解的是， 以上实施方式仅仅是为了说明本发明的原理而釆用的示 例性实施方式， 然而本发明并不局限于此。 对于本领域内的普通技术人员而 言， 在不脱离本发明的精神和实质的情况下， 可以做出各种变型和改进， 这 些变型和改进也视为本发明的保护范围。

Claims

权 利 要 求 书
1、 一种像素单元驱动电路， 包括：
开关单元， 其第一端与高电压信号端连接， 第二端与发光器件连接， 第 三端与第一控制线连接， 第四端与第二控制线连接；
驱动晶体管， 其漏极与所述开关单元连接， 源极与低电压信号端连接； 电容存储单元， 其第一端与所述驱动晶体管的栅极连接， 第二端与所述 驱动晶体管的源极连接， 第三端与第二控制线连接。
2、 根据权利要求 1所述的像素单元驱动电路， 所述电容存储单元包括： 第一电容、 第二电容和第五晶体管； 其中
所述第一电容一端与所述驱动晶体管的栅极连接， 另一端与所述驱动晶 体管的源极连接；
所述第二电容的一端与所述驱动晶体管的栅极连接， 另一端与所述第五 晶体管的漏极连接；
所述第五晶体管的栅极与所述第二控制线连接， 源极与所述驱动晶体管 的源极连接。
3、 根据权利要求 1所述的像素单元驱动电路， 所述电容存储单元包括： 第一电容、 第二电容和第五晶体管； 其中
所述第一电容一端与所述驱动晶体管的栅极连接， 另一端与所述第二电 容的一端连接；
所述第二电容的另一端与所述驱动晶体管的源极连接；
所述第五晶体管的漏极连接在所述第一电容和第二电容之间， 栅极与第 二控制线连接， 源极与所述驱动晶体管的源极连接。
4、根据权利要求 1至 3任一所述的像素单元驱动电路， 所述开关单元包 括： 第二晶体管、 第四晶体管；
所述第二晶体管的漏极与高电压信号端连接， 栅极与第二控制线连接， 源极与所述驱动晶体管的漏极连接；
所述第四晶体管的源极与所述驱动晶体管的栅极连接， 栅极与第一控制 线连接， 漏极与高电压信号端连接。
5、 根据权利要求 4所述的像素单元驱动电路， 所述开关单元还包括： 第三晶体管， 其源极与所述驱动晶体管漏极连接， 漏极与高电压信号端 连接， 栅极与第一控制线连接。
6、根据权利要求 5所述的像素单元驱动电路， 所述驱动晶体管、 第二晶 体管、 第三晶体管、 第四晶体管、 第五晶体管为 n型薄膜晶体管。
7、 一种像素单元， 包括 OLED和如权利要求 1至 6中任一权利要求所 述的像素单元驱动电路， 所述像素单元驱动电路与所述 OLED的阴极连接， 所述 OLED的阳极与高电压信号端连接。
8、 一种显示装置， 包括多个如权利要求 7所述的像素单元。
PCT/CN2012/087715 2012-01-04 2012-12-27 像素单元驱动电路、像素单元和显示装置 Ceased WO2013102416A1 (zh)

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