WO2013097608A1 - Transistor à effet de champ métal-oxyde semiconducteur à double diffusion latérale - Google Patents

Transistor à effet de champ métal-oxyde semiconducteur à double diffusion latérale Download PDF

Info

Publication number
WO2013097608A1
WO2013097608A1 PCT/CN2012/086518 CN2012086518W WO2013097608A1 WO 2013097608 A1 WO2013097608 A1 WO 2013097608A1 CN 2012086518 W CN2012086518 W CN 2012086518W WO 2013097608 A1 WO2013097608 A1 WO 2013097608A1
Authority
WO
WIPO (PCT)
Prior art keywords
effect transistor
oxide semiconductor
region
metal oxide
drain region
Prior art date
Application number
PCT/CN2012/086518
Other languages
English (en)
Chinese (zh)
Inventor
韩广涛
颜剑
Original Assignee
无锡华润上华半导体有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡华润上华半导体有限公司 filed Critical 无锡华润上华半导体有限公司
Publication of WO2013097608A1 publication Critical patent/WO2013097608A1/fr

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the invention belongs to a lateral double-diffused metal oxide semiconductor field effect transistor (Lateral Double Diffused)
  • the field of MOSFET (LDMOS) technology in particular, relates to an LDMOS in which a field auxiliary electrode is disposed on a field oxide layer to increase its breakdown voltage in an on state.
  • LDMOS As a power switching device, LDMOS has the advantages of relatively high operating voltage, simple process, and easy process compatibility with low-voltage CMOS circuits. It includes “Off-state” and “On” (On). -state)". With the widespread use of LDMOS power integrated circuits (Power Integrated Circuit (PIC), the performance requirements of LDMOS devices are also getting higher and higher, one of the important requirements is to increase the breakdown voltage of LDMOS in the open state.
  • PIC Power Integrated Circuit
  • Figure 1 shows the basic cross-sectional structure of a conventional LDMOS.
  • LDMOS On the P-type substrate 100 of 10, an active region 110, a drain region 170, a P-type body region 120, a high-voltage N-well 150 (for forming a drift region), a source are formed on a P-type substrate 100 by a pattern doping process.
  • a source (S) and a drain (D) Above the region 110 and the drain region 170, a source (S) and a drain (D) (not shown) may be respectively patterned, and the gate dielectric layer 130 is patterned and oxidized to form a gate dielectric layer 130, and is formed on the gate dielectric.
  • a gate 140 (G) of polysilicon is formed on layer 130 for use on high voltage N-well 250 LOCOS ( Local Oxidation of Silicon The local oxidation of silicon process forms a field oxide layer 160, which may extend partially over the field oxide layer 160.
  • the LDMOS shown in Figure 1 typically operates under high voltage conditions.
  • the gate 140 and drain region 170 are biased high, and the drift region is thus continuously depleted; as the drain region 170 is biased
  • the voltage is continuously increased (ie, the source-drain voltage Vds is continuously increased), and the depletion layer in the drift region is continuously expanded toward the drain region 170; when the depletion layer is about to contact the N+ well boundary of the drain region 170, due to the drain region 170
  • the high doping characteristics the depletion layer continues to expand to the drain region 170 is limited, at the intersection of the drain region 170 and the drift region, the power line distribution tends to be dense, that is, the high voltage biased by the drain region 170 is easily loaded at the junction.
  • the electric field in this region increases rapidly with the increase of Vds; further, it is easy to induce impact ionization due to large electric field (Impact Ionization) leads to breakdown.
  • the conventional LDMOS of the embodiment shown in FIG. 1 is easily broken down in the open state as the Vds rises, that is, the breakdown voltage in the on state is low.
  • One of the objects of the present invention is to increase the breakdown voltage of an LDMOS in an on state.
  • the present invention provides an LDMOS including a source region, a gate dielectric layer, a drain region, a drift region disposed between the drain region and the gate dielectric layer, and a field oxide layer disposed over the drift region.
  • a gate electrode substantially disposed on the gate dielectric layer, wherein a field auxiliary electrode is disposed on a portion of the field oxide layer relatively close to the drain region, and in the on state, the field region assists The electrode is biased to the same voltage as the voltage biased by the drain region.
  • an LDMOS wherein the field auxiliary electrode and the drain region are biased by a voltage of the same magnitude.
  • the distance between the field auxiliary electrode and the drain region is 5% of the length of the field oxide layer to 25%.
  • the field auxiliary electrode and the gate are both polysilicon electrodes, and the field auxiliary electrode and the gate are patterned in synchronization.
  • the drift region is doped the same type as the drain region, and the drift region is lower than the drain region doping concentration.
  • the drift region has a doping concentration ranging from 1 ⁇ 10 15 /cm 3 to 1 ⁇ 10 18 /cm 3 .
  • the doping concentration of the drain region ranges from 1 ⁇ 10 18 /cm 3 to 1 ⁇ 10 22 /cm 3 .
  • the field auxiliary electrode is disposed over the field oxide layer in one or more segments.
  • an LDMOS wherein the field auxiliary electrode is disposed separately from a drain on the drain region.
  • the field auxiliary electrode is integrally provided with a drain on the drain region.
  • the field auxiliary electrode and the drain are made of a metal or metal silicide material.
  • the LDMOS is an N-channel LDMOS, and the voltage direction is a positive direction.
  • the technical effect of the present invention is that by providing a field auxiliary electrode on the field oxide layer, it biases the same voltage as the bias voltage in the open state in the on state, so that the field area auxiliary electrode can be substantially below
  • the impurity concentration in the drift region increases, and when the Vds increases, the region prevents the depletion layer from expanding toward the highly doped drain region boundary, can reduce the electric field at the intersection of the drain region and the drift region, optimize the electric field distribution, and avoid collision ionization. Occurs to increase the breakdown voltage and thereby increase the operating voltage of the LDMOS.
  • FIG. 1 is a schematic diagram showing the basic cross-sectional structure of a conventional LDMOS.
  • FIG. 2 is a schematic cross-sectional structural view of an LDMOS according to an embodiment of the invention.
  • Figure 3 is a schematic diagram of the transfer characteristic curve of the LDMOS.
  • FIG. 4 is a schematic cross-sectional structural view of an LDMOS according to still another embodiment of the present invention.
  • the directional terms of "upper”, “lower”, “left”, and “right” are defined with respect to the orientation of the LDMOS in the drawing (for example, the left-right direction refers to the channel direction of the LDMOS, which is parallel On the surface of the substrate, the up and down direction is perpendicular to the surface of the substrate). Also, it should be understood that these directional terms are relative concepts that are used in relation to the description and clarification, which may vary accordingly depending on the orientation in which the LDMOS is placed.
  • FIG. 2 is a schematic cross-sectional view showing the basic structure of an LDMOS according to an embodiment of the invention.
  • LDMOS 20 is an N-channel LDMOS, and the LDMOS structure of this embodiment will be specifically described below with reference to FIG.
  • an LDMOS is formed on a substrate 200.
  • the substrate 200 is P-type doped, and its specific doping concentration is not limited by the present invention.
  • the substrate 200 may be specifically formed by epitaxial growth or may be a wafer substrate.
  • An active region 210 and a drain region 270 are formed in the substrate 200.
  • the source region 210 and the drain region 270 are formed by patterning the substrate 200 to N-type doping to form an N+ well, the source region 210 and the drain region 270.
  • the doping concentration can be the same, so that the two can be formed by simultaneous doping.
  • a source (not shown) and a drain 271 may be formed over the source region 210 and the drain region 270, respectively; a source for extracting the source region 210, which are defined as source terminals of the LDMOS; and a drain 271 for A drain region 270 is drawn, which is defined as the drain terminal of the LDMOS.
  • the N-type doping concentration of the source region 210 and the drain region 270 may range from 1 ⁇ 10 18 /cm 3 to 1 ⁇ 10 22 /cm 3 , for example, the doping concentration is set to 1 ⁇ 10 20 /cm 3 .
  • the doping concentration of the body region 220 may range from 1 x 10 15 /cm 3 to 1 x 10 18 /cm 3 , for example, the doping concentration is set to ? 1e17? .
  • the drift region 250 is N-doped (N-well as shown), and its doping concentration is generally lower than the doping concentration of the drain region 270.
  • the drift region 250 is doped.
  • the concentration may range from 1 ⁇ 10 15 /cm 3 to 1 ⁇ 10 18 /cm 3 , for example, the doping concentration is set to 5 ⁇ 10 16 /cm 3 .
  • the source and the drain as shown in Fig. 2, specifically, it may be formed by patterning oxidation, and of course, may be patterned by thin film deposition or the like.
  • the field oxide layer 260 is formed by patterning oxidation using a LOCOS process.
  • a gate 240 is patterned on the gate dielectric layer 230. As illustrated in FIG. 2, the gate 240 can cover a portion of the field oxide layer 260 adjacent to the gate dielectric layer 230.
  • the particular material of the gate 240 is not limited by the present invention, for example, it can be formed by low resistivity polysilicon patterning.
  • a field auxiliary electrode 280 is patterned, and the field auxiliary electrode 280 is disposed relatively close to the drain region 270. It is to be understood that the position of the field auxiliary electrode 280 is relative to field oxidation. Defined by the gate dielectric layer 230 and the drain region 270 on both sides of the layer 260, in the present invention, "relatively close to the drain region 270" can be understood as the distance between the field region auxiliary electrode 280 and the drain region 270 is less than or equal to the field region auxiliary electrode 280.
  • the field auxiliary electrode 280 is placed to the right of the centerline 261 of the field oxide layer 260 (i.e., alongside the drain region); the field region auxiliary electrode 280 can be selected to form a low resistivity polysilicon pattern.
  • Vds is greater than zero, that is, the drain terminal is biased to the forward voltage, and the source terminal is biased at 0 volts; meanwhile, when the field region auxiliary electrode 280 is biased to the forward voltage ( The same as the voltage direction of the drain region bias, both positive), the drift region corresponding to the lower portion of the field auxiliary electrode 280 will be enhanced, and the N-type impurity concentration will greatly increase (the electron concentration increases), therefore, the field auxiliary electrode The impurity concentration in the lower region of 280 is relatively high.
  • the power line of the region will be denser and the electric field is relatively higher, thereby enabling
  • the depletion layer is further depleted to the drain region 280, that is, the depletion layer is difficult to expand toward the highly doped drain region 280 boundary. Therefore, the electric field at the intersection of the drain region 280 and the drift region 250 can be reduced, and the collision ionization under the large electric field condition is prevented from being caused by the increase of the Vds, and the breakdown voltage in the open state is greatly improved.
  • the field auxiliary electrode 280 biases the same direction and the same magnitude of voltage as the drain terminal.
  • the drain 270 and the field auxiliary electrode 280 are connected to the same voltage source, thus reducing the design of the corresponding power supply. It helps to reduce the peripheral circuits of LDMOS.
  • FIG. 3 shows a schematic diagram of the output characteristics of the LDMOS.
  • the curve 11 is the transfer characteristic curve of the LDMOS of the embodiment shown in FIG. 1
  • the field auxiliary electrode 280 when the field auxiliary electrode 280 is disposed relatively close to the drain region 270, its distance from the drain region 270 is preferably 5% to 25% of the length of the field oxide layer 260 (the length in the channel direction). , for example, 10%.
  • the area of the field auxiliary electrode 280 is smaller than the area of the field oxide layer 260, and the area size ranges from 5% to 25 of the area of the field oxide layer 260. %, for example, 10%.
  • the field auxiliary electrode 280 is polysilicon, it may be P-type doped or N-type doped, and its resistivity is low.
  • the specific thickness of the field auxiliary electrode 280 and the doping concentration are not limited by the embodiments of the present invention.
  • the bias voltage of the field auxiliary electrode 280 is also not limited by the above embodiments, for example, it can also bias other forward voltages, such as +10V.
  • the field auxiliary electrode 280 can be disposed in multiple stages (one stage setting in FIG. 2), and each of the field auxiliary electrodes 280 is disposed opposite to the drained area 270.
  • the working principle of the auxiliary electrode 280 of each segment is substantially the same as that of the field auxiliary electrode 280 in the above embodiment.
  • FIG. 4 is a schematic cross-sectional view showing the basic structure of an LDMOS according to another embodiment of the present invention.
  • the drain electrode 271 extends over the field oxide layer 260, so that a part of the electrode above the field oxide layer 260 is defined as the field area auxiliary electrode 380, so the field area assists
  • the electrode 380 is integrally provided with respect to the drain 271.
  • the field auxiliary electrode 380 and the drain 271 are made of the same material, for example, a metal or metal salicide electrode.
  • the LDMOS disclosed in the above embodiments are all N-channel LDMOS, and those skilled in the art propose a P-channel LDMOS with similar structure according to the above teachings, which will not be exemplified herein; it should be understood that the field of the P-channel LDMOS
  • the auxiliary electrode and the drain region are biased in a negative direction in an open state to increase the impurity concentration of the region corresponding to the drift region substantially below the field auxiliary electrode.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

L'invention concerne un transistor à effet de champ métal-oxyde semiconducteur à double diffusion latérale (LDMOS) (20). Le LDMOS (20) comprend une région de source (210), une couche diélectrique de grille (230), une région de drain (270), une région de dérive (250) disposée entre la région de drain (270) et la couche diélectrique de grille (230), une couche d'oxyde de champ (260) disposée sur la région de dérive (250) et une électrode de grille (240) sensiblement disposée sur la couche diélectrique de grille (230), une électrode auxiliaire de région de champ (280) étant disposée sur la partie de la couche d'oxyde de champ (260) relativement proche à la région de drain (270), et l'électrode auxiliaire de région de champ (280) étant polarisée selon une tension dans la même direction que la tension polarisée de la région de drain (270) dans l'état allumé. Le LDMOS (20) a les caractéristiques d'une haute tension de rupture dans l'état allumé et d'une haute tension de fonctionnement.
PCT/CN2012/086518 2011-12-30 2012-12-13 Transistor à effet de champ métal-oxyde semiconducteur à double diffusion latérale WO2013097608A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110453969.0A CN103187443B (zh) 2011-12-30 2011-12-30 横向双扩散金属氧化物半导体场效应晶体管
CN201110453969.0 2011-12-30

Publications (1)

Publication Number Publication Date
WO2013097608A1 true WO2013097608A1 (fr) 2013-07-04

Family

ID=48678529

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/086518 WO2013097608A1 (fr) 2011-12-30 2012-12-13 Transistor à effet de champ métal-oxyde semiconducteur à double diffusion latérale

Country Status (2)

Country Link
CN (1) CN103187443B (fr)
WO (1) WO2013097608A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6820811B2 (ja) * 2017-08-08 2021-01-27 三菱電機株式会社 半導体装置および電力変換装置
CN110416301A (zh) * 2018-04-28 2019-11-05 中芯国际集成电路制造(上海)有限公司 横向双扩散晶体管及其形成方法
CN109713033A (zh) * 2018-12-29 2019-05-03 上海华力微电子有限公司 Ldmos器件及其制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1632931A (zh) * 2004-12-23 2005-06-29 上海华虹（集团）有限公司 提高表面降场型ldmos器件耐压的工艺
CN201910425U (zh) * 2010-12-30 2011-07-27 厦门烁芯光电技术有限公司 一种适用于高低压单片集成的ldmos器件
CN102157518A (zh) * 2011-01-07 2011-08-17 北方工业大学 单片集成的新型双重突波保护器件及其制作方法
CN102176469A (zh) * 2011-03-10 2011-09-07 杭州电子科技大学 一种具有p埋层的SOI nLDMOS器件单元

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2743978Y (zh) * 2004-06-24 2005-11-30 东南大学 多电位场极板横向高压n型金属氧化物半导体管
KR100628250B1 (ko) * 2005-09-28 2006-09-27 동부일렉트로닉스 주식회사 전력용 반도체 소자 및 그의 제조방법
CN101969074B (zh) * 2010-10-28 2012-07-04 电子科技大学 一种高压ldmos器件
CN102169903B (zh) * 2011-03-22 2013-05-01 成都芯源系统有限公司 Ldmos器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1632931A (zh) * 2004-12-23 2005-06-29 上海华虹（集团）有限公司 提高表面降场型ldmos器件耐压的工艺
CN201910425U (zh) * 2010-12-30 2011-07-27 厦门烁芯光电技术有限公司 一种适用于高低压单片集成的ldmos器件
CN102157518A (zh) * 2011-01-07 2011-08-17 北方工业大学 单片集成的新型双重突波保护器件及其制作方法
CN102176469A (zh) * 2011-03-10 2011-09-07 杭州电子科技大学 一种具有p埋层的SOI nLDMOS器件单元

Also Published As

Publication number Publication date
CN103187443B (zh) 2016-06-01
CN103187443A (zh) 2013-07-03

Similar Documents

Publication Publication Date Title
US9418993B2 (en) Device and method for a LDMOS design for a FinFET integrated circuit
TWI501399B (zh) 橫向電晶體及其製造方法
US20130193509A1 (en) Soi lateral mosfet devices
EP3217431B1 (fr) Dispositif semi-conducteur pouvant fonctionner à haute tension
US20070181941A1 (en) High voltage semiconductor devices and methods for fabricating the same
JP2002319675A (ja) 埋設導電層を備えた高電圧トランジスタ
WO2013123805A1 (fr) Transistor à effet de champ à semiconducteur d'oxyde de métal latéral double diffusé
JP2001015741A (ja) 電界効果トランジスタ
EP2203933A2 (fr) Dispositif à semi-conducteur à tension élevée
US9716169B2 (en) Lateral double diffused metal oxide semiconductor field-effect transistor
US11322617B2 (en) Semiconductor device
WO2011066728A1 (fr) Transistor à effet de champ à grille isolante de type accumulation en matériau hybride
TW200303602A (en) Self-alignment of seperated regions in a lateral MOSFET structure of an integrated circuit
WO2012006805A1 (fr) Composant mos avec une structure bts et son procédé de fabrication
WO2013097608A1 (fr) Transistor à effet de champ métal-oxyde semiconducteur à double diffusion latérale
KR20110024328A (ko) 고유전율막을 갖는 터널링 전계효과 트랜지스터
TWI398951B (zh) 具分離式閘極垂直型金氧半電晶體元件結構及其製造方法
WO2013155760A1 (fr) Structure semi-conductrice et procédé de fabrication de celle-ci
US8823098B2 (en) Structures for power transistor and methods of manufacture
CN109390409B (zh) 一种阈值可调式高压金属氧化物半导体器件及其制备方法
TWI824365B (zh) 感應超結電晶體
KR100388063B1 (ko) 전력 집적 회로 제조 방법
WO2015021927A1 (fr) Transistor à effet de champ métal-oxyde-semiconducteur à double diffusion latérale
WO2023224332A1 (fr) Transistor à effet de champ à effet tunnel comportant un motif semi-conducteur en forme d'ailette et une région de drain comportant une partie centrale concave
CN114121950A (zh) 具有背对背连接的晶体管的负载开关

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12863472

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12863472

Country of ref document: EP

Kind code of ref document: A1