WO2013097608A1 - Lateral double diffused metal oxide semiconductor field effect transistor - Google Patents

Lateral double diffused metal oxide semiconductor field effect transistor Download PDF

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WO2013097608A1
WO2013097608A1 PCT/CN2012/086518 CN2012086518W WO2013097608A1 WO 2013097608 A1 WO2013097608 A1 WO 2013097608A1 CN 2012086518 W CN2012086518 W CN 2012086518W WO 2013097608 A1 WO2013097608 A1 WO 2013097608A1
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effect transistor
oxide semiconductor
region
metal oxide
drain region
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PCT/CN2012/086518
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French (fr)
Chinese (zh)
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韩广涛
颜剑
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无锡华润上华半导体有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41758—Source or drain electrodes for field effect devices for lateral devices with structured layout for source or drain region, i.e. the source or drain region having cellular, interdigitated or ring structure or being curved or angular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Definitions

  • the invention belongs to a lateral double-diffused metal oxide semiconductor field effect transistor (Lateral Double Diffused)
  • the field of MOSFET (LDMOS) technology in particular, relates to an LDMOS in which a field auxiliary electrode is disposed on a field oxide layer to increase its breakdown voltage in an on state.
  • LDMOS As a power switching device, LDMOS has the advantages of relatively high operating voltage, simple process, and easy process compatibility with low-voltage CMOS circuits. It includes “Off-state” and “On” (On). -state)". With the widespread use of LDMOS power integrated circuits (Power Integrated Circuit (PIC), the performance requirements of LDMOS devices are also getting higher and higher, one of the important requirements is to increase the breakdown voltage of LDMOS in the open state.
  • PIC Power Integrated Circuit
  • Figure 1 shows the basic cross-sectional structure of a conventional LDMOS.
  • LDMOS On the P-type substrate 100 of 10, an active region 110, a drain region 170, a P-type body region 120, a high-voltage N-well 150 (for forming a drift region), a source are formed on a P-type substrate 100 by a pattern doping process.
  • a source (S) and a drain (D) Above the region 110 and the drain region 170, a source (S) and a drain (D) (not shown) may be respectively patterned, and the gate dielectric layer 130 is patterned and oxidized to form a gate dielectric layer 130, and is formed on the gate dielectric.
  • a gate 140 (G) of polysilicon is formed on layer 130 for use on high voltage N-well 250 LOCOS ( Local Oxidation of Silicon The local oxidation of silicon process forms a field oxide layer 160, which may extend partially over the field oxide layer 160.
  • the LDMOS shown in Figure 1 typically operates under high voltage conditions.
  • the gate 140 and drain region 170 are biased high, and the drift region is thus continuously depleted; as the drain region 170 is biased
  • the voltage is continuously increased (ie, the source-drain voltage Vds is continuously increased), and the depletion layer in the drift region is continuously expanded toward the drain region 170; when the depletion layer is about to contact the N+ well boundary of the drain region 170, due to the drain region 170
  • the high doping characteristics the depletion layer continues to expand to the drain region 170 is limited, at the intersection of the drain region 170 and the drift region, the power line distribution tends to be dense, that is, the high voltage biased by the drain region 170 is easily loaded at the junction.
  • the electric field in this region increases rapidly with the increase of Vds; further, it is easy to induce impact ionization due to large electric field (Impact Ionization) leads to breakdown.
  • the conventional LDMOS of the embodiment shown in FIG. 1 is easily broken down in the open state as the Vds rises, that is, the breakdown voltage in the on state is low.
  • One of the objects of the present invention is to increase the breakdown voltage of an LDMOS in an on state.
  • the present invention provides an LDMOS including a source region, a gate dielectric layer, a drain region, a drift region disposed between the drain region and the gate dielectric layer, and a field oxide layer disposed over the drift region.
  • a gate electrode substantially disposed on the gate dielectric layer, wherein a field auxiliary electrode is disposed on a portion of the field oxide layer relatively close to the drain region, and in the on state, the field region assists The electrode is biased to the same voltage as the voltage biased by the drain region.
  • an LDMOS wherein the field auxiliary electrode and the drain region are biased by a voltage of the same magnitude.
  • the distance between the field auxiliary electrode and the drain region is 5% of the length of the field oxide layer to 25%.
  • the field auxiliary electrode and the gate are both polysilicon electrodes, and the field auxiliary electrode and the gate are patterned in synchronization.
  • the drift region is doped the same type as the drain region, and the drift region is lower than the drain region doping concentration.
  • the drift region has a doping concentration ranging from 1 ⁇ 10 15 /cm 3 to 1 ⁇ 10 18 /cm 3 .
  • the doping concentration of the drain region ranges from 1 ⁇ 10 18 /cm 3 to 1 ⁇ 10 22 /cm 3 .
  • the field auxiliary electrode is disposed over the field oxide layer in one or more segments.
  • an LDMOS wherein the field auxiliary electrode is disposed separately from a drain on the drain region.
  • the field auxiliary electrode is integrally provided with a drain on the drain region.
  • the field auxiliary electrode and the drain are made of a metal or metal silicide material.
  • the LDMOS is an N-channel LDMOS, and the voltage direction is a positive direction.
  • the technical effect of the present invention is that by providing a field auxiliary electrode on the field oxide layer, it biases the same voltage as the bias voltage in the open state in the on state, so that the field area auxiliary electrode can be substantially below
  • the impurity concentration in the drift region increases, and when the Vds increases, the region prevents the depletion layer from expanding toward the highly doped drain region boundary, can reduce the electric field at the intersection of the drain region and the drift region, optimize the electric field distribution, and avoid collision ionization. Occurs to increase the breakdown voltage and thereby increase the operating voltage of the LDMOS.
  • FIG. 1 is a schematic diagram showing the basic cross-sectional structure of a conventional LDMOS.
  • FIG. 2 is a schematic cross-sectional structural view of an LDMOS according to an embodiment of the invention.
  • Figure 3 is a schematic diagram of the transfer characteristic curve of the LDMOS.
  • FIG. 4 is a schematic cross-sectional structural view of an LDMOS according to still another embodiment of the present invention.
  • the directional terms of "upper”, “lower”, “left”, and “right” are defined with respect to the orientation of the LDMOS in the drawing (for example, the left-right direction refers to the channel direction of the LDMOS, which is parallel On the surface of the substrate, the up and down direction is perpendicular to the surface of the substrate). Also, it should be understood that these directional terms are relative concepts that are used in relation to the description and clarification, which may vary accordingly depending on the orientation in which the LDMOS is placed.
  • FIG. 2 is a schematic cross-sectional view showing the basic structure of an LDMOS according to an embodiment of the invention.
  • LDMOS 20 is an N-channel LDMOS, and the LDMOS structure of this embodiment will be specifically described below with reference to FIG.
  • an LDMOS is formed on a substrate 200.
  • the substrate 200 is P-type doped, and its specific doping concentration is not limited by the present invention.
  • the substrate 200 may be specifically formed by epitaxial growth or may be a wafer substrate.
  • An active region 210 and a drain region 270 are formed in the substrate 200.
  • the source region 210 and the drain region 270 are formed by patterning the substrate 200 to N-type doping to form an N+ well, the source region 210 and the drain region 270.
  • the doping concentration can be the same, so that the two can be formed by simultaneous doping.
  • a source (not shown) and a drain 271 may be formed over the source region 210 and the drain region 270, respectively; a source for extracting the source region 210, which are defined as source terminals of the LDMOS; and a drain 271 for A drain region 270 is drawn, which is defined as the drain terminal of the LDMOS.
  • the N-type doping concentration of the source region 210 and the drain region 270 may range from 1 ⁇ 10 18 /cm 3 to 1 ⁇ 10 22 /cm 3 , for example, the doping concentration is set to 1 ⁇ 10 20 /cm 3 .
  • the doping concentration of the body region 220 may range from 1 x 10 15 /cm 3 to 1 x 10 18 /cm 3 , for example, the doping concentration is set to ? 1e17? .
  • the drift region 250 is N-doped (N-well as shown), and its doping concentration is generally lower than the doping concentration of the drain region 270.
  • the drift region 250 is doped.
  • the concentration may range from 1 ⁇ 10 15 /cm 3 to 1 ⁇ 10 18 /cm 3 , for example, the doping concentration is set to 5 ⁇ 10 16 /cm 3 .
  • the source and the drain as shown in Fig. 2, specifically, it may be formed by patterning oxidation, and of course, may be patterned by thin film deposition or the like.
  • the field oxide layer 260 is formed by patterning oxidation using a LOCOS process.
  • a gate 240 is patterned on the gate dielectric layer 230. As illustrated in FIG. 2, the gate 240 can cover a portion of the field oxide layer 260 adjacent to the gate dielectric layer 230.
  • the particular material of the gate 240 is not limited by the present invention, for example, it can be formed by low resistivity polysilicon patterning.
  • a field auxiliary electrode 280 is patterned, and the field auxiliary electrode 280 is disposed relatively close to the drain region 270. It is to be understood that the position of the field auxiliary electrode 280 is relative to field oxidation. Defined by the gate dielectric layer 230 and the drain region 270 on both sides of the layer 260, in the present invention, "relatively close to the drain region 270" can be understood as the distance between the field region auxiliary electrode 280 and the drain region 270 is less than or equal to the field region auxiliary electrode 280.
  • the field auxiliary electrode 280 is placed to the right of the centerline 261 of the field oxide layer 260 (i.e., alongside the drain region); the field region auxiliary electrode 280 can be selected to form a low resistivity polysilicon pattern.
  • Vds is greater than zero, that is, the drain terminal is biased to the forward voltage, and the source terminal is biased at 0 volts; meanwhile, when the field region auxiliary electrode 280 is biased to the forward voltage ( The same as the voltage direction of the drain region bias, both positive), the drift region corresponding to the lower portion of the field auxiliary electrode 280 will be enhanced, and the N-type impurity concentration will greatly increase (the electron concentration increases), therefore, the field auxiliary electrode The impurity concentration in the lower region of 280 is relatively high.
  • the power line of the region will be denser and the electric field is relatively higher, thereby enabling
  • the depletion layer is further depleted to the drain region 280, that is, the depletion layer is difficult to expand toward the highly doped drain region 280 boundary. Therefore, the electric field at the intersection of the drain region 280 and the drift region 250 can be reduced, and the collision ionization under the large electric field condition is prevented from being caused by the increase of the Vds, and the breakdown voltage in the open state is greatly improved.
  • the field auxiliary electrode 280 biases the same direction and the same magnitude of voltage as the drain terminal.
  • the drain 270 and the field auxiliary electrode 280 are connected to the same voltage source, thus reducing the design of the corresponding power supply. It helps to reduce the peripheral circuits of LDMOS.
  • FIG. 3 shows a schematic diagram of the output characteristics of the LDMOS.
  • the curve 11 is the transfer characteristic curve of the LDMOS of the embodiment shown in FIG. 1
  • the field auxiliary electrode 280 when the field auxiliary electrode 280 is disposed relatively close to the drain region 270, its distance from the drain region 270 is preferably 5% to 25% of the length of the field oxide layer 260 (the length in the channel direction). , for example, 10%.
  • the area of the field auxiliary electrode 280 is smaller than the area of the field oxide layer 260, and the area size ranges from 5% to 25 of the area of the field oxide layer 260. %, for example, 10%.
  • the field auxiliary electrode 280 is polysilicon, it may be P-type doped or N-type doped, and its resistivity is low.
  • the specific thickness of the field auxiliary electrode 280 and the doping concentration are not limited by the embodiments of the present invention.
  • the bias voltage of the field auxiliary electrode 280 is also not limited by the above embodiments, for example, it can also bias other forward voltages, such as +10V.
  • the field auxiliary electrode 280 can be disposed in multiple stages (one stage setting in FIG. 2), and each of the field auxiliary electrodes 280 is disposed opposite to the drained area 270.
  • the working principle of the auxiliary electrode 280 of each segment is substantially the same as that of the field auxiliary electrode 280 in the above embodiment.
  • FIG. 4 is a schematic cross-sectional view showing the basic structure of an LDMOS according to another embodiment of the present invention.
  • the drain electrode 271 extends over the field oxide layer 260, so that a part of the electrode above the field oxide layer 260 is defined as the field area auxiliary electrode 380, so the field area assists
  • the electrode 380 is integrally provided with respect to the drain 271.
  • the field auxiliary electrode 380 and the drain 271 are made of the same material, for example, a metal or metal salicide electrode.
  • the LDMOS disclosed in the above embodiments are all N-channel LDMOS, and those skilled in the art propose a P-channel LDMOS with similar structure according to the above teachings, which will not be exemplified herein; it should be understood that the field of the P-channel LDMOS
  • the auxiliary electrode and the drain region are biased in a negative direction in an open state to increase the impurity concentration of the region corresponding to the drift region substantially below the field auxiliary electrode.

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Abstract

A lateral double diffused metal oxide semiconductor field effect transistor (LDMOS) (20) is provided. The LDMOS (20) comprises a source region (210), a gate dielectric layer (230), a drain region (270), a drift region (250) arranged between the drain region (270) and the gate dielectric layer (230), a field oxide layer (260) arranged on the drift region (250) and a gate electrode (240) arranged on the gate dielectric layer (230) substantially, wherein a field region auxiliary electrode (280) is arranged on the portion of the field oxide layer (260) relatively close to the drain region (270), and the field region auxiliary electrode (280) is biased a voltage in the same direction of the voltage biased to the drain region (270) in on state. The LDMOS (20) has the characteristics of a high breakdown voltage in on state and a high operating voltage.

Description

横向双扩散金属氧化物半导体场效应晶体管Transverse double diffused metal oxide semiconductor field effect transistor
【技术领域】[Technical Field]
本发明属于横向双扩散金属氧化物半导体场效应晶体管（Lateral Double Diffused MOSFET，LDMOS）技术领域，尤其涉及在场氧化层上设置场辅助电极以提高其在开态的崩溃电压的LDMOS。The invention belongs to a lateral double-diffused metal oxide semiconductor field effect transistor (Lateral Double Diffused) The field of MOSFET (LDMOS) technology, in particular, relates to an LDMOS in which a field auxiliary electrode is disposed on a field oxide layer to increase its breakdown voltage in an on state.
【背景技术】【Background technique】
LDMOS作为一种功率开关器件，其具有工作电压相对高、工艺简单、易于同低压CMOS电路在工艺上兼容等优点，在工作时包括有“关态（Off-state）”和“开态（On-state）”。随着LDMOS的广泛应用功率集成电路（Power Integrated Circuit，PIC），对LDMOS的器件性能要求也越来越高，其中一个重要要求在于提高LDMOS在开态的崩溃电压。As a power switching device, LDMOS has the advantages of relatively high operating voltage, simple process, and easy process compatibility with low-voltage CMOS circuits. It includes "Off-state" and "On" (On). -state)". With the widespread use of LDMOS power integrated circuits (Power Integrated Circuit (PIC), the performance requirements of LDMOS devices are also getting higher and higher, one of the important requirements is to increase the breakdown voltage of LDMOS in the open state.
图1所示为传统LDMOS的基本截面结构示意图。如图1所示，在LDMOS 10的P型衬底100上，在P型衬底100上通过构图掺杂工艺形成有源区110、漏区170、P型体区120、高压N阱150（用于形成漂移区），源区110和漏区170之上可以分别构图引出源极（S）和漏极（D）（图中未示出），P型体区220之上构图氧化形成栅介质层130、并在栅介质层130上形成多晶硅的栅极140（G），在高压N阱250上采用 LOCOS （ Local Oxidation of Silicon ，硅的局部氧化）工艺形成场氧化层160，栅极140可以部分地延伸至场氧化层160之上。Figure 1 shows the basic cross-sectional structure of a conventional LDMOS. As shown in Figure 1, in LDMOS On the P-type substrate 100 of 10, an active region 110, a drain region 170, a P-type body region 120, a high-voltage N-well 150 (for forming a drift region), a source are formed on a P-type substrate 100 by a pattern doping process. Above the region 110 and the drain region 170, a source (S) and a drain (D) (not shown) may be respectively patterned, and the gate dielectric layer 130 is patterned and oxidized to form a gate dielectric layer 130, and is formed on the gate dielectric. A gate 140 (G) of polysilicon is formed on layer 130 for use on high voltage N-well 250 LOCOS ( Local Oxidation of Silicon The local oxidation of silicon process forms a field oxide layer 160, which may extend partially over the field oxide layer 160.
图1所示的LDMOS通常工作在高压条件下，例如，在开态时，栅极140和漏区170会被偏置高压，漂移区因此会被不断耗尽；随着漏区170上偏置的电压不断提高（也即源漏电压Vds不断提高），漂移区中的耗尽层会向漏区170不断扩展；当耗尽层快要接触到漏区170的N+阱边界时，由于漏区170的高掺杂特性，耗尽层向漏区170继续扩展有限，在漏区170与漂移区的交接处，电力线分布趋于密集，也即漏区170偏置的高压容易加载在该交接处的有限区域内，该区域电场随着Vds的增加而快速增大；进而，也容易由于大电场引发碰撞电离（Impact Ionization）导致击穿。The LDMOS shown in Figure 1 typically operates under high voltage conditions. For example, in the on state, the gate 140 and drain region 170 are biased high, and the drift region is thus continuously depleted; as the drain region 170 is biased The voltage is continuously increased (ie, the source-drain voltage Vds is continuously increased), and the depletion layer in the drift region is continuously expanded toward the drain region 170; when the depletion layer is about to contact the N+ well boundary of the drain region 170, due to the drain region 170 The high doping characteristics, the depletion layer continues to expand to the drain region 170 is limited, at the intersection of the drain region 170 and the drift region, the power line distribution tends to be dense, that is, the high voltage biased by the drain region 170 is easily loaded at the junction. In a finite region, the electric field in this region increases rapidly with the increase of Vds; further, it is easy to induce impact ionization due to large electric field (Impact Ionization) leads to breakdown.
因此，图1所示实施例的传统LDMOS在开态下随着Vds的上升而容易被击穿，也即开态下的崩溃电压较低。Therefore, the conventional LDMOS of the embodiment shown in FIG. 1 is easily broken down in the open state as the Vds rises, that is, the breakdown voltage in the on state is low.
中国专利申请号为CN201110077379.2、名称为“LDMOS器件”的发明专利中，公开了一种LDMOS，其在漂移区中设置有电容区域，以改善漂移区域的电场分布，从而提高击穿电压（不同于崩溃电压）、减小导通电阻。但是，其并没有解决图1所示LDMOS中存在的问题。Chinese Patent Application No. CN201110077379.2, entitled "LDMOS Device", discloses an LDMOS which is provided with a capacitor region in the drift region to improve the electric field distribution in the drift region, thereby increasing the breakdown voltage ( Unlike the breakdown voltage), reduce the on-resistance. However, it does not solve the problem in the LDMOS shown in Fig. 1.
【发明内容】[Summary of the Invention]
本发明的目的之一在于，提高LDMOS在开态下的崩溃电压。One of the objects of the present invention is to increase the breakdown voltage of an LDMOS in an on state.
为实现以上目的或者其他目的，本发明提供一种LDMOS，包括源区、栅介质层、漏区、设置在漏区和栅介质层之间的漂移区、设置在漂移区之上的场氧化层、基本设置在栅介质层之上的栅极，其特征在于，在所述场氧化层的相对靠近所述漏区的部分之上设置场区辅助电极，在开态时，所述场区辅助电极被偏置与所述漏区所偏置的电压方向相同的电压。To achieve the above or other objects, the present invention provides an LDMOS including a source region, a gate dielectric layer, a drain region, a drift region disposed between the drain region and the gate dielectric layer, and a field oxide layer disposed over the drift region. a gate electrode substantially disposed on the gate dielectric layer, wherein a field auxiliary electrode is disposed on a portion of the field oxide layer relatively close to the drain region, and in the on state, the field region assists The electrode is biased to the same voltage as the voltage biased by the drain region.
按照本发明一实施例的LDMOS，其中，所述场区辅助电极与所述漏区偏置相同大小的电压。In accordance with an embodiment of the present invention, an LDMOS, wherein the field auxiliary electrode and the drain region are biased by a voltage of the same magnitude.
在之前所述任意实施例的LDMOS中，优选地，所述场区辅助电极与所述漏区之间的距离为所述场氧化层的长度的5%至 25%。In the LDMOS of any of the foregoing embodiments, preferably, the distance between the field auxiliary electrode and the drain region is 5% of the length of the field oxide layer to 25%.
在之前所述任意实施例的LDMOS中，优选地，所述场区辅助电极与所述栅极均为多晶硅电极，所述场区辅助电极和所述栅极同步地构图形成。In the LDMOS of any of the foregoing embodiments, preferably, the field auxiliary electrode and the gate are both polysilicon electrodes, and the field auxiliary electrode and the gate are patterned in synchronization.
在之前所述任意实施例的LDMOS中，优选地，所述漂移区与所述漏区同类型掺杂，并且，所述漂移区低于所述漏区掺杂浓度。In the LDMOS of any of the foregoing embodiments, preferably, the drift region is doped the same type as the drain region, and the drift region is lower than the drain region doping concentration.
优选地，所述漂移区的掺杂浓度范围为1×1015/cm3至1×1018/cm3。 Preferably, the drift region has a doping concentration ranging from 1 × 10 15 /cm 3 to 1 × 10 18 /cm 3 .
优选地，所述漏区的掺杂浓度范围为1×1018/cm3至1×1022/cm3。Preferably, the doping concentration of the drain region ranges from 1 × 10 18 /cm 3 to 1 × 10 22 /cm 3 .
在之前所述任意实施例的LDMOS中，优选地，所述场区辅助电极以一段或多段的形式设置于所述场氧化层之上。In the LDMOS of any of the preceding embodiments, preferably, the field auxiliary electrode is disposed over the field oxide layer in one or more segments.
按照本发明又一实施例的LDMOS，其中，所述场区辅助电极与所述漏区上的漏极分离地设置。According to still another embodiment of the present invention, an LDMOS, wherein the field auxiliary electrode is disposed separately from a drain on the drain region.
按照本发明还一实施例的LDMOS，其中，所述场区辅助电极与所述漏区上的漏极一体化地设置。According to still another embodiment of the present invention, in the LDMOS, the field auxiliary electrode is integrally provided with a drain on the drain region.
优选地，所述场区辅助电极与所述漏极为金属或金属硅化物材料制成。Preferably, the field auxiliary electrode and the drain are made of a metal or metal silicide material.
按照本发明再一实施例的LDMOS，其中，所述LDMOS为N沟道LDMOS，所述电压方向为正向。According to still another embodiment of the present invention, the LDMOS is an N-channel LDMOS, and the voltage direction is a positive direction.
本发明的技术效果是，通过在场氧化层之上设置场区辅助电极，其在开态下偏置与漏区所偏置电压方向相同的电压，从而可以使场区辅助电极的大致下方所对应的漂移区区域的杂质浓度增加，在Vds增大时，该区域阻止耗尽层向高掺杂的漏区边界扩展，能降低漏区与漂移区交接处的电场，优化电场分布，避免碰撞电离发生，提高崩溃电压，并从而提高LDMOS的工作电压。The technical effect of the present invention is that by providing a field auxiliary electrode on the field oxide layer, it biases the same voltage as the bias voltage in the open state in the on state, so that the field area auxiliary electrode can be substantially below The impurity concentration in the drift region increases, and when the Vds increases, the region prevents the depletion layer from expanding toward the highly doped drain region boundary, can reduce the electric field at the intersection of the drain region and the drift region, optimize the electric field distribution, and avoid collision ionization. Occurs to increase the breakdown voltage and thereby increase the operating voltage of the LDMOS.
【附图说明】[Description of the Drawings]
从结合附图的以下详细说明中，将会使本发明的上述和其他目的及优点更加完全清楚，其中，相同或相似的要素采用相同的标号表示。The above and other objects and advantages of the present invention will be more fully understood from the aspects of the appended claims.
图1是传统LDMOS的基本截面结构示意图。1 is a schematic diagram showing the basic cross-sectional structure of a conventional LDMOS.
图2是按照本发明一实施例提供的LDMOS的基本截面结构示意图。2 is a schematic cross-sectional structural view of an LDMOS according to an embodiment of the invention.
图3是LDMOS的转移特性曲线示意图。Figure 3 is a schematic diagram of the transfer characteristic curve of the LDMOS.
图4是按照本发明又一实施例提供的LDMOS的基本截面结构示意图。4 is a schematic cross-sectional structural view of an LDMOS according to still another embodiment of the present invention.
【具体实施方式】 【detailed description】
下面介绍的是本发明的多个可能实施例中的一些，旨在提供对本发明的基本了解，并不旨在确认本发明的关键或决定性的要素或限定所要保护的范围。容易理解，根据本发明的技术方案，在不变更本发明的实质精神下，本领域的一般技术人员可以提出可相互替换的其他实现方式。因此，以下具体实施方式以及附图仅是对本发明的技术方案的示例性说明，而不应当视为本发明的全部或者视为对本发明技术方案的限定或限制。The following is a description of some of the various possible embodiments of the invention, which are intended to provide a basic understanding of the invention and are not intended to identify key or critical elements of the invention or the scope of the invention. It is to be understood that, in accordance with the technical aspects of the present invention, those skilled in the art can suggest other alternatives that are interchangeable without departing from the spirit of the invention. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the embodiments of the invention, and are not intended to
在附图中，为了清楚起见，夸大了层和区域的厚度，并且，由于刻蚀引起的圆润等形状特征未在附图中示意出。In the drawings, the thickness of layers and regions are exaggerated for clarity, and the shape features such as rounding due to etching are not illustrated in the drawings.
本文中，“上”、“下”、“左”、“右”的方向性术语是相对于附图中的LDMOS的方位来定义的（例如，左右方向是指LDMOS的沟道方向、其平行于衬底表面，上下方向垂直于衬底表面）。并且，应当理解到，这些方向性术语是相对的概念，它们用于相对于的描述和澄清，其可以根据LDMOS所放置的方位的变化而相应地发生变化。Herein, the directional terms of "upper", "lower", "left", and "right" are defined with respect to the orientation of the LDMOS in the drawing (for example, the left-right direction refers to the channel direction of the LDMOS, which is parallel On the surface of the substrate, the up and down direction is perpendicular to the surface of the substrate). Also, it should be understood that these directional terms are relative concepts that are used in relation to the description and clarification, which may vary accordingly depending on the orientation in which the LDMOS is placed.
图2所示为按照本发明一实施例提供的LDMOS的基本截面结构示意图。在该实施例中，LDMOS 20为N沟道LDMOS，以下结合图2对该实施例的LDMOS结构进行具体说明。FIG. 2 is a schematic cross-sectional view showing the basic structure of an LDMOS according to an embodiment of the invention. In this embodiment, LDMOS 20 is an N-channel LDMOS, and the LDMOS structure of this embodiment will be specifically described below with reference to FIG.
如图2所示，LDMOS形成于衬底200上，对于N沟道LDMOS，衬底200为P型掺杂，其具体掺杂浓度不受本发明限制性的。衬底200具体地可以通过外延生长形成、也可以为晶圆衬底。在衬底200中形成有源区210和漏区270，在该实例中，源区210和漏区270通过对衬底200构图N型掺杂形成N+阱来形成，源区210和漏区270的掺杂浓度可以相同，因此，二者可以同步地掺杂形成。源区210和漏区270之上可以分别形成源极（图中未示出）和漏极271；源极用于引出源区210，二者被定义为LDMOS的源端；漏极271用于引出漏区270，二者被定义为LDMOS的漏端。在优选实例中，源区210和漏区270的N型掺杂浓度范围可以为1×1018/cm3至1×1022/cm3，例如掺杂浓度设置为1×1020/cm3。As shown in FIG. 2, an LDMOS is formed on a substrate 200. For an N-channel LDMOS, the substrate 200 is P-type doped, and its specific doping concentration is not limited by the present invention. The substrate 200 may be specifically formed by epitaxial growth or may be a wafer substrate. An active region 210 and a drain region 270 are formed in the substrate 200. In this example, the source region 210 and the drain region 270 are formed by patterning the substrate 200 to N-type doping to form an N+ well, the source region 210 and the drain region 270. The doping concentration can be the same, so that the two can be formed by simultaneous doping. A source (not shown) and a drain 271 may be formed over the source region 210 and the drain region 270, respectively; a source for extracting the source region 210, which are defined as source terminals of the LDMOS; and a drain 271 for A drain region 270 is drawn, which is defined as the drain terminal of the LDMOS. In a preferred embodiment, the N-type doping concentration of the source region 210 and the drain region 270 may range from 1 × 10 18 /cm 3 to 1 × 10 22 /cm 3 , for example, the doping concentration is set to 1 × 10 20 /cm 3 .
在衬底200上，形成了P阱的体区220，同时还形成了漂移区250。在优选实例中，体区220的掺杂浓度范围可以为1×1015/cm3至1×1018/cm3，例如掺杂浓度设置为？1e17？。对于N沟道LDMOS，漂移区250为N型掺杂（如图所示N阱），其掺杂浓度一般地低于漏区270的掺杂浓度，在优选实施例中，漂移区250掺杂浓度范围可以为1×1015/cm3至1×1018/cm3，例如掺杂浓度设置为5×1016/cm3。On the substrate 200, a body region 220 of a P well is formed while a drift region 250 is also formed. In a preferred embodiment, the doping concentration of the body region 220 may range from 1 x 10 15 /cm 3 to 1 x 10 18 /cm 3 , for example, the doping concentration is set to ? 1e17? . For an N-channel LDMOS, the drift region 250 is N-doped (N-well as shown), and its doping concentration is generally lower than the doping concentration of the drain region 270. In a preferred embodiment, the drift region 250 is doped. The concentration may range from 1 × 10 15 /cm 3 to 1 × 10 18 /cm 3 , for example, the doping concentration is set to 5 × 10 16 /cm 3 .
继续如图2所示，在衬底200表面、源端和漏端之间形成栅介质层230，具体地，其可以通过构图氧化形成，当然，也可以通过薄膜沉积等方法构图形成。在漂移区250上，采用LOCOS工艺构图氧化形成场氧化层260。在栅介质层230上构图形成栅极240，如图2示意，栅极240可以覆盖靠近栅介质层230的部分场氧化层260。栅极240具体材料不受本发明限制，例如，其可以为低电阻率的多晶硅构图形成。Continuing with the formation of the gate dielectric layer 230 between the surface of the substrate 200, the source and the drain, as shown in Fig. 2, specifically, it may be formed by patterning oxidation, and of course, may be patterned by thin film deposition or the like. On the drift region 250, the field oxide layer 260 is formed by patterning oxidation using a LOCOS process. A gate 240 is patterned on the gate dielectric layer 230. As illustrated in FIG. 2, the gate 240 can cover a portion of the field oxide layer 260 adjacent to the gate dielectric layer 230. The particular material of the gate 240 is not limited by the present invention, for example, it can be formed by low resistivity polysilicon patterning.
继续如图2所示，在场氧化层260上，构图形成有场区辅助电极280，场区辅助电极280相对靠近漏区270设置，需要理解的是，场区辅助电极280的位置相对于场氧化层260两旁的栅介质层230和漏区270来定义的，在本发明中，“相对靠近漏区270”可以理解为场区辅助电极280与漏区270的距离小于或等于场区辅助电极280与场氧化层260的距离，例如，场区辅助电极280置于场氧化层260的中心线261的右边（即漏区一旁）；场区辅助电极280可以选择低电阻率的多晶硅构图形成。Continuing, as shown in FIG. 2, on the field oxide layer 260, a field auxiliary electrode 280 is patterned, and the field auxiliary electrode 280 is disposed relatively close to the drain region 270. It is to be understood that the position of the field auxiliary electrode 280 is relative to field oxidation. Defined by the gate dielectric layer 230 and the drain region 270 on both sides of the layer 260, in the present invention, "relatively close to the drain region 270" can be understood as the distance between the field region auxiliary electrode 280 and the drain region 270 is less than or equal to the field region auxiliary electrode 280. The distance from the field oxide layer 260, for example, the field auxiliary electrode 280 is placed to the right of the centerline 261 of the field oxide layer 260 (i.e., alongside the drain region); the field region auxiliary electrode 280 can be selected to form a low resistivity polysilicon pattern.
对于N沟道LDMOS20，在其处于开态时，Vds大于零，也即漏端偏置正向电压、源端偏置在0伏；同时，将场区辅助电极280偏置正向电压时（与漏区偏置的电压方向相同，均为正），场区辅助电极280大致下方所对应的漂移区将被增强，N型杂质浓度将大大上升（电子浓度增加），因此，场区辅助电极280下方区域的杂质浓度相对较高。随着Vds的增大，在漂移区的耗尽层向漏区270靠近的过程中，当耗尽层耗尽到该下方区域时，该区域的电力线将更加密集，电场相对更高，从而能导致耗尽层进一步向漏区280耗尽，也即耗尽层很难向高掺杂的漏区280边界扩展。因此，能降低漏区280与漂移区250交接处的电场，避免其因Vds的增大而导致大电场条件下的碰撞电离发生，开态下的崩溃电压得到大大提高。For the N-channel LDMOS 20, when it is in an on state, Vds is greater than zero, that is, the drain terminal is biased to the forward voltage, and the source terminal is biased at 0 volts; meanwhile, when the field region auxiliary electrode 280 is biased to the forward voltage ( The same as the voltage direction of the drain region bias, both positive), the drift region corresponding to the lower portion of the field auxiliary electrode 280 will be enhanced, and the N-type impurity concentration will greatly increase (the electron concentration increases), therefore, the field auxiliary electrode The impurity concentration in the lower region of 280 is relatively high. As Vds increases, during the process of the depletion layer of the drift region approaching the drain region 270, when the depletion layer is depleted to the lower region, the power line of the region will be denser and the electric field is relatively higher, thereby enabling The depletion layer is further depleted to the drain region 280, that is, the depletion layer is difficult to expand toward the highly doped drain region 280 boundary. Therefore, the electric field at the intersection of the drain region 280 and the drift region 250 can be reduced, and the collision ionization under the large electric field condition is prevented from being caused by the increase of the Vds, and the breakdown voltage in the open state is greatly improved.
在一优选实例中，场区辅助电极280偏置与漏端相同方向且相同大小的电压，例如，漏极270和场区辅助电极280连接在同一电压源上，这样减少相应电源的设计，有利于减少LDMOS的外围电路。In a preferred embodiment, the field auxiliary electrode 280 biases the same direction and the same magnitude of voltage as the drain terminal. For example, the drain 270 and the field auxiliary electrode 280 are connected to the same voltage source, thus reducing the design of the corresponding power supply. It helps to reduce the peripheral circuits of LDMOS.
图3所示为LDMOS的输出特性曲线示意图。其中，曲线11为图1所示实施例LDMOS的转移特性曲线，曲线21为图2所示实施例LDMOS的转移特性曲线（场区辅助电极280与漏端偏置相同电压）。对比曲线11和21，对于曲线11，当Vds达到35伏左右时，Ids开始快速上升，表明在漏区180与漂移区150交接处开始发生碰撞电离；对于曲线21， Vds达到41伏左右时，Ids才开始快速上升，表明在漏区280与漂移区250交接处开始发生碰撞电离。因此，开态下的崩溃电压得到大大提高。在崩溃电压得到提高的情况下，LDMOS20相对LDMOS10的工作电压提高，例如，LDMOS20可以在Vds=38V下工作。Figure 3 shows a schematic diagram of the output characteristics of the LDMOS. The curve 11 is the transfer characteristic curve of the LDMOS of the embodiment shown in FIG. 1, and the curve 21 is the transfer characteristic curve of the LDMOS of the embodiment shown in FIG. 2 (the field auxiliary electrode 280 is biased with the same voltage as the drain terminal). Comparing curves 11 and 21, for curve 11, when Vds reaches about 35 volts, Ids starts to rise rapidly, indicating that impact ionization begins to occur at the intersection of drain region 180 and drift region 150; for curve 21, When the Vds reached about 41 volts, the Ids began to rise rapidly, indicating that impact ionization began to occur at the intersection of the drain region 280 and the drift region 250. Therefore, the breakdown voltage in the on state is greatly improved. In the case where the breakdown voltage is increased, the operating voltage of the LDMOS 20 with respect to the LDMOS 10 is increased, for example, the LDMOS 20 can operate at Vds = 38V.
继续如图2所示，场区辅助电极280相对靠近漏区270设置时，其相对漏区270的距离优选地为场氧化层260的长度（沟道方向上的长度）的5%至25%，例如，10%。场区辅助电极280的面积相对场氧化层260的面积较小，其面积大小范围为场氧化层260的面积的5%至25？%，例如，10%。场区辅助电极280为多晶硅时，其可以为P型掺杂也可以为N型掺杂，其电阻率较低，具体地，可以与多晶硅的栅极240同步地构图形成（但是，二者不能连接在一起），场区辅助电极280的具体厚度以及掺杂浓度不受本发明实施例限制。场区辅助电极280偏置的电压也不受以上实施例限制，例如，其还可以偏置其他的正向电压，例如+10V等。Continuing as shown in FIG. 2, when the field auxiliary electrode 280 is disposed relatively close to the drain region 270, its distance from the drain region 270 is preferably 5% to 25% of the length of the field oxide layer 260 (the length in the channel direction). , for example, 10%. The area of the field auxiliary electrode 280 is smaller than the area of the field oxide layer 260, and the area size ranges from 5% to 25 of the area of the field oxide layer 260. %, for example, 10%. When the field auxiliary electrode 280 is polysilicon, it may be P-type doped or N-type doped, and its resistivity is low. Specifically, it may be patterned in synchronization with the gate 240 of the polysilicon (however, the two cannot Connected together), the specific thickness of the field auxiliary electrode 280 and the doping concentration are not limited by the embodiments of the present invention. The bias voltage of the field auxiliary electrode 280 is also not limited by the above embodiments, for example, it can also bias other forward voltages, such as +10V.
在其它实施例中，场区辅助电极280可以多段地设置（图2中一段设置），每段场区辅助电极280均相对靠经漏区270设置。每段场区辅助电极280的作用原理与以上实施例中的场区辅助电极280的作用原理基本一致。In other embodiments, the field auxiliary electrode 280 can be disposed in multiple stages (one stage setting in FIG. 2), and each of the field auxiliary electrodes 280 is disposed opposite to the drained area 270. The working principle of the auxiliary electrode 280 of each segment is substantially the same as that of the field auxiliary electrode 280 in the above embodiment.
图4所示为按照本发明又一实施例提供的LDMOS的基本截面结构示意图。相比于图2所示实施例，其主要区别在于，漏极271向场氧化层260之上延伸，从而在场氧化层260之上的部分电极被定义为场区辅助电极380，因此场区辅助电极380相对于漏极271一体化地设置，这样，容易使LDMOS在开态时、场区辅助电极与漏极或漏区偏置相同电压，结构相对更简单，也更容易制备。在该实施例中，场区辅助电极380与漏极271采用相同的材料，例如，金属或金属硅化物（salicide）电极。FIG. 4 is a schematic cross-sectional view showing the basic structure of an LDMOS according to another embodiment of the present invention. Compared with the embodiment shown in FIG. 2, the main difference is that the drain electrode 271 extends over the field oxide layer 260, so that a part of the electrode above the field oxide layer 260 is defined as the field area auxiliary electrode 380, so the field area assists The electrode 380 is integrally provided with respect to the drain 271. Thus, it is easy to bias the LDMOS in the on state, the field auxiliary electrode and the drain or drain region are biased by the same voltage, and the structure is relatively simpler and easier to prepare. In this embodiment, the field auxiliary electrode 380 and the drain 271 are made of the same material, for example, a metal or metal salicide electrode.
以上实施例所揭示的LDMOS均为N沟道LDMOS，本领域技术人员根据以上教导提出结构相似的P沟道LDMOS，在此不再一一示例；需要理解的是，P沟道LDMOS的场区辅助电极与漏区在开态是偏置负向的电压以提高场区辅助电极之下大致对应的漂移区区域的杂质浓度。The LDMOS disclosed in the above embodiments are all N-channel LDMOS, and those skilled in the art propose a P-channel LDMOS with similar structure according to the above teachings, which will not be exemplified herein; it should be understood that the field of the P-channel LDMOS The auxiliary electrode and the drain region are biased in a negative direction in an open state to increase the impurity concentration of the region corresponding to the drift region substantially below the field auxiliary electrode.
以上例子主要说明了本发明的LDMOS。尽管只对其中一些本发明的实施方式进行了描述，但是本领域普通技术人员应当了解，本发明可以在不偏离其主旨与范围内以许多其他的形式实施。因此，所展示的例子与实施方式被视为示意性的而非限制性的，在不脱离如所附各权利要求所定义的本发明精神及范围的情况下，本发明可能涵盖各种的修改与替换。The above examples mainly illustrate the LDMOS of the present invention. Although only a few of the embodiments of the present invention have been described, it will be understood by those skilled in the art that the invention may be practiced in many other forms without departing from the spirit and scope of the invention. Accordingly, the present invention is to be construed as illustrative and not restrictive, and the invention may cover various modifications without departing from the spirit and scope of the invention as defined by the appended claims With replacement.

Claims (13)

  1. 一种横向双扩散金属氧化物半导体场效应晶体管，包括源区、栅介质层、漏区、设置在漏区和栅介质层之间的漂移区、设置在漂移区之上的场氧化层、基本设置在栅介质层之上的栅极，其特征在于，在所述场氧化层的相对靠近所述漏区的部分之上设置场区辅助电极。A lateral double-diffused metal oxide semiconductor field effect transistor comprising a source region, a gate dielectric layer, a drain region, a drift region disposed between the drain region and the gate dielectric layer, a field oxide layer disposed above the drift region, and a basic A gate electrode disposed over the gate dielectric layer is characterized in that a field region auxiliary electrode is disposed over a portion of the field oxide layer relatively close to the drain region.
  2. 如权利要求1所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，在开态时，所述场区辅助电极被偏置与所述漏区所偏置的电压方向相同的电压。The lateral double-diffused metal oxide semiconductor field effect transistor of claim 1 wherein, in the on state, said field auxiliary electrode is biased by a voltage that is the same as a voltage biased by said drain region .
  3. 如权利要求2所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区辅助电极与所述漏区偏置相同大小的电压。The lateral double-diffused metal oxide semiconductor field effect transistor of claim 2 wherein said field auxiliary electrode and said drain region are biased by a voltage of the same magnitude.
  4. 如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区辅助电极与所述漏区之间的距离为所述场氧化层的长度的5%至25%。The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1 or 3, wherein a distance between the field auxiliary electrode and the drain region is 5% of a length of the field oxide layer Up to 25%.
  5. 如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区辅助电极与所述栅极均为多晶硅电极，所述场区辅助电极和所述栅极同步地构图形成。The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1 or 3, wherein said field auxiliary electrode and said gate are both polysilicon electrodes, said field auxiliary electrode and said gate The pattern is formed in a very synchronous manner.
  6. 如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述漂移区与所述漏区同类型掺杂，并且，所述漂移区低于所述漏区掺杂浓度。The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1 or 3, wherein the drift region is doped with the drain region, and the drift region is lower than the drain region Doping concentration.
  7. 如权利要求6所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述漂移区的掺杂浓度范围为1×1015/cm3至1×1018/cm3。The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 6, wherein the drift region has a doping concentration ranging from 1 × 10 15 /cm 3 to 1 × 10 18 /cm 3 .
  8. 如权利要求6所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述漏区的掺杂浓度范围为1×1018/cm3至1×1022/cm3。A lateral double-diffused metal oxide semiconductor field effect transistor according to claim 6, wherein said drain region has a doping concentration ranging from 1 × 10 18 /cm 3 to 1 × 10 22 /cm 3 .
  9. 如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区辅助电极以一段或多段的形式设置于所述场氧化层之上。The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1 or 3, wherein the field auxiliary electrode is disposed on the field oxide layer in one or more stages.
  10. 如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区辅助电极与所述漏区上的漏极分离地设置。The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1 or 3, wherein the field auxiliary electrode is provided separately from the drain on the drain region.
  11. 如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区辅助电极与所述漏区上的漏极一体化地设置。The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1 or 3, wherein the field auxiliary electrode is provided integrally with the drain on the drain region.
  12. 如权利要求11所述的横向双扩散金属氧化物半导体场效应晶体管，其特征在于，所述场区辅助电极与所述漏极为金属或金属硅化物材料制成。A lateral double-diffused metal oxide semiconductor field effect transistor according to claim 11, wherein said field auxiliary electrode and said drain are made of a metal or metal silicide material.
  13. 如权利要求1或3所述的横向双扩散金属氧化物半导体场效应晶体管，所述横向双扩散金属氧化物半导体场效应晶体管为N沟道横向双扩散金属氧化物半导体场效应晶体管，所述电压方向为正向。The lateral double-diffused metal oxide semiconductor field effect transistor according to claim 1 or 3, wherein said lateral double-diffused metal oxide semiconductor field effect transistor is an N-channel lateral double-diffused metal oxide semiconductor field effect transistor, said voltage The direction is positive.
PCT/CN2012/086518 2011-12-30 2012-12-13 Lateral double diffused metal oxide semiconductor field effect transistor WO2013097608A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1632931A (en) * 2004-12-23 2005-06-29 上海华虹（集团）有限公司 Technique for improving voltage resistance of reduced surface field type LDMOS device
CN201910425U (en) * 2010-12-30 2011-07-27 厦门烁芯光电技术有限公司 LDMOS (laterally diffused metal oxide semiconductor) device suitable for high and low-voltage monolithic integration
CN102157518A (en) * 2011-01-07 2011-08-17 北方工业大学 Novel double-surge protection device with single-chip integration and manufacturing method thereof
CN102176469A (en) * 2011-03-10 2011-09-07 杭州电子科技大学 SOI (Silicon on Insulator) nLDMOS (n-Channel Lateral Diffused Metal Oxide Semiconductor) device unit with p buried layer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN2743978Y (en) * 2004-06-24 2005-11-30 东南大学 Transverse high-voltage N type metal oxide semiconductor transistor with multi-potential field polar plate
KR100628250B1 (en) * 2005-09-28 2006-09-27 동부일렉트로닉스 주식회사 Semiconductor device for using power and method for fabricating the same
CN101969074B (en) * 2010-10-28 2012-07-04 电子科技大学 High voltage lateral double diffused MOSFET element
CN102169903B (en) * 2011-03-22 2013-05-01 成都芯源系统有限公司 Ldmos device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1632931A (en) * 2004-12-23 2005-06-29 上海华虹（集团）有限公司 Technique for improving voltage resistance of reduced surface field type LDMOS device
CN201910425U (en) * 2010-12-30 2011-07-27 厦门烁芯光电技术有限公司 LDMOS (laterally diffused metal oxide semiconductor) device suitable for high and low-voltage monolithic integration
CN102157518A (en) * 2011-01-07 2011-08-17 北方工业大学 Novel double-surge protection device with single-chip integration and manufacturing method thereof
CN102176469A (en) * 2011-03-10 2011-09-07 杭州电子科技大学 SOI (Silicon on Insulator) nLDMOS (n-Channel Lateral Diffused Metal Oxide Semiconductor) device unit with p buried layer

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