WO2023224332A1 - Tunneling field-effect transistor having fin-shaped semiconductor pattern and drain region having concave central portion - Google Patents

Abstract

Provided is a tunneling field-effect transistor. The tunneling field-effect transistor is defined by an element isolation film disposed on a substrate, and includes a semiconductor pattern that has a protruding pin-like shape protruding above the upper surface of the element isolation film, and comprises a channel region and a source region, having a first conductivity-type region, and a drain region, having a second conductivity-type region, on respective sides of the channel region. A gate electrode is disposed on the upper surface of the channel region and extends onto a first side wall of the channel region and a second side wall of the channel region, wherein the second side wall is opposite the first side wall. A gate insulating layer is interposed between the channel region and the gate electrode. A source electrode is connected to the source region. A drain electrode is connected to the drain region. The drain region comprises: a first sub-region extending from the first side wall of the channel region and a region adjacent to the first side wall; and a second sub-region extending from the second side wall of the channel region and a region adjacent to the second side wall. The sum of a first width of the first sub-region and a second width of the second sub-region is less than the width of the channel region.

Description

Tunneling field-effect transistor with a fin-shaped semiconductor pattern and a centrally concave drain region

The present invention relates to semiconductor devices, and more particularly to tunneling field effect transistors.

Unlike general field effect transistors, tunneling field effect transistors operate using tunneling between source-channel-drain without operation such as depletion or inversion of the channel region, so they have a low subthreshold swing. It is known to be suitable for low-power devices because it can implement .

Taking an n-type transistor among tunneling field effect transistors as an example, when a positive voltage higher than the threshold voltage is applied to the gate electrode, the energy band of the channel region goes down, and the valence band of the source region and the channel region The tunneling width between the conduction bands can be reduced. Accordingly, as electrons tunnel from the valence band of the source region to the conduction band of the channel region, current flows between the source region and the drain region, turning the transistor into an on state.

On the other hand, when a negative voltage is applied to the gate electrode, the energy band of the channel region increases, and the tunneling width between the valence band of the channel region and the conduction band of the drain region may decrease. Accordingly, electrons tunnel from the valence band of the channel region to the conduction band of the drain region, allowing current to flow between the source region and the drain region. This is called an ambipolar current, and when a negative voltage is applied to the gate electrode, it can be defined as a leakage current in a circuit where the transistor must remain in the off state, which can cause malfunction and power consumption. .

In order to reduce the power of the device, it is necessary to improve the on-current of the tunneling field effect transistor. However, improving the on-current may result in the off-current, that is, the bidirectional current, increasing simultaneously. Therefore, there is a need for a method that can suppress the off-current while improving the on-current of the tunneling field effect transistor.

The problem to be solved by the present invention is to provide a tunneling field effect transistor that can suppress off-current while improving on-current without increasing the surface area occupied by one transistor.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the above technical problem, one aspect of the present invention provides a tunneling field effect transistor. The tunneling field effect transistor is defined by a device isolation film disposed on a substrate and has a fin-shape protruding above the upper surface of the device isolation film, a source region having a channel region and a first conductive region on both sides thereof, and a second channel region. It includes semiconductor patterns each having drain regions having two conductive regions. A gate electrode is disposed on the upper surface of the channel region and extends onto a first sidewall of the channel region and a second sidewall of the channel region facing the first sidewall of the channel region. A gate insulating film is interposed between the channel region and the gate electrode. A source electrode is connected to the source region. A drain electrode is connected to the drain region. The drain region has a first sub-region extending from a first sidewall of the channel region and an area adjacent thereto and a second sub-region extending from a second sidewall of the channel region and an area adjacent thereto, and the first sub-region The sum of the first width of and the second width of the second sub-region is smaller than the width of the channel region.

The first sidewall of the first sub-region may be located in the same plane as the first sidewall of the channel region, and the second sidewall of the second sub-region may be located in the same plane as the second sidewall of the channel region.

An upper surface of at least one of the first sub-region and the second sub-region may be located in the same plane as the upper surface of the channel region. In another example, the height of at least one of the first sub-region and the second sub-region may be lower than the height of the channel region.

The first conductivity type region may be a charge plasma region of the first conductivity type induced by the source electrode. The source electrode may be a metal electrode having a large work function compared to the work function of the source region, the charge plasma of the first conductivity type may be a hole plasma, and the first conductivity type region may be a p-type region.

The second conductivity type region may be a charge plasma region of the second conductivity type induced by the drain electrode. The drain electrode may be a metal electrode having a small work function compared to the work function of the drain region, the charge plasma of the second conductivity type may be an electron plasma, and the second conductivity type region may be an n-type drain region.

As described above, according to an embodiment of the present invention, it is possible to suppress the generation of reverse current or ambipolar current while improving on-state current without increasing the planar area occupied by one transistor. As a result, it is possible to improve on-current and suppress leakage current without reducing device integration.

However, the effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1A and 1B are perspective views of a tunneling field effect transistor according to a first embodiment.

FIG. 2 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 1A.

Figure 3 is a cross-sectional view taken along line II' of Figure 1b.

FIG. 4A is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the first embodiment viewed from the source region, and FIG. 4B is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the first embodiment from the drain region side. This is a cross-sectional view.

5A and 5B are perspective views of a tunneling field effect transistor according to a second embodiment.

FIG. 6 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 5A.

Figure 7 is a cross-sectional view taken along line II' of Figure 5b.

FIG. 8A is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the second embodiment as seen from the source region, and FIG. 8B is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the second embodiment from the drain region side. This is a cross-sectional view.

Hereinafter, in order to explain the present invention in more detail, preferred embodiments according to the present invention will be described in more detail with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the drawings, where a layer is referred to as being “on” another layer or substrate, it may be formed directly on the other layer or substrate, or there may be a third layer interposed between them. In the present embodiments, “first,” “second,” or “third” are not intended to impose any limitation on the components, but should be understood as terms for distinguishing the components.

1A and 1B are perspective views of a tunneling field effect transistor according to a first embodiment. Here, FIG. 1A is a perspective view excluding the source electrode and drain electrode shown in FIG. 1B. FIG. 2 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 1A, and FIG. 3 is a cross-sectional view taken along the cutting line II' of FIG. 1B.

Referring to FIGS. 1A, 1B, 2, and 3, a substrate 100 may be provided. The substrate may be a semiconductor substrate, a metal substrate, a glass substrate, or a flexible substrate. For example, the flexible substrate may be a polymer substrate, such as a polyethylene terephthalate (PET) or polyimide (PI) substrate. Elements for operation circuits, etc. may be formed on the substrate 100. Additionally, a protective layer 105 such as an insulating film may be formed to cover the substrate or the device. The protective layer 105 may be a silicon oxide film, a silicon nitride film, or a composite layer thereof.

A base semiconductor layer can be formed on the protective layer 105. The base semiconductor layer may be a silicon layer. As an example, it may be a single crystalline silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer. Specifically, it may be an epitaxially grown single crystal silicon layer. In one example, the substrate 100, the protective layer 105, and the base semiconductor layer may be a silicon on insulator (SOI) substrate.

The semiconductor pattern 120 may be formed on the lower semiconductor layer 110, which is the lower region of the base semiconductor layer, by patterning the upper region of the base semiconductor layer. After stacking a device isolation film 115 on the lower semiconductor layer 110 on which the semiconductor pattern 120 is formed, the stacked device isolation film 115 is etched to form the device isolation film 115. It can be made to protrude upward from the upper surface and have a pin-shape.

At this time, the fin-shaped semiconductor pattern 120 includes a channel region 125 and a source region 123 and a drain region 121 on both sides of the channel region 125, respectively.

The central portion of the drain region 121 in contact with the channel region 125 may be formed to be concave compared to the outer portion. Specifically, the drain region 121 faces the first sub-region 121a extending from an area adjacent to the first sidewall 125x of the channel region 125 and the first sidewall 125x of the channel region 125. The beam may have a second sub-region 121b extending from an area adjacent to the second side wall 125y and a third sub-region 121c connecting the first sub-region 121a and the second sub-region 121b. . Specifically, the first sub-region 121a may have a first sidewall 121x located in the same plane as the first sidewall 125x of the channel region 125 and a first width W _1x . The second sub-region 121b may have a second side wall 121y located in the same plane as the second side wall 125y of the channel region 125 and a second width W _1y . The sum of the first width (W _1x ) of the first sub-region 121a and the second width (W 1y ) of the second sub-region _121b is the width of the channel region 125 or the source region 123 ( It may be smaller than W ₂ ). As a result, a concave or recessed area may be located between the first sub-area 121a and the second sub-area 121b, and the channel area 125 may be exposed within the concave area. Here, the upper surface 121z of the drain region 121, that is, the upper surface of the first sub-region 121a and the second sub-region 121b, is the same plane as the upper surface 125z of the channel region 125. It can be located within.

Afterwards, a gate insulating film 130 may be formed on the fin-shaped semiconductor pattern 120. The gate insulating film 130 may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or a composite film thereof. The gate insulating layer 130 may also be formed on the top surface and sidewalls of the fin-shaped semiconductor pattern 120.

By forming the gate electrode 140 on the gate insulating film 130, the gate insulating film may be interposed between the channel region 125 and the gate electrode 140. The gate electrode 140 is formed on a wide portion of the fin-shaped semiconductor pattern 120, that is, on the upper surface 125z of the channel region 125 and the first and second sidewalls 125x and 125y. can be formed in The gate electrode 140 may be formed using Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy thereof.

A source electrode 160 connected to the source region 123 can be formed. Specifically, the source electrode 160 may be formed on the source region 123, which is a wide portion of the fin-shaped semiconductor pattern 120 adjacent to the gate electrode 140. The source electrode 160 may be a metal electrode having a large work function compared to the work function of the semiconductor pattern 120 adjacent thereto, that is, the source region 123. When the source region 123 is silicon, the source electrode 160 is made of nickel (Ni), iridium (Ir), palladium (Pd), or platinum (with a work function greater than silicon, for example, 5 eV or more). Pt), or a combination thereof. In this way, due to the difference in work function between the source region 123 and the source electrode 160, electrons in the source region 123 can move to the source electrode 160, ) A charge plasma of the first conductivity type, specifically, a hole plasma, may be formed in the source region 123 adjacent to the source region 123 to induce a p-type region, that is, a first conductivity type region 123p.

Specifically, the drain region 121 may form a drain electrode 150 connected to the first sub-region 121a, the second sub-region 121b, and the third sub-region 121c. The drain electrode 150 may be a metal electrode having a small work function compared to the work function of the semiconductor pattern 120, that is, the drain region 121. When the drain region 121 is a silicon layer, the drain electrode 150 is made of hafnium (Hf) or indium (In), which has a work function smaller than that of silicon, for example, a work function of 4.5 eV, specifically, a work function of 4.2 eV or less. ), zirconium (Zr), thallium (Tl), tantalum (Ta), titanium (Ti), aluminum (Al), or a combination thereof. In this way, due to the difference in work function between the drain region 121 and the drain electrode 150, electrons can move from the drain electrode 150 to the drain region 121, so that the drain electrode 150 ) A charge plasma of a second conductivity type, specifically, an electron plasma, may be formed in the drain region 121 adjacent to the n-type region, that is, a second conductivity type region 121p. The channel region 125 may be exposed on the sidewall of the concave area, and the device isolation layer 115 may be exposed on the bottom of the concave area.

Specifically, the channel region 125 between the first conductive region 123p and the second conductive region 121p may be an intrinsic semiconductor region. In this way, the first conductive region 123p and the second conductive region 121p can be induced into the conductive region through charge plasma generation without impurity doping using ion implantation or the like. Accordingly, the manufacturing process is simpler compared to impurity doping such as ion implantation, and the production of defects can be suppressed. However, the present invention is not limited to this, and the first conductivity type region 123p and the second conductivity type region 121p may be formed by impurity doping using ion implantation, etc. rather than charge plasma generation. Above, the first conductive region (123p) is described as p-type and the second conductive region (121p) as n-type. However, this is not limited to this, and the first conductive region (123p) is described as n-type and the second conductive region (121p) is described as n-type. The conductive region 121p may be formed as a p-type.

The gate insulating film 130 is formed between the semiconductor pattern 120 and the gate electrode 140, and may extend between the source electrode 160 and the drain electrode 150 and the semiconductor pattern 120. .

FIG. 4A is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the first embodiment viewed from the source region, and FIG. 4B is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the first embodiment from the drain region side. This is a cross-sectional view.

Referring to FIG. 4A, in general, a tunneling field effect transistor generates an on-current by charge tunneling between the source region and the channel region. In the fin-shaped semiconductor pattern 120 according to the present embodiment, the area where the channel region 125 overlaps the gate electrode 140 is not only the upper surface 125z of the channel region 125, but also the side walls 125x, As it extends to 125y), the effective channel width (SW _eff ) where the on-current is generated at the portion of the channel region 125 that is in contact with the source region 123 increases, so the on-current may increase.

Referring to FIG. 4B, in general, a tunneling field effect transistor generates an off-current by charge tunneling between the drain region and the channel region. In the device according to this embodiment, the drain region 121 includes a first sub-region 121a extending from an area adjacent to the first sidewall 125x of the channel region 125 and a first sidewall of the channel region 125. It has a second sub-area (121b) extending from an area adjacent to the second side wall (125y) facing (125x), and a concave area or recess is formed between the first sub-area (121a) and the second sub-area (121b). The channel area 125 is exposed within the concave area. As a result, the effective channel width (DW _eff1 ) at which the off-current is generated in the region 125c directly in contact with the first sub-region 121a of the channel region 125 and the second sub-region 125 of the channel region 125 The sum of the effective channel width (DW _eff2 ) where the off-current is generated in the area (125d) directly in contact with the area (121b) is smaller than the effective channel width (SW _eff in FIG. 4b) where the on-current is generated, so the off-current can be suppressed.

Accordingly, in one embodiment of the present invention, the on-current can be improved and the off-current can be suppressed without increasing the planar area occupied by one tunneling field effect transistor.

5A and 5B are perspective views of a tunneling field effect transistor according to a second embodiment. Here, FIG. 5A is a perspective view excluding the source electrode and drain electrode shown in FIG. 5B. FIG. 6 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 5A, and FIG. 7 is a cross-sectional view taken along the cutting line II' of FIG. 5B. FIG. 8A is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the second embodiment as seen from the source region, and FIG. 8B is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the second embodiment from the drain region side. This is a cross-sectional view. The tunneling field effect transistor according to the second embodiment is substantially the same as the first embodiment except as described later. Specifically, the tunneling field effect transistor according to the second embodiment may be changed only in the area of the area where the drain region overlaps the channel region compared to the tunneling field effect transistor according to the first embodiment.

Referring to FIGS. 5A, 5B, 6, 7, 8A, and 8B, like the first embodiment, the drain region 121 has a central portion in contact with the channel region 125 and an outer portion. In comparison, it may be formed concavely. Specifically, the drain region 121 faces the first sub-region 121a extending from an area adjacent to the first sidewall 125x of the channel region 125 and the first sidewall 125x of the channel region 125. The beam may have a second sub-region 121b extending from an area adjacent to the second side wall 125y and a third sub-region 121c connecting the first sub-region 121a and the second sub-region 121b. . Specifically, the first sub-region 121a may have a first sidewall 121x located in the same plane as the first sidewall 125x of the channel region 125 and a first width W _1x . The second sub-region 121b may have a second side wall 121y located in the same plane as the second side wall 125y of the channel region 125 and a second width W _1y . The sum of the first width (W _1x ) of the first sub-region 121a and the second width (W 1y ) of the second sub-region _121b is the width of the channel region 125 or the source region 123 ( It may be smaller than W ₂ ). As a result, a concave or recessed area may be located between the first sub-area 121a and the second sub-area 121b, and the channel area 125 may be exposed within the concave area.

However, unlike the first embodiment, the upper surface 121z of the drain region 121, that is, the upper surface of at least one of the first sub-region 121a and the second sub-region 121b, is connected to the channel region 125. ) can be recessed relative to the upper surface (125z). As a result, the height h ₁ of the drain region 121, that is, the height h 1 of at least one of the first sub-region 121a and the second sub-region _121b is equal to that of the channel region 125. It may be low compared to the height (h ₂ ).

Accordingly, the area of the channel regions 125c and 125d overlapping the drain region 121 may be further reduced. Specifically, the effective channel width (DW _eff1 ) at which the off-current is generated in the region 125c directly in contact with the first sub region 121a of the channel region 125 and the second sub region 125 of the channel region 125. The sum of the effective channel widths (DW _eff2 ) in which the off-current is generated in the area 125d directly in contact with the area 121b is smaller than the effective channel width (SW _eff in FIG. 8B) in which the on-current is generated, so that the off-current can be suppressed.

Above, the present invention has been described in detail with preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical spirit and scope of the present invention. This is possible.

Claims (8)

1. It is defined by a device isolation film disposed on a substrate and has a fin-shape that protrudes upward from the upper surface of the device isolation film, and has a channel region and a source region having a first conductivity type region on both sides thereof and a second conductivity type region. Semiconductor patterns each having a drain region;

   a gate electrode disposed on an upper surface of the channel region and extending on a first sidewall of the channel region and a second sidewall of the channel region facing the first sidewall of the channel region;

   a gate insulating film interposed between the channel region and the gate electrode;

   a source electrode connected to the source region; and

   Provided with a drain electrode connected to the drain region,

   The drain region has a first sub-region extending from a first sidewall of the channel region and an area adjacent thereto and a second sub-region extending from a second sidewall of the channel region and an area adjacent thereto, and the first sub-region A tunneling field effect transistor, wherein the sum of the first width of and the second width of the second sub-region is smaller than the width of the channel region.
2. In claim 1,

   A tunneling field effect transistor wherein the first sidewall of the first sub-region is located in the same plane as the first sidewall of the channel region, and the second sidewall of the second sub-region is located in the same plane as the second sidewall of the channel region. .
3. In claim 1 or claim 2,

   A tunneling field effect transistor wherein an upper surface of at least one of the first sub-region and the second sub-region is located in the same plane as an upper surface of the channel region.
4. In claim 1 or claim 2,

   A tunneling field effect transistor wherein the height of at least one of the first sub-region and the second sub-region is lower than the height of the channel region.
5. In claim 1,

   A tunneling field effect transistor wherein the first conductivity type region is a charge plasma region of the first conductivity type induced by the source electrode.
6. In claim 5,

   The source electrode is a metal electrode having a large work function compared to the work function of the source region, the charge plasma of the first conductivity type is a hole plasma, and the first conductivity type region is a p-type region.
7. In claim 1,

   A tunneling field effect transistor, wherein the second conductivity type region is a charge plasma region of the second conductivity type induced by the drain electrode.
8. In claim 7,

   The drain electrode is a metal electrode having a small work function compared to the work function of the drain region, the charge plasma of the second conductivity type is an electron plasma, and the second conductivity type region is an n-type drain region.

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