WO2023224331A1

WO2023224331A1 - Tunneling field effect transistor having fin-shaped semiconductor pattern

Info

Publication number: WO2023224331A1
Application number: PCT/KR2023/006526
Authority: WO
Inventors: 홍진표
Original assignee: 한양대학교 산학협력단
Priority date: 2022-05-20
Filing date: 2023-05-15
Publication date: 2023-11-23
Also published as: KR20230162386A

Abstract

A tunneling field effect transistor is provided. The tunneling field effect transistor is defined by a device isolation layer disposed on a substrate, and comprises a fin-shaped semiconductor pattern that protrudes farther upward than an upper surface of the device isolation layer. The semiconductor pattern includes a channel region and a source region and a drain region on both sides of the channel region, and the width of the drain region is narrower than the width of the channel region. The source region has a first conductivity type region, and the drain region has a second conductivity type region. A gate electrode is disposed on an upper surface of the channel region, wherein the gate electrode extends on a first sidewall of the channel region and a second sidewall of the channel region facing the first sidewall of the channel region. A gate insulating film is interposed between the channel region and the gate electrode. A source electrode is connected to the source region. A drain electrode is connected to the drain region.

Description

Tunneling field effect transistor with fin-shaped semiconductor pattern

The present invention relates to semiconductor devices, and more particularly to tunneling field effect transistors.

Unlike general field effect transistors, tunneling field effect transistors operate using tunneling between source-channel-drain without operation such as depletion or inversion of the channel region, so they have a low subthreshold swing. It is known to be suitable for low-power devices because it can implement .

Taking an n-type transistor among tunneling field effect transistors as an example, when a positive voltage higher than the threshold voltage is applied to the gate electrode, the energy band of the channel region goes down, and the valence band of the source region and the channel region The tunneling width between the conduction bands can be reduced. Accordingly, as electrons tunnel from the valence band of the source region to the conduction band of the channel region, current flows between the source region and the drain region, turning the transistor into an on state.

On the other hand, when a negative voltage is applied to the gate electrode, the energy band of the channel region increases, and the tunneling width between the valence band of the channel region and the conduction band of the drain region may decrease. Accordingly, electrons tunnel from the valence band of the channel region to the conduction band of the drain region, allowing current to flow between the source region and the drain region. This is called an ambipolar current, and when a negative voltage is applied to the gate electrode, it can be defined as a leakage current in a circuit where the transistor must remain in the off state, which can cause malfunction and power consumption. .

In order to reduce the power of the device, it is necessary to improve the on-current of the tunneling field effect transistor. However, improving the on-current may result in the off-current, that is, the bidirectional current, increasing simultaneously. Therefore, there is a need for a method that can suppress the off-current while improving the on-current of the tunneling field effect transistor.

The problem to be solved by the present invention is to provide a tunneling field effect transistor that can suppress off-current while improving on-current without increasing the surface area occupied by one transistor.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

In order to achieve the above technical problem, one aspect of the present invention provides a tunneling field effect transistor. The tunneling field effect transistor is defined by a device isolation layer disposed on a substrate and includes a fin-shaped semiconductor pattern that protrudes upward from the top surface of the device isolation layer. The semiconductor pattern includes a channel region and a source region and a drain region on both sides thereof, and the width of the drain region is narrow compared to the width of the channel region. The source region has a first conductivity type region, and the drain region has a second conductivity type region. A gate electrode is disposed on the upper surface of the channel region, wherein the gate electrode extends on a first sidewall of the channel region and a second sidewall of the channel region facing the first sidewall of the channel region. A gate insulating film is interposed between the channel region and the gate electrode. A source electrode is connected to the source region. A drain electrode is connected to the drain region.

The first sidewall of the drain region may be located in the same plane as the first sidewall of the channel region.

In one example, the top surface of the drain region may be located in the same plane as the top surface of the channel region. In another example, the height of the drain region may be lower than the height of the channel region. Specifically, the upper surface of the drain region may be recessed compared to the upper surface of the channel region.

The first conductivity type region may be a charge plasma region of the first conductivity type induced by the source electrode. To this end, the source electrode may be a metal electrode whose work function is large compared to the work function of the source region. In this case, the charge plasma of the first conductivity type may be a hole plasma, and the first conductivity type region may be a p-type region.

The second conductivity type region may be a charge plasma region of the second conductivity type induced by the drain electrode. To this end, the drain electrode may be a metal electrode whose work function is small compared to the work function of the drain region. In this case, the charge plasma of the second conductivity type may be an electron plasma, and the second conductivity type region may be an n-type drain region.

As described above, according to an embodiment of the present invention, it is possible to suppress the generation of reverse current or ambipolar current while improving on-state current without increasing the planar area occupied by one transistor. As a result, it is possible to improve on-current and suppress leakage current without reducing device integration.

However, the effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.

1A and 1B are perspective views of a tunneling field effect transistor according to a first embodiment.

FIG. 2 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 1A.

Figure 3 is a cross-sectional view taken along line II' of Figure 1b.

FIG. 4A is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the first embodiment viewed from the source region, and FIG. 4B is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the first embodiment from the drain region side. This is a cross-sectional view.

Figure 5 is a perspective view of the tunneling field effect transistor according to the second embodiment, excluding the source electrode and drain electrode.

FIG. 6 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 5.

Figure 7 is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the second embodiment as seen from the drain region.

8A and 8B are perspective views of a tunneling field effect transistor according to a third embodiment.

FIG. 9 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 8A.

Figure 10 is a cross-sectional view taken along line II' of Figure 8b.

FIG. 11A is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the third embodiment viewed from the source region, and FIG. 11B is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the third embodiment from the drain region side. This is a cross-sectional view.

Figure 12 is a perspective view of the tunneling field effect transistor according to the fourth embodiment, excluding the source electrode and drain electrode.

FIG. 13 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 12.

Figure 14 is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the fourth embodiment as seen from the drain region.

Hereinafter, in order to explain the present invention in more detail, preferred embodiments according to the present invention will be described in more detail with reference to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. In the drawings, where a layer is referred to as being “on” another layer or substrate, it may be formed directly on the other layer or substrate, or there may be a third layer interposed between them. In the present embodiments, “first,” “second,” or “third” are not intended to impose any limitation on the components, but should be understood as terms for distinguishing the components.

1A and 1B are perspective views of a tunneling field effect transistor according to a first embodiment. Here, FIG. 1A is a perspective view excluding the source electrode and drain electrode shown in FIG. 1B. FIG. 2 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 1A, and FIG. 3 is a cross-sectional view taken along the cutting line II' of FIG. 1B.

Referring to FIGS. 1A, 1B, 2, and 3, a substrate 100 may be provided. The substrate may be a semiconductor substrate, a metal substrate, a glass substrate, or a flexible substrate. For example, the flexible substrate may be a polymer substrate, such as a polyethylene terephthalate (PET) or polyimide (PI) substrate. Elements for operation circuits, etc. may be formed on the substrate 100. Additionally, a protective layer 105 such as an insulating film may be formed covering the substrate or the device. The protective layer 105 may be a silicon oxide film, a silicon nitride film, or a composite layer thereof.

A base semiconductor layer can be formed on the protective layer 105. The base semiconductor layer may be a silicon layer. As an example, it may be a single crystalline silicon layer, a polycrystalline silicon layer, or an amorphous silicon layer. Specifically, it may be an epitaxially grown single crystal silicon layer. In one example, the substrate 100, the protective layer 105, and the base semiconductor layer may be a silicon on insulator (SOI) substrate.

The semiconductor pattern 120 may be formed on the lower semiconductor layer 110, which is the lower region of the base semiconductor layer, by patterning the upper region of the base semiconductor layer. After stacking a device isolation film 115 on the lower semiconductor layer 110 on which the semiconductor pattern 120 is formed, the stacked device isolation film 115 is etched to form the device isolation film 115. It can be made to protrude upward from the upper surface and have a pin-shape.

At this time, the fin-shaped semiconductor pattern 120 includes a channel region 125 and a source region 123 and a drain region 121 on both sides of the channel region 125, respectively. The width W ₁ of the drain region 121 may be narrower than the width W ₂ of the channel region 125 or the source region 123 . Additionally, the first sidewall 121x of the drain region 121 may be located in the same plane as the first sidewall 125x of the channel region 125. In addition, the second sidewall 121y facing the first sidewall 121x of the drain region 121 is a drain area compared to the second sidewall 125y facing the first sidewall 125x of the channel region 125. It may be recessed in the direction of the first side wall (121x) of (121). As a result, the width between the first sidewall 121x and the second sidewall 121y of the drain region 121, that is, the width W ₁ of the drain region 121, is equal to the first sidewall of the channel region 125. The width between (125x) and the second side wall 125y, that is, may be narrower than the width (W ₂ ) of the channel region 125.

Here, the upper surface 121z of the drain region 121 may be located in the same plane as the upper surface 125z of the channel region 125.

Afterwards, a gate insulating film 130 may be formed on the fin-shaped semiconductor pattern 120. The gate insulating film 130 may be a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, an aluminum oxynitride film, or a composite film thereof. The gate insulating layer 130 may also be formed on the top surface and sidewalls of the fin-shaped semiconductor pattern 120.

By forming the gate electrode 140 on the gate insulating film 130, the gate insulating film may be interposed between the channel region 125 and the gate electrode 140. The gate electrode 140 is formed on a wide portion of the fin-shaped semiconductor pattern 120, that is, on the upper surface 125z of the channel region 125 and the first and

second sidewalls

125x and 125y. can be formed in The gate electrode 140 may be formed using Al, Cr, Cu, Ta, Ti, Mo, W, or an alloy thereof.

A source electrode 160 connected to the source region 123 can be formed. Specifically, the source electrode 160 may be formed on the source region 123, which is a wide portion of the fin-shaped semiconductor pattern 120 adjacent to the gate electrode 140. The source electrode 160 may be a metal electrode having a large work function compared to the work function of the semiconductor pattern 120 adjacent thereto, that is, the source region 123. When the source region 123 is a silicon layer, the source electrode 160 is made of nickel (Ni), iridium (Ir), palladium (Pd), or platinum with a work function greater than silicon, for example, 5 eV or more. (Pt), or a combination thereof. In this way, due to the difference in work function between the source region 123 and the source electrode 160, electrons in the source region 123 can move to the source electrode 160, ) A charge plasma of the first conductivity type, specifically, a hole plasma, may be formed in the source region 123 adjacent to the source region 123 to induce a p-type region, that is, a first conductivity type region 123p.

A drain electrode 150 connected to the drain region 121 can be formed. Specifically, the drain electrode 150 may be formed on the drain region 121, which is a narrow portion of the fin-shaped semiconductor pattern 120 adjacent to the gate electrode 140. The drain electrode 150 may be a metal electrode having a small work function compared to the work function of the semiconductor pattern 120, that is, the drain region 121. When the drain region 121 is a silicon layer, the drain electrode 150 is made of hafnium (Hf) or indium (In), which has a work function smaller than that of silicon, for example, a work function of 4.5 eV, specifically, a work function of 4.2 eV or less. ), zirconium (Zr), thallium (Tl), tantalum (Ta), titanium (Ti), aluminum (Al), or a combination thereof. In this way, due to the difference in work function between the drain region 121 and the drain electrode 150, electrons can move from the drain electrode 150 to the drain region 121, so that the drain electrode 150 ) A charge plasma of a second conductivity type, specifically, an electron plasma, may be formed in the drain region 121 adjacent to the n-type region, that is, a second conductivity type region 121p.

Specifically, the channel region 125 between the first conductive region 123p and the second conductive region 121p may be an intrinsic semiconductor region. In this way, the first conductive region 123p and the second conductive region 121p can be induced into the conductive region through charge plasma generation without impurity doping using ion implantation or the like. Accordingly, the manufacturing process is simpler compared to impurity doping such as ion implantation, and the production of defects can be suppressed. However, the present invention is not limited to this, and the first conductivity type region 123p and the second conductivity type region 121p may be formed by impurity doping using ion implantation, etc. rather than charge plasma generation. Above, the first conductive region (123p) is described as p-type and the second conductive region (121p) as n-type. However, this is not limited to this, and the first conductive region (123p) is described as n-type and the second conductive region (121p) is described as n-type. The conductive region 121p may be formed as a p-type.

The gate insulating film 130 is formed between the semiconductor pattern 120 and the gate electrode 140, and may extend between the source electrode 160 and the drain electrode 150 and the semiconductor pattern 120. .

Referring to FIG. 4A, in general, a tunneling field effect transistor generates an on-current by charge tunneling between the source region and the channel region. In the fin-shaped semiconductor pattern 120 according to the present embodiment, the area where the channel region 125 overlaps the gate electrode 140 is not only the upper surface 125z of the channel region 125, but also the side walls 125x, As the channel region 125 extends to 125y), the effective channel width (SW _eff ) where the on-current is generated at the portion where the channel region 125 is in contact with the source region 123 increases, thereby increasing the on-current.

Referring to FIG. 4B, in general, a tunneling field effect transistor generates an off-current by charge tunneling between the drain region and the channel region. In the device according to this embodiment, the first sidewall 121x of the drain region 121 is located in the same plane as the first sidewall 125x of the channel region 125, and the width (W) of the drain region 121 is ₁ ) is smaller than the width (W ₂ ) of the channel region 125, so the effective channel width (DW _eff ) where the off-current is generated in the portion 125d where the channel region overlaps the drain region 121 is on -Off-current can be suppressed because it is small compared to the effective channel width (SW _eff ) where the current is generated.

Accordingly, in one embodiment of the present invention, the on-current can be improved and the off-current can be suppressed without increasing the planar area occupied by one tunneling field effect transistor.

Figure 5 is a perspective view of the tunneling field effect transistor according to the second embodiment, excluding the source electrode and drain electrode. FIG. 6 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 5. Figure 7 is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the second embodiment as seen from the drain region. FIGS. 5, 6, and 7 correspond to FIGS. 1A, 2, and 4B, respectively, according to the first embodiment, and the tunneling field effect transistor according to the second embodiment is similar to that of the first embodiment, except as described later. It is substantially the same as the example. Specifically, the tunneling field effect transistor according to the second embodiment may have only the location of the drain region relative to the channel region changed compared to the tunneling field effect transistor according to the first embodiment.

Referring to FIGS. 5, 6, and 7, the first sidewall 121y of the drain region 121 may be located in the same plane as the first sidewall 125y of the channel region 125. In addition, the second side wall 121x facing the first side wall 121y of the drain region 121 is a drain region compared to the second side wall 125x facing the first side wall 125y of the channel region 125. It may be recessed in the direction of the first side wall (121y) of (121). As a result, the width between the first sidewall 121y and the second sidewall 121x of the drain region 121, that is, the width W ₁ of the drain region 121, is equal to the first sidewall of the channel region 125. The width between (125y) and the second side wall 125x, that is, may be narrower than the width (W ₂ ) of the channel region 125.

Accordingly, the effective channel width (DW _eff ) at which the off-current is generated in the region 125d where the channel region 125 overlaps the drain region 121 is the effective channel width at which the on-current is generated (SW in FIG. 4A _eff ), so the off-current can be suppressed.

8A and 8B are perspective views of a tunneling field effect transistor according to a third embodiment. Here, FIG. 8A is a perspective view excluding the source electrode and drain electrode shown in FIG. 8B. FIG. 9 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 8A, and FIG. 10 is a cross-sectional view taken along the cutting line II' of FIG. 8B. FIG. 11A is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the third embodiment viewed from the source region, and FIG. 11B is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the third embodiment from the drain region side. This is a cross-sectional view. The tunneling field effect transistor according to the third embodiment is substantially the same as the first embodiment except as described later. Specifically, the tunneling field effect transistor according to the third embodiment may be changed only in the area of the overlapping area of the drain region with respect to the channel region compared to the tunneling field effect transistor according to the first embodiment.

Referring to FIGS. 8A, 8B, 9, 10, 11A, and 11B, the first sidewall 121x of the drain region 121 is the same as the first sidewall 125x of the channel region 125. It can be located within a plane. In addition, the second side wall 121y facing the first side wall 121x of the drain region 121 is a drain region compared to the second side wall 125y facing the first side wall 125x of the channel region 125. It may be recessed in the direction of the first side wall (121x) of (121). As a result, the width between the first sidewall 121x and the second sidewall 121y of the drain region 121, that is, the width W ₁ of the drain region 121, is equal to the first sidewall of the channel region 125. The width between (125x) and the second side wall 125y, that is, may be narrower than the width (W ₂ ) of the channel region 125.

In addition, the upper surface 121z of the drain region 121 is recessed compared to the upper surface 125z of the channel region 125, so that the height (h ₁ ) of the drain region 121 is greater than the channel region ( It may be lower than the height (h ₂ ) of 125).

Accordingly, the area of the region 125d where the channel region 125 overlaps the drain region 121 is reduced, and the effective channel width (DW _eff ) at which the off-current is generated is reduced to the effective channel width at which the on-current is generated ( It is smaller than SW _eff ) in Figure 11a, so the off-current can be further suppressed.

Figure 12 is a perspective view of the tunneling field effect transistor according to the fourth embodiment, excluding the source electrode and drain electrode. FIG. 13 is a plan view showing the semiconductor pattern and gate electrode shown in FIG. 12. Figure 14 is a cross-sectional view of the channel region and gate electrode of the tunneling field effect transistor according to the fourth embodiment as seen from the drain region. FIGS. 12, 13, and 14 correspond to FIGS. 8A, 9, and 11B, respectively, according to the third embodiment, and the tunneling field effect transistor according to the fourth embodiment is similar to that of the third embodiment, except as described later. It is substantially the same as the example. Specifically, the tunneling field effect transistor according to the fourth embodiment may have only the location of the drain region relative to the channel region changed compared to the tunneling field effect transistor according to the third embodiment.

Referring to FIGS. 12, 13, and 14, the first sidewall 121y of the drain region 121 may be located in the same plane as the first sidewall 125y of the channel region 125. In addition, the second side wall 121x facing the first side wall 121y of the drain region 121 is a drain region compared to the second side wall 125x facing the first side wall 125y of the channel region 125. It may be recessed in the direction of the first side wall (121y) of (121). As a result, the width between the first sidewall 121y and the second sidewall 121x of the drain region 121, that is, the width W ₁ of the drain region 121, is equal to the first sidewall of the channel region 125. The width between (125y) and the second side wall 125x, that is, may be narrower than the width (W ₂ ) of the channel region 125.

Above, the present invention has been described in detail with preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical spirit and scope of the present invention. This is possible.

Claims

It is defined by a device isolation film disposed on a substrate and has a fin-shape that protrudes upward from the upper surface of the device isolation film, and has a channel region and a source region having a first conductivity type region on both sides thereof and a second conductivity type region. Semiconductor patterns each having a drain region, wherein the width of the drain region is narrower than the width of the channel region;

a gate electrode disposed on an upper surface of the channel region and extending on a first sidewall of the channel region and a second sidewall of the channel region facing the first sidewall of the channel region;

a gate insulating film interposed between the channel region and the gate electrode;

a source electrode connected to the source region; and

A tunneling field effect transistor having a drain electrode connected to the drain region.
In claim 1,

A tunneling field effect transistor wherein the first sidewall of the drain region is located in the same plane as the first sidewall of the channel region.
In claim 1 or claim 2,

A tunneling field effect transistor wherein the upper surface of the drain region is located in the same plane as the upper surface of the channel region.
In claim 1 or claim 2,

A tunneling field effect transistor with a height of the drain region that is lower than that of the channel region.
In claim 4,

A tunneling field effect transistor wherein the upper surface of the drain region is recessed compared to the upper surface of the channel region.
In claim 1,

A tunneling field effect transistor wherein the first conductivity type region is a charge plasma region of the first conductivity type induced by the source electrode.
In claim 6,

The source electrode is a metal electrode having a large work function compared to the work function of the source region, the charge plasma of the first conductivity type is a hole plasma, and the first conductivity type region is a p-type region.
In claim 1,

A tunneling field effect transistor, wherein the second conductivity type region is a charge plasma region of the second conductivity type induced by the drain electrode.
In claim 8,

The drain electrode is a metal electrode having a small work function compared to the work function of the drain region, the charge plasma of the second conductivity type is an electron plasma, and the second conductivity type region is an n-type drain region.