KR20190114695A - Tunneling field-effect transistor and method for manufacturing thereof - Google Patents

Abstract

According to an aspect of the technical idea of the present invention, a method for manufacturing a tunneling field-effect transistor is disclosed, comprising the steps of: forming a fin structure including a preliminary source pattern, a preliminary channel pattern, and a preliminary drain pattern by patterning a stack including at least one Si layer and at least one SiGe layer alternately stacked on a substrate; forming at least one bridge channel by selectively removing either the Si layer or the SiGe layer from the preliminary channel pattern of the fin structure; implanting Ge into the bridge channel, the preliminary source pattern, and the preliminary drain pattern of the fin structure; forming a dummy gate surrounding at least a portion of the bridge channel; forming a source and a drain by implanting impurities of different conductive types into each of the preliminary source pattern and the preliminary drain pattern of the fin structure; removing the dummy gate; and forming a gate surrounding at least a portion of the bridge channel. Thus, tunneling efficiency and a tunneling area can be increased by using multiple SiGe or Ge-based bridge channels.

Description

Tunneling field effect transistor and method of manufacturing the same {TUNNELING FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING THEREOF}

The technical idea of the present invention relates to a tunneling field effect transistor capable of implementing ultra low power and high energy efficiency and a method of manufacturing the same.

Semiconductor technology has revolutionized growth based on metal oxide semiconductor field effect transistors (MOSFETs) driven in the form of gate voltages and drift of carriers by drain voltages.

Recently, Tunneling Field Effect Transistors (TFETs) using band-to-band tunneling have been actively studied as a way to overcome the physical limitation that the MOSFET's threshold voltage cannot be lowered below 60mV / dec at room temperature. The TFET operates as a tunneling phenomenon of the carrier based on the energy band characteristic by the gate voltage and the drain voltage, and has a superior sub-threshold slope characteristic compared to the MOSFET. This is an index for evaluating the performance of the transistor as a switch. The lower the SS value, the lower the standby power consumption.

However, TFETs have not yet shown performance comparable to MOSFETs. Among the various reasons, the most important factors are the limited tunneling area, low band-to-band tunneling efficiency due to high bandgap energy, and low channel grip of the gate.

The technical problem to be achieved by the tunneling field effect transistor and its manufacturing method according to the technical idea of the present invention, by improving the tunneling efficiency, tunneling area, the channel grip force of the gate can achieve a significant improvement in current compared to the conventional tunneling field effect transistor. To implement a tunneling field effect transistor and a method of manufacturing the same.

The technical problem to be achieved by the tunneling field effect transistor and the method of manufacturing the same according to the technical idea of the present invention is not limited to the above-mentioned problem, another task not mentioned can be clearly understood by those skilled in the art from the following description will be.

In a method of manufacturing a tunneling field effect transistor according to an aspect of the inventive concept, a preliminary source pattern is formed by patterning a laminate including at least one Si layer and at least one SiGe layer alternately stacked on a substrate. Forming a fin structure comprising a preliminary channel pattern and a preliminary drain pattern; Selectively removing any one of the Si layer and the SiGe layer in the preliminary channel pattern of the fin structure to form at least one bridge channel; Implanting Ge into the bridge channel, the preliminary source pattern and the preliminary drain pattern of the fin structure; Forming a dummy gate surrounding at least a portion of the bridge channel; Implanting impurities of different conductivity types into each of the preliminary source pattern and the preliminary drain pattern of the fin structure to form a source and a drain; Removing the dummy gate; And forming a gate surrounding at least a portion of the bridge channel.

In example embodiments, the forming of the fin structure may include a width of the preliminary channel pattern in one direction parallel to the upper surface of the substrate in the at least one of the preliminary source pattern and the preliminary drain pattern. The fin structure may be formed by patterning the laminate so as to have a width smaller than.

According to an exemplary embodiment, the forming of the bridge channel may include removing the SiGe layer from the preliminary channel pattern of the fin structure to form the bridge channel, and implanting the Ge may include: The Si layer of the structure is converted to a Si _{1 - x} Ge _x layer, where x is greater than 0 and no greater than 1 and the SiGe layer is a Si _{1 - y} Ge _y layer, where y is greater than 0 and 1 The Ge may be injected into the bridge channel, the preliminary source pattern, and the preliminary drain pattern of the fin structure to be converted to the following, less than x).

According to an exemplary embodiment, the forming of the bridge channel may include removing the Si layer from the preliminary channel pattern of the fin structure to form the bridge channel, and implanting Ge may include: The SiGe layer of the structure is converted to a Si _{1 - x} Ge _x layer, where x is greater than 0 and no greater than 1 and the Si layer is a Si _{1 - y} Ge _y layer, where y is greater than 0 and 1 The Ge may be injected into the bridge channel, the preliminary source pattern, and the preliminary drain pattern of the fin structure to be converted to the following, less than x).

In example embodiments, the forming of the bridge channel may include forming one of the Si layer and the SiGe layer in the preliminary channel pattern of the fin structure through a dry etching process using fluorine as an etchant. It may be selectively removed to form the bridge channel.

According to an exemplary embodiment, the forming of the bridge channel may include forming the bridge channel in the preliminary channel pattern of the fin structure through a wet etching process using an ammonia-peroxide mixture (APM). One of the layers may be selectively removed to form the bridge channel.

According to an exemplary embodiment, the injecting Ge may include forming a SiGe thin film covering the bridge channel, the preliminary source pattern, and the preliminary drain pattern of the fin structure; And diffusing the Ge contained in the SiGe thin film into the bridge channel, the preliminary source pattern, and the preliminary drain pattern of the fin structure through an oxidation process.

According to an exemplary embodiment, the forming of the dummy gate may include forming a dummy gate material layer covering an upper surface of the substrate and the fin structure; And patterning the silicon oxide film remaining on the fin structure and the dummy gate material layer as a result of performing the step of diffusing Ge to form the dummy gate surrounding at least a portion of the bridge channel and the silicon oxide film on the bridge channel. It may include;

According to an exemplary embodiment, the method of manufacturing the tunneling field effect transistor may include: forming a gate dielectric layer surrounding at least a portion of the bridge channel between removing the dummy gate and forming the gate; It may further include.

According to another aspect of the present invention, there is provided a method of manufacturing a tunneling field effect transistor, by patterning a laminate including at least one Si layer and at least one SiGe layer alternately stacked on a substrate, thereby preparing a preliminary source. Forming a fin structure comprising a pattern, a preliminary channel pattern, and a preliminary drain pattern; Implanting Ge into the preliminary source pattern, the preliminary channel pattern, and the preliminary drain pattern of the fin structure; Selectively removing one of the Si and SiGe layers implanted with Ge in the preliminary channel pattern of the fin structure to form at least one bridge channel; Forming a dummy gate surrounding at least a portion of the bridge channel; Implanting impurities of different conductivity types into each of the preliminary source pattern and the preliminary drain pattern of the fin structure to form a source and a drain; Removing the dummy gate; And forming a gate surrounding at least a portion of the bridge channel.

According to an exemplary embodiment, the injecting Ge may include forming a SiGe thin film covering the preliminary source pattern, the preliminary channel pattern, and the preliminary drain pattern of the fin structure; And diffusing the Ge contained in the SiGe thin film into the preliminary source pattern, the preliminary channel pattern, and the preliminary drain pattern of the fin structure through an oxidation process.

According to an exemplary embodiment, the method of manufacturing the tunneling field effect transistor may be formed on the fin structure as a result of performing the step of diffusing the Ge between the step of implanting the Ge and forming the bridge channel. Removing the silicon silicon oxide film; may further include.

According to an exemplary embodiment, the step of implanting Ge, wherein the Si layer of the fin structure is converted into a Si _{1 - x} Ge _x layer, where x is greater than 0 and less than 1 and the SiGe layer is The Ge to the preliminary source pattern, the preliminary channel pattern and the preliminary drain pattern of the fin structure to be converted to a Si _{1 - y} Ge _y layer, where y is greater than 0 and less than 1 but less than x. and the number to be injected, forming a bridge channel is, in the preliminary channel pattern of the fin structure, the Si _{1 -} it is possible to remove the _y Ge _y layer to form the bridge channel.

According to an exemplary embodiment, the injecting Ge may include converting the SiGe layer of the fin structure into a Si _{1 - x} Ge _x layer, where x is greater than 0 and less than or equal to 1 and the Si layer is The Ge to the preliminary source pattern, the preliminary channel pattern and the preliminary drain pattern of the fin structure to be converted to a Si _{1 - y} Ge _y layer, where y is greater than 0 and less than 1 but less than x. and the number to be injected, forming a bridge channel is, in the preliminary channel pattern of the fin structure, the Si _{1 -} it is possible to remove the _y Ge _y layer to form the bridge channel.

According to an exemplary embodiment, the method of manufacturing the tunneling field effect transistor may include: forming a gate dielectric layer surrounding at least a portion of the bridge channel between removing the dummy gate and forming the gate; It may further include.

According to a tunneling field effect transistor according to embodiments of the inventive concept, tunneling efficiency and tunneling area may be increased by using a plurality of SiGe (silicon-germanium) or Ge (germanium) based bridge channels. The channel holding power of the gate is increased due to the enclosing of the plurality of channels, and as a result, a significant improvement in current can be obtained as compared with the conventional tunneling field effect transistor.

In addition, according to the method of manufacturing a tunneling field effect transistor according to embodiments of the inventive concept, a plurality of sources, drains, and gates are not formed before forming a channel in order to prevent damage to the channel. By forming the bridge channels of the line and ensuring the characteristics such as tunneling efficiency of the plurality of bridge channels through Ge condensation, it is possible to manufacture a tunneling field effect transistor having improved characteristics in a simplified process.

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings referred to herein, a brief description of each drawing is provided.
1A to 1D are exemplary views illustrating a tunneling field effect transistor according to an embodiment of the inventive concept, FIG. 1A is a perspective view schematically illustrating some components of a tunneling field effect transistor, and FIG. 1B is 1A is a cross-sectional view of the tunneling field effect transistor of FIG. 1A taken along line BB ′, and FIG. 1C is a cross-sectional view of the tunneling field effect transistor of FIG. 1A taken along line CC ′, and FIG. 1D illustrates the tunneling field effect transistor of FIG. 1A. Sectional view taken along the line DD '.
2A to 2K are perspective views illustrating a manufacturing method of a tunneling field effect transistor according to an embodiment of the inventive concept.
3A to 3D are perspective views illustrating a manufacturing method of a tunneling field effect transistor according to another embodiment of the inventive concept.

Exemplary embodiments according to the technical idea of the present invention are provided to more fully explain the technical idea of the present invention to those skilled in the art, and the following embodiments are modified in various other forms. The scope of the technical spirit of the present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

Although the terms first, second, etc. are used herein to describe various members, regions, layers, regions, and / or components, these members, parts, regions, layers, regions, and / or components are referred to in these terms. It is obvious that it should not be limited by. These terms do not imply any particular order, up or down, or superiority, and are used only to distinguish one member, region, region, or component from another member, region, region, or component. Accordingly, the first member, region, region or component to be described below may refer to the second member, region, region or component without departing from the teachings of the inventive concept. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by those skilled in the art, including technical terms and scientific terms. Also, as used in the prior art, terms as defined in advance should be construed to have a meaning consistent with what they mean in the context of the technology concerned, and in an overly formal sense unless explicitly defined herein. It should not be interpreted.

In the case where an embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously or in a reverse order.

In the accompanying drawings, for example, variations in the shape shown may be envisaged, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments according to the spirit of the present invention should not be construed as limited to the specific shape of the region shown in the present specification, but should include, for example, a change in shape resulting from the manufacturing process. The same reference numerals are used for the same elements in the drawings, and redundant description thereof will be omitted.

The term 'and / or' as used herein includes each and every combination of one or more of the mentioned members.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are exemplary views illustrating a tunneling field effect transistor 100 according to an embodiment of the inventive concept, and FIG. 1A schematically illustrates some components of the tunneling field effect transistor 100. 1B is a cross-sectional view of the tunneling field effect transistor of FIG. 1A taken along line BB ', and FIG. 1C is a cross-sectional view of the tunneling field effect transistor of FIG. 1A taken along line CC ′, and FIG. 1D is a view of FIG. 1A Is a cross-sectional view of a tunneling field effect transistor taken along the line DD '.

1A to 1D, the tunneling field effect transistors 100 are spaced apart from each other along a substrate 110 and a first direction parallel to the upper surface of the substrate 110 on the substrate 110 (hereinafter referred to as an X direction). A gate 150 covering at least a portion of each of the source 120 and the drain 130, the plurality of bridge channels 140 formed between the source 120 and the drain 130, and the plurality of bridge channels 140. And a gate dielectric layer 160 interposed between at least a portion of each of the plurality of bridge channels 140 and the gate 150. Here, the bridge channels 140 may be named differently, such as a nano wire channel, and will be referred to below as bridge channels 140 for convenience of description.

Although not shown in FIGS. 1A to 1D, the tunneling field effect transistor 100 includes an insulating layer covering the source 120, the drain 130, and the gate 150 on the substrate 110 (see 170 of FIG. 2K). It may include. In addition, although not shown in FIGS. 1A to 1D, a contact for connecting to a corresponding wiring in a later process is formed on each of the source 120, the drain 130, and the gate 150 of the tunneling field effect transistor 100. Of course, the electrode structure may be further formed.

The substrate 110 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. However, the present invention is not limited thereto, and the substrate 110 may be a bulk silicon substrate.

The substrate 110 may include a base layer 111 and an insulating layer 112.

The base layer 111 may be, for example, a single semiconductor material such as Si (silicon) or Ge (germanium), or SiGe (silicon germanium), SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide) Or a compound semiconductor material such as indium phosphide (InP). In some embodiments, the base layer 111 may include a conductive region, for example, a well doped with impurities, or a structure doped with impurities.

The insulating layer 112 may be formed of, for example, a silicon oxide film, a silicon nitride film, or a combination thereof. Alternatively, the insulating layer 112 may be, for example, a tetraethyl orthosilicate (TEOS) oxide film or a high density plasma (HDP) oxide film having excellent step coverage. 1A to 1D, the insulating layer 112 is illustrated as being made of a single layer, but the insulating layer 112 may be composed of a plurality of layers as necessary.

The source 120 may include first SiGe layers 121 and second SiGe layers 122 that are alternately stacked along a direction perpendicular to an upper surface of the substrate 110 (hereinafter, referred to as a Z direction).

In some embodiments, the first SiGe layers 121 and the second SiGe layers 122 may be formed of SiGe doped with a first conductivity type impurity, for example, a P type impurity. However, the present invention is not limited thereto, and the first SiGe layers 121 and the second SiGe layers 122 may be formed of SiGe doped with a second conductivity type impurity, for example, an N type impurity.

In some embodiments, the Ge content of the first SiGe layers 121 may be greater than the Ge content of the second SiGe layers 122. Specifically, the first 1 SiGe layer 121 are Si _{1 - x} Ge _x is composed of, claim 2 SiGe layer 122 are Si _{1 -} may be of a _y Ge _y. Here, x may be greater than 0 and less than or equal to 1, and y may be smaller than x.

In some embodiments, the first SiGe layers 121 and the second SiGe layers 122 may have the same thickness in the Z direction. However, the present invention is not limited thereto, and the first SiGe layers 121 and the second SiGe layers 122 may have different thicknesses in the Z direction.

Meanwhile, in FIGS. 1A and 1B, the source 120 has a structure in which three first SiGe layers 121 and two second SiGe layers 122 are stacked, but the first SiGe layers 121 and first are formed. The number of 2 SiGe layers 122 is not limited thereto.

1A and 1B, the first SiGe layers 121 are shown to constitute the bottom and top layers of the source 120, whereas the bottom and / or top layers of the source 120 are second. It may be composed of SiGe layers 122.

1A and 1B, each of the first SiGe layers 121 and the second SiGe layers 122 of the source 120 may be parallel to the X direction and the upper surface of the substrate 110 and orthogonal to the X direction. Although the side surfaces of the first SiGe layers 121 and the second SiGe layers 122 have the same width along the second direction (hereinafter, referred to as the Y direction), but are not limited thereto. It is not.

Due to the selective etching of the bridge channel 140 forming process to be described later, the first SiGe layers 121 and the second SiGe layers 122 may have different widths along the X direction and / or the Y direction, As a result, side surfaces of the first SiGe layers 121 and the second SiGe layers 122 may have a step in the X direction and / or the Y direction.

The drain 130 may include third SiGe layers 131 and fourth SiGe layers 132 that are alternately stacked along the Z direction.

In some embodiments, the third SiGe layers 131 and the fourth SiGe layers 132 may be formed of SiGe doped with a second conductivity type impurity, for example, an N type impurity. However, the present invention is not limited thereto, and the third SiGe layers 131 and the fourth SiGe layers 132 may be formed of SiGe doped with a first conductivity type impurity, for example, a P type impurity. That is, the third SiGe layers 131 and the fourth SiGe layers 132 of the drain 130 have different conductivity types from those of the first SiGe layers 121 and the second SiGe layers 122 of the source 120. May be made of SiGe doped with impurities.

In some embodiments, the Ge content of the third SiGe layers 131 may be greater than the Ge content of the fourth SiGe layers 132. Specifically, the first 3 SiGe layer 131 are Si _{1 -} consist of _x Ge _x, the SiGe 4 layer 132 are Si _{1 -} may be of a _y Ge _y. Here, x may be greater than 0 and less than or equal to 1, and y may be smaller than x.

In some embodiments, the third SiGe layers 131 and the fourth SiGe layers 132 may have the same thickness in the Z direction. However, the present invention is not limited thereto, and the third SiGe layers 131 and the fourth SiGe layers 132 may have different thicknesses in the Z direction.

Meanwhile, in FIGS. 1A and 1C, the drain 130 has a structure in which three third SiGe layers 131 and two fourth SiGe layers 132 are stacked, but the third SiGe layers 131 and the third layer are formed. The number of layers in which 4 SiGe layers 132 are stacked is not limited thereto.

1A and 1C, the third SiGe layers 131 are shown to constitute the bottom and top layers of the drain 130, whereas the bottom and / or top layers of the drain 130 may be the fourth layer. It may be composed of SiGe layers 132.

In addition, in FIGS. 1A and 1C, each of the third SiGe layers 131 and the fourth SiGe layers 132 of the drain 130 has the same width along the X and Y directions and has a third SiGe layer ( Side surfaces of each of the 131 and the fourth SiGe layers 132 are illustrated to be coplanar with each other, but embodiments are not limited thereto.

Like the source 120, the third SiGe layers 131 and the fourth SiGe layers 132 may be formed along the X direction and / or the Y direction due to the selective etching of the bridge channel 140 forming process to be described later. The side surfaces of each of the third SiGe layers 131 and the fourth SiGe layers 132 may have steps along the X direction and / or the Y direction.

The bridge channels 140 may extend in the X direction to connect the source 120 and the drain 130, respectively, and may be spaced apart from each other at predetermined intervals along the Z direction.

Specifically, the bridge channels 140 may extend along the X direction to connect the first SiGe layers 121 of the corresponding source 120 and the third SiGe layers 131 of the drain 130, respectively. The second SiGe layers 122 of the source 120 or the fourth SiGe layers 132 of the drain 130 may be spaced apart from each other at intervals corresponding to the thicknesses in the Z direction. Meanwhile, in FIGS. 1A and 1B, each of the bridge channels 140 is spaced at equal intervals along the Z direction, but is not limited thereto.

The bridge channels 140 may include first to third portions 140a to 140c, respectively.

For example, the first portion 140a may be formed of SiGe doped with a first conductivity type impurity, such as the first SiGe layer 121 of the source 120, and the second portion 140b may be formed on the gate 150. It is an effective channel surrounded by the outer surface by the impurity doped SiGe, the third portion 140c is a SiGe doped with a second conductivity type impurities, such as the third SiGe layer 131 of the drain 130 Can be done.

However, this is merely exemplary, and the first to third portions 140a to 140c of each of the bridge channels 140 may be modified according to the width of the gate 150 in the X direction described below.

For example, if the width of the gate 150 in the X direction is the same as the width of the bridge channels 140 in the X direction, each of the bridge channels 140 is entirely surrounded by the gate 150. Therefore, all parts may be made of SiGe, which is not doped with impurities as an effective channel, as in the second part described above.

The first to third portions (140a to 140c) are substantially example SiGe, for example, having the same Ge content, Si _{1 - x} Ge _x may be formed of.

The width of each of the bridge channels 140 in the Y direction may be smaller than the width of the source 120 and / or drain 130 in the Y direction.

Meanwhile, in FIGS. 1A and 1D, the widths of the bridge channels 140 in the Y direction and the thicknesses in the Z direction are the same, but are not limited thereto.

The vertical cross section of the bridge channels 140 in the X direction may have a rectangular shape as shown in FIGS. 1A and 1D. However, the present invention is not limited thereto, and the vertical cross section of the bridge channels 140 in the X direction may have various shapes such as a circle.

1A and 1D illustrate an embodiment in which three bridge channels 140 are configured, but embodiments are not limited thereto. The number of the bridge channels 140 may be variously configured to correspond to the number of stacks of the first SiGe layers 121 of the source 120 and the third SiGe layers 131 of the drain 130, but at least one or more. It may be configured as.

The gate 150 may be formed on the substrate 110 to surround at least a portion of the bridge channels 140 with the gate dielectric layer 160 interposed therebetween.

The gate 150 may be made of various materials such as a metal material. For example, the gate 150 may be polysilicon, tantalum nitride (TaN), nickel tantalum (NiTa), titanium (Ti), titanium nitride (TiN), titanium (Ti), tungsten (W), or tungsten nitride. At least one selected from (WN), hafnium (Hf), molybdenum (Mo), iridium (Ir), platinum (Pt), cobalt (Co), chromium (Cr), ruthenium oxide (RuO2), and molybdenum nitride (Mo2N) It can be made of a material.

The gate dielectric layer 160 may be formed of at least one material selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an oxide / nitride / oxide (ONO), or a higher-k dielectric material than the silicon oxide film. . For example, the gate dielectric layer 160 may include a material having a dielectric constant of about 10 to 25. The gate dielectric layer 160 includes, for example, hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), and lanthanum aluminum oxide ( LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide ( BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and / or lead scandium tantalum oxide (PbScTaO). .

As described above, the tunneling field effect transistor 100 according to the embodiments of the inventive concept may include a plurality of bridge channels each including SiGe or Ge having an outer surface surrounded by a gate and having an energy band gap lower than that of Si. By doing so, it is possible to increase the tunneling area and the tunneling efficiency as well as to improve the channel grip force of the gate.

2A to 2K are perspective views illustrating a manufacturing method of a tunneling field effect transistor 100 according to an embodiment of the inventive concept. In Figs. 2A to 2K, the same reference numerals as in Figs. 1A to 1D denote the same members, and redundant description thereof is omitted here for the sake of simplicity.

In the present embodiment, a selective epitaxial-layer growth (SEG) technique for selectively depositing SiGe in a plurality of bridge channels made of Si, a plurality of bridges made of SiGe or Ge through Ge condensation Channel formation technology, self-align dummy gate formation technology, high selectivity dummy gate etching technology, high concentration source / drain formation technology, low SiGe-metal contact resistance formation technology, SiGe heterojunction multi-bridge Through the channel structure forming technology, a tunneling field effect transistor 100 having a high driving current and a low threshold voltage slope characteristic is implemented.

Referring to FIG. 2A, a laminate 220 in which a plurality of Si layers 221 and a plurality of SiGe layers 222 are alternately stacked is formed on a substrate 110.

The laminate 220 in this embodiment has a structure in which three Si layers 221 and two SiGe layers 222 are stacked, but the number of Si layers 221 and SiGe layers 222 is not limited thereto. Do not. In this embodiment, the Si layer 221 is composed of the lowermost layer and the uppermost layer of the laminate 220. Alternatively, the lowermost layer and / or the uppermost layer of the laminate 220 may be the SiGe layer 222. have. The Si layer 221 and the SiGe layer 222 may be stacked with the same thickness in the Z-axis direction, but is not limited thereto.

In the present embodiment, when the substrate 110 is formed of an SOI substrate, the lowermost Si layer 221 may be an upper Si layer of the SOI substrate, and the insulating layer 112 may be a buried oxide layer of the SOI substrate.

Referring to FIG. 2B, the fin structure 230 may be formed by patterning the stack 220 of FIG. 2A.

The fin structure 230 may be formed by forming a hard mask on the laminate 220 of FIG. 2A and then etching the laminate 220 using the formed hard mask as an etching mask.

The fin structure 230 may include a preliminary source pattern 230a for forming a source by a subsequent process, a preliminary channel pattern 230b for forming bridge channels, and a preliminary drain pattern 230c for forming a drain. have.

The width of the preliminary channel pattern 230b in the Y direction may be smaller than the width of the preliminary source pattern 230a or the preliminary drain pattern 230c in the Y direction.

Referring to FIG. 2C, one of the Si layers 221 and the SiGe layers 222 included in the preliminary channel pattern 230b of FIG. 2B may be selectively removed.

In the present exemplary embodiment, the SiGe layers 222 are selectively removed from the Si layers 221 and the SiGe layers 222. However, the Si of the Si layers 221 and the SiGe layers 222 is different. Layers 221 may optionally be removed.

Accordingly, a plurality of preliminary bridge channels 230bx connected to the preliminary source pattern 230ax and the preliminary drain pattern 230cx of the fin structure 230x and spaced apart from each other in the Z-axis direction may be formed.

The preliminary bridge channels 230bx may be formed of only the Si layers 221 by selective etching of the SiGe layers 222. Meanwhile, as described above, if the Si layers 221 are selectively etched instead of the SiGe layers 222, the preliminary bridge channels 230bx may be formed of only the SiGe layers 222.

This selective etching process may be performed through a chemical dry etch (CDE) or wet etch (wet etch).

In the chemical dry etching process, the plasma generated in the radical generator may be used. The radicals are evenly distributed in the process chamber and adhere to the surface of the target (ie, SiGe layer 222) without directivity, resulting in isotropic etching. The reaction between the radical and the exposed surface produces volatiles and continues further reaction. The main etchant for etching the SiGe layers 222 in this embodiment may be, for example, fluorine. The selectivity between Si and SiGe is due to the difference in the binding energy of Si-Si and Si-Ge. Si-Ge bond energy is 2.12eV, which is less than Si-Si bond energy 2.31eV, so Si-Ge bonds are easily broken and Si-F or Ge-F bonds are easier than Si-Si bonds. The continuous reaction between the fluorine atom and Si- or Ge- produces volatile SiF _x and GeF _y , which allows the SiGe layers 222 located in the preliminary channel pattern 230b to be completely removed. With this mechanism, SiGe has a selectivity of 20: 1 relative to Si and can be successfully removed.

Another method of selective etching is a wet etching process using an ammonia-peroxide mixture (APM). In the mixture, H ₂ O ₂ may serve as an oxidizing agent and NH ₄ OH may serve as an oxide etchant. Since the oxidation rate is faster than that of Si, Ge can be selectively etched by NH 4 OH with a selectivity of 5: 1 relative to Si. In this case, corners of the preliminary bridge channels 230bx may be rounded more than dry etching due to the corner-rounding tendency of the APM.

On the other hand, although not shown, as a result of the above-described etching process, the preliminary bridge channel 230bx is also finely etched so that the corners of the preliminary bridge channels 230bx may have a rounded shape.

In addition, as a result of performing the above-described etching processes, a part of the SiGe layers 222 of each of the preliminary source pattern 230ax and / or the preliminary drain pattern 230cx are etched to form the preliminary source pattern 230ax and / or the preliminary drain. Si layers 221 and SiGe layers 222 may have a step in the X direction at each side of the pattern 230cx.

Referring to FIG. 2D, a SiGe thin film 240 covering the fin structure 230x may be formed for Ge condensation.

In some embodiments, SiGe thin film 240 may be formed by a selective epitaxial growth (SEG) process. The selective epitaxial growth process may be implemented by a reduced pressure chemical vapor deposition method or a low pressure chemical vapor deposition method.

Referring to FIG. 2E, an oxidation process may be performed while the SiGe thin film 240 covering the fin structure 230x is formed to diffuse Ge contained in the SiGe thin film 240 into the fin structure 230x.

As the Ge contained in the SiGe thin film 240 diffuses into the fin structure 230x (see FIG. 2D), the Si layers 221 and the SiGe layers 222 constituting the fin structure 230x are modified (ie, The Ge content is changed) to form the fin structure 230y.

More specifically, the Si layers 221 (see FIG. 2D) of the fin structure 230x are SiGe layers 221y, and the SiGe layers 222 (see FIG. 2D) of the fin structure 230x are SiGe layers 222y. Can be. Here, SiGe layer (221y) are Si _{1 - x} Ge _x may be may be, SiGe layer (222y) are _{Si 1-y Ge y (y} <x).

Meanwhile, when the Si layers 221 are removed in the process described with reference to FIG. 2C, the SiGe layers 222 of the fin structure 230x are Si _{1 - x} Ge _x , and the Si layers 221 are Si _{1- .} The Ge may be diffused into the fin structure 230x to be converted to _y Ge _y (y <x).

The oxidation process can be carried out, for example, through dry oxidation or wet oxidation. This oxidation process may be performed by supplying oxygen to the furnace while heat-treating for several minutes to 800 hours at 800 to 950 ° C. with the substrate 110 having the structure shown in FIG. 2D disposed on the furnace. have. Such heat treatment conditions may vary depending on the thickness of the SiGe thin film 240 and the mole fraction of Ge contained in the SiGe thin film 240.

Meanwhile, through the Ge condensation process described with reference to FIGS. 2D and 2E, Si of the SiGe thin film 240 (see FIG. 2D) is oxidized to remain on the fin structure 230y as the silicon oxide film 240y.

Referring to FIG. 2F, a dummy gate material layer 250 covering the upper surface of the substrate 110 and the fin structure 230y may be formed. The dummy gate material layer 250 is for forming a dummy gate in a subsequent process, and may be formed of silicon nitride, for example.

Referring to FIG. 2G, the dummy gate material layer 250 (see FIG. 2F) is patterned to form a dummy gate 250x surrounding a portion of the modified preliminary bridge channels 230by. In the patterning process, the silicon oxide layer 240y that covers the fin structure 230y may be removed except for a portion 240z that the dummy gate 250x covers.

Referring to FIG. 2H, each of the modified preliminary source pattern 230ay and the modified preliminary drain pattern 230cy may be doped with impurities of different conductivity types to form the source 120 and the drain 130.

For example, the source 120 may form a photoresist film (not shown) in the dummy gate 250x and the modified preliminary drain pattern 230cy of the fin structure 230y, and may be a region in which the photoresist film does not exist, that is, modified. It can be formed by injecting a high concentration of P-type impurities into the preliminary source pattern 230ay.

For example, the drain 130 may pattern a photoresist film (not shown) in the dummy gate 250x and the source 120 of the fin structure 230y, and may include a region in which the photoresist film does not exist, that is, a modified preliminary drain pattern. It can be formed by injecting a high concentration of N-type impurities to 230cy.

Meanwhile, as the dummy gate 250x is formed to cover only a part of the modified preliminary bridge channel 230by, the N-type impurities and the P-type impurities are respectively injected into both ends of the modified preliminary bridge channels 230by to bridge the channel. 140 may be defined.

Referring to FIG. 2I, an insulating layer 170 may be formed to cover the source 120, the bridge channels 140, the drain 130, and the dummy gate 250x on the substrate 110.

The insulating layer 170 may be formed of a material having an etching selectivity different from that of the dummy gate 250x. For example, when the dummy gate 250x is made of silicon nitride, the insulating layer 170 may be made of silicon oxide.

The upper surface of the dummy gate 250x may be exposed through a process such as chemical mechanical planarization (CMP) followed by the formation of the insulating layer 170.

Referring to FIG. 2J, the silicon oxide layer 240z (see FIG. 2I) covered by the dummy gate 250x and the dummy gate 250x may be removed through the exposed top surface of the dummy gate 250x (see FIG. 2I).

Removal of the dummy gate 250x and the silicon oxide layer 240z may be performed by, for example, a wet etching process or a dry etching process, through which a bridge channel connecting the source 120 and the drain 130 may be formed. Some of the 140 may be exposed.

Referring to FIG. 2K, the gate dielectric layer 160 may be formed to cover a portion of the exposed bridge channels 140, and the gate 150 may be formed to fill a space in which the dummy gate 250x (see FIG. 2I) was formed. Can be.

Thereafter, although not shown, a process of forming a gate electrode structure on the upper surface of the gate 150, a process of forming a contact structure on the upper surface of the source 120 and the drain 130, and a post-process for wiring connection may be performed. have.

3A through 3D are perspective views illustrating a manufacturing method of a tunneling field effect transistor according to another embodiment of the inventive concept. In Figs. 2A to 2K, the same or similar reference numerals as in Figs. 1A to 1D and 2A to 2K denote the same or similar members, and redundant description thereof will be omitted here for the sake of simplicity.

3A to 3D exemplarily illustrate a method of manufacturing a tunneling field effect transistor in which Ge condensation processes are performed before the formation of bridge channels, unlike the embodiment described with reference to FIGS. 2A to 2K. Drawings for the following.

First, referring to FIG. 3A, the fin structure 330 may be formed by patterning a laminate in which a plurality of Si layers 321 and a plurality of SiGe layers 322 are alternately stacked on the substrate 110. .

The fin structure 330, like the fin structure 230 described with reference to FIG. 2B, may include a preliminary source pattern 330a for forming a source, a preliminary channel pattern 330b for forming bridge channels, and a drain by a subsequent process. A preliminary drain pattern 330c may be included.

Referring to FIG. 3B, the fin structure 330y may be formed by injecting Ge into the fin structure 330. Injection of the Ge may be performed by Ge condensation described with reference to FIGS. 2D and 2E, and redundant description thereof will be omitted.

The Si layer 321 (see FIG. 3A) may be SiGe layers 321y by the Ge injection, and the SiGe layers 322 (see FIG. 3A) may be SiGe layers 322y. Here, SiGe layer (321y) are Si _{1 -} can be a _{y Ge y (y <x)} - x Ge x may be, SiGe layer (222y) are Si _1.

Meanwhile, when the Si layers 321 are removed in the process described below, the SiGe layers 322 of the fin structure 230x are Si _{1 - x} Ge _x , and the Si layers 321 are Si _{1 - y} Ge _y ( The Ge may be diffused into the fin structure 330x to be converted into y <x).

Referring to FIG. 3C, one of the SiGe layers 321y and the SiGe layers 322y included in the preliminary channel pattern 330b of FIG. 3B may be selectively removed.

In the present exemplary embodiment, the SiGe layers 322y among the SiGe layers 321y and the SiGe layers 322y are selectively removed. However, SiGe among the SiGe layers 321y and the SiGe layers 322y is different. Layers 321y may optionally be removed.

Accordingly, a plurality of preliminary bridge channels 330bx may be formed to connect the preliminary source pattern 230ax and the preliminary drain pattern 230cx of the fin structure 330x and be spaced apart from each other in the Z-axis direction.

Referring to FIG. 3D, the source 120, the drain 130, the bridge channels 140, the gate 150, the gate dielectric layer 160, and the like may be formed by a method similar to that described with reference to FIGS. 2F through 2K. The tunneling field effect transistor 100 can be manufactured.

As described above, according to the method of manufacturing the tunneling field effect transistor 100 according to the embodiments of the inventive concept, a plurality of bridge channels are formed prior to forming a source, a drain, and a gate, but the plurality of bridge channels are formed through Ge condensation. By making the bridge channels of SiGe or Ge having a lower bandgap energy than Si, it is possible to manufacture a tunneling field effect transistor having improved characteristics such as tunneling efficiency at a low cost through a simplified process.

Those skilled in the art will appreciate that various modifications and variations can be made without departing from the essential features of the present invention.

Therefore, the embodiments disclosed in the present specification are not intended to limit the technical spirit of the present invention but to describe the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments.

The protection scope of the present invention should be interpreted by the following claims, and all technical ideas within the equivalent scope should be interpreted as being included in the scope of the present invention.

100: tunneling field effect transistor
110: substrate
120: source
130: drain
140: bridge channel
150: gate
160: gate dielectric layer

Claims (15)

Patterning a laminate including at least one Si layer and at least one SiGe layer alternately stacked on a substrate to form a fin structure including a preliminary source pattern, a preliminary channel pattern, and a preliminary drain pattern;
Selectively removing one of the Si layer and the SiGe layer in the preliminary channel pattern of the fin structure to form at least one bridge channel;
Implanting Ge into the bridge channel, the preliminary source pattern and the preliminary drain pattern of the fin structure;
Forming a dummy gate surrounding at least a portion of the bridge channel;
Implanting impurities of different conductivity types into each of the preliminary source pattern and the preliminary drain pattern of the fin structure to form a source and a drain;
Removing the dummy gate; And
Forming a gate surrounding at least a portion of the bridge channel;
A method of manufacturing a tunneling field effect transistor comprising a.
According to claim 1,
Forming the fin structure,
The fin structure is formed by patterning the laminate such that a width of the preliminary channel pattern in one direction parallel to the upper surface of the substrate is smaller than a width of at least one of the preliminary source pattern and the preliminary drain pattern in the one direction. The manufacturing method of the tunneling field effect transistor characterized by the above-mentioned.
According to claim 1,
Forming the bridge channel,
Removing the SiGe layer from the preliminary channel pattern of the fin structure to form the bridge channel,
Injecting the Ge,
The Si layer of the fin structure is converted to a Si _{1 - x} Ge _x layer, where x is greater than 0 and less than or equal to 1, and the SiGe layer is a Si _{1 - y} Ge _y layer, where y is greater than 0 And Ge is injected into the bridge channel, the preliminary source pattern and the preliminary drain pattern of the fin structure to be converted to 1 or less but less than x).
According to claim 1,
Forming the bridge channel,
Removing the Si layer from the preliminary channel pattern of the fin structure to form the bridge channel,
Injecting the Ge,
The SiGe layer of the fin structure is converted to a Si _{1 - x} Ge _x layer, where x is greater than 0 and less than 1, and the Si layer is a Si _{1 - y} Ge _y layer, where y is greater than 0 And Ge is injected into the bridge channel, the preliminary source pattern and the preliminary drain pattern of the fin structure to be converted to 1 or less but less than x).
According to claim 1,
Forming the bridge channel,
Tunneling, characterized in that to form the bridge channel by selectively removing any one of the Si layer and the SiGe layer in the preliminary channel pattern of the fin structure through a dry etching process using fluorine as an etchant (etchant) Method for manufacturing a field effect transistor.
According to claim 1,
Forming the bridge channel,
Selectively removing any one of the Si layer and the SiGe layer from the preliminary channel pattern of the fin structure through a wet etching process using an ammonia-peroxide mixture (APM) to form the bridge channel A method of manufacturing a tunneling field effect transistor, characterized in that.
According to claim 1,
Injecting the Ge,
Forming a SiGe thin film covering the bridge channel, the preliminary source pattern and the preliminary drain pattern of the fin structure; And
Diffusing the Ge contained in the SiGe thin film into the bridge channel, the preliminary source pattern, and the preliminary drain pattern of the fin structure through an oxidation process;
Method for manufacturing a tunneling field effect transistor comprising a.
The method of claim 7, wherein
Forming the dummy gate,
Forming a dummy gate material layer covering an upper surface of the substrate and the fin structure; And
Patterning the silicon oxide film remaining on the fin structure and the dummy gate material layer as a result of performing the step of diffusing Ge to form the dummy gate surrounding at least a portion of the bridge channel and the silicon oxide film on the bridge channel ;
Method for manufacturing a tunneling field effect transistor comprising a.
According to claim 1,
Between removing the dummy gate and forming the gate,
Forming a gate dielectric layer surrounding at least a portion of the bridge channel;
Method for manufacturing a tunneling field effect transistor, characterized in that it further comprises.
Patterning a laminate including at least one Si layer and at least one SiGe layer alternately stacked on a substrate to form a fin structure including a preliminary source pattern, a preliminary channel pattern, and a preliminary drain pattern;
Implanting Ge into the preliminary source pattern, the preliminary channel pattern, and the preliminary drain pattern of the fin structure;
Selectively removing one of the Si and SiGe layers implanted with Ge in the preliminary channel pattern of the fin structure to form at least one bridge channel;
Forming a dummy gate surrounding at least a portion of the bridge channel;
Implanting impurities of different conductivity types into each of the preliminary source pattern and the preliminary drain pattern of the fin structure to form a source and a drain;
Removing the dummy gate; And
Forming a gate surrounding at least a portion of the bridge channel;
A method of manufacturing a tunneling field effect transistor comprising a.
The method of claim 10,
Injecting the Ge,
Forming a SiGe thin film covering the preliminary source pattern, the preliminary channel pattern, and the preliminary drain pattern of the fin structure; And
Diffusing the Ge contained in the SiGe thin film into the preliminary source pattern, the preliminary channel pattern, and the preliminary drain pattern of the fin structure through an oxidation process; manufacturing a tunneling field effect transistor. Way.
The method of claim 11, wherein
Between injecting the Ge and forming the bridge channel,
Removing the silicon silicon oxide film remaining on the fin structure as a result of performing the step of diffusing Ge;
Method for manufacturing a tunneling field effect transistor, characterized in that it further comprises.
The method of claim 10,
Injecting the Ge,
The Si layer of the fin structure is converted to a Si _{1 - x} Ge _x layer, where x is greater than 0 and less than or equal to 1, and the SiGe layer is a Si _{1 - y} Ge _y layer, where y is greater than 0 And Ge is injected into the preliminary source pattern, the preliminary channel pattern, and the preliminary drain pattern of the fin structure to be converted to 1 or less but less than x).
Forming the bridge channel,
And removing the Si _{1 - y} Ge _y layer from the preliminary channel pattern of the fin structure to form the bridge channel.
The method of claim 10,
Injecting the Ge,
The SiGe layer of the fin structure is converted to a Si _{1 - x} Ge _x layer, where x is greater than 0 and less than 1, and the Si layer is a Si _{1 - y} Ge _y layer, where y is greater than 0 And Ge is injected into the preliminary source pattern, the preliminary channel pattern, and the preliminary drain pattern of the fin structure to be converted to 1 or less but less than x).
Forming the bridge channel,
And removing the Si _{1 - y} Ge _y layer from the preliminary channel pattern of the fin structure to form the bridge channel.
The method of claim 10,
Between removing the dummy gate and forming the gate,
Forming a gate dielectric layer surrounding at least a portion of the bridge channel;
Method for manufacturing a tunneling field effect transistor, characterized in that it further comprises.

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