CN108962985B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
CN108962985B
CN108962985B CN201710350087.9A CN201710350087A CN108962985B CN 108962985 B CN108962985 B CN 108962985B CN 201710350087 A CN201710350087 A CN 201710350087A CN 108962985 B CN108962985 B CN 108962985B
Authority
CN
China
Prior art keywords
dielectric layer
layer
gate
dummy gate
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710350087.9A
Other languages
Chinese (zh)
Other versions
CN108962985A (en
Inventor
李勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710350087.9A priority Critical patent/CN108962985B/en
Publication of CN108962985A publication Critical patent/CN108962985A/en
Application granted granted Critical
Publication of CN108962985B publication Critical patent/CN108962985B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/785Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

The application discloses a semiconductor device and a manufacturing method thereof, and relates to the technical field of semiconductors. The device comprises: a substrate; a first fin on the substrate for a first device; a first gate structure over a portion of the first fin, comprising: a first gate dielectric layer on a portion of the first fin; and a first gate on the first gate dielectric layer; and a first source region and a first drain region at least partially in the first fin on both sides of the first gate structure; the first gate dielectric layer is adjacent to the first drain region and is a first part, the first gate dielectric layer is adjacent to the first source region and is a second part, the first gate dielectric layer is located between the first part and the second part and is a third part, and the thickness of the first part is larger than that of the third part. The GIDL of the device can be reduced.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present disclosure relates to semiconductor technologies, and more particularly, to a semiconductor device and a method for manufacturing the same.
Background
As the critical dimension of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is reduced, the Short Channel Effect (SCE) is more and more serious. A Fin Field Effect Transistor (FinFET) has good gate control capability, and can effectively suppress SCE.
However, the inventors of the present application have found that for some FinFET devices, such as input/output (I/O) devices, the gate-induced drain leakage current (GIDL) is relatively large, thereby affecting the reliability of the device.
Disclosure of Invention
It is an object of the present application to reduce GIDL of the device.
According to an aspect of the present application, there is provided a semiconductor device including: a substrate; a first fin on the substrate for a first device; a first gate structure over a portion of the first fin, comprising: a first gate dielectric layer on a portion of the first fin; and a first gate on the first gate dielectric layer; and a first source region and a first drain region at least partially in the first fin on both sides of the first gate structure; the first gate dielectric layer is adjacent to the first drain region and is a first part, the first gate dielectric layer is adjacent to the first source region and is a second part, the first gate dielectric layer is located between the first part and the second part and is a third part, and the thickness of the first part is larger than that of the third part.
In one embodiment, the thickness of the second portion is greater than the thickness of the third portion.
In one embodiment, the first gate dielectric layer includes: a first dielectric layer over a portion of the first fin; a first high-k dielectric layer on the first dielectric layer; and a first oxide layer under edges of the first dielectric layer, the first oxide layer embedded in the first fins.
In one embodiment, the first gate dielectric layer further comprises: a first oxide region underlying a portion between edges of the first dielectric layer and abutting the first oxide layer; wherein a thickness of the first oxide layer is greater than a thickness of the first oxide region.
In one embodiment, the first gate dielectric layer further comprises: a second oxide region between an edge of the first dielectric layer and the first high-k dielectric layer.
In one embodiment, the first gate dielectric layer further comprises: a third oxide region between the portion between the edges of the first dielectric layer and the first high-k dielectric layer and adjacent to the second oxide region; wherein a thickness of the second oxide region is greater than a thickness of the third oxide region.
In one embodiment, the apparatus further comprises: a second fin on the substrate for a second device; a second gate structure over a portion of the second fin, comprising: a second gate dielectric layer on a portion of the second fin; and a second gate on the second gate dielectric layer; and a second source region and a second drain region at least partially in the second fin on both sides of the second gate structure.
In one embodiment, the second gate dielectric layer comprises a second high-k dielectric layer.
In one embodiment, the first gate dielectric layer further comprises a first interface layer between the first dielectric layer and the first high-k dielectric layer.
In one embodiment, the second gate dielectric layer further includes a second interfacial layer between the portion of the second fin and the second high-k dielectric layer.
In one embodiment, the first device includes an input/output device and the second device includes a core device.
According to another aspect of the present application, there is provided a method of manufacturing a semiconductor device, including: providing a substrate structure, the substrate structure comprising: a substrate; a first fin on the substrate for a first device; and a first dummy gate structure on a portion of the first fin, the first dummy gate structure comprising a first dielectric layer on a portion of the first fin and a first dummy gate on the first dielectric layer; performing an etching process to remove a part of the first fin on the side surface of the first dummy gate structure so as to form a first recess and a second recess; performing an oxidation process to oxidize the surface of the first fin under the first recess and the second recess, thereby forming a first oxide layer; performing a selective removal process to selectively remove a portion of the first oxide layer, leaving a portion of the first oxide layer under an edge of the first dielectric layer; an epitaxial process is performed to epitaxially grow a semiconductor material in the first recess and the second recess to form a first source region and a first drain region.
In one embodiment, the first dummy gate structure further includes a first hard mask layer on the first dummy gate, the first spacer layer being on sidewalls of the first dummy gate and the first hard mask layer.
In one embodiment, the oxidation process further oxidizes a surface of the first fin under a portion between edges of the first dielectric layer, forming a first oxide region adjacent to the first oxide layer; the first oxidation zone is also retained after the selective removal process.
In one embodiment, the oxidation process further oxidizes the first dummy gate on the edge of the first dielectric layer, thereby forming a second oxide region; the second oxide region is also retained after the selective removal process.
In one embodiment, the oxidation process further causes the first dummy gate on the portion between the edges of the first dielectric layer to be oxidized, thereby forming a third oxide region adjacent to the second oxide region, the second oxide region having a thickness greater than a thickness of the third oxide region; the third oxidation zone is also retained after the selective removal process.
In one embodiment, a portion of the first oxide layer is selectively removed using hydrogen fluoride.
In one embodiment, the oxidation process comprises a rapid thermal oxidation process, a furnace oxidation process, or an in-situ steam generation process.
In one embodiment, the method further comprises: after the epitaxial process is carried out, depositing an interlayer dielectric layer and flattening to expose the first dummy gate; removing the first dummy gate to form a first trench for a first device; forming a first high-k dielectric layer on a bottom of the first trench; forming a first gate on the first high-k dielectric layer; wherein the first dielectric layer, the portion of the first oxide layer under the edge of the first dielectric layer, and the first high-k dielectric layer act as a first gate dielectric layer for a first gate.
In one embodiment, the substrate structure further includes a second fin on the substrate for a second device and a second dummy gate structure on a portion of the second fin, the second dummy gate structure including a second dielectric layer on a portion of the second fin and a second dummy gate on the second dielectric layer; the etching process also removes a part of the second fin on the side surface of the second pseudo gate structure to form a third recess and a fourth recess; the oxidation process also oxidizes the surfaces of the third recess and the second fin under the second recess, thereby forming a second oxide layer; the selective removal process also selectively removes a portion of the second oxide layer, leaving a portion of the second oxide layer under the edge of the second dielectric layer; the epitaxial process also epitaxially grows a semiconductor material in the third recess and the fourth recess, thereby forming a second source region and a second drain region.
In one embodiment, the method further comprises: after the epitaxial process is carried out, depositing an interlayer dielectric layer and flattening to expose the first dummy gate and the second dummy gate; removing the first dummy gate and the second dummy gate to form a first trench for a first device and a second trench for a second device; removing the second dielectric layer and the part of the second oxide layer, which is positioned below the edge of the second dielectric layer; forming a first high-k dielectric layer on the bottom of the first trench and a second high-k dielectric layer on the bottom of the second trench; forming a first gate on the first high-k dielectric layer and a second gate on the second high-k dielectric layer; wherein the first dielectric layer, the portion of the first oxide layer under the edge of the first dielectric layer, and the first high-k dielectric layer act as a first gate dielectric layer for a first gate, and the second high-k dielectric layer act as a second gate dielectric layer for the second gate.
In one embodiment, the method further comprises: forming a first interfacial layer on a bottom of the first trench, the first high-k dielectric layer being formed on the first interfacial layer; forming a second interfacial layer on a bottom of the second trench, the second high-k dielectric layer being formed on the second interfacial layer.
In one embodiment, the first device includes an input/output device and the second device includes a core device.
In the semiconductor device provided by the embodiment of the application, the thickness of the first gate dielectric layer adjacent to the first drain region is larger than that of the middle third portion, that is, the thickness of the first gate dielectric layer between the first drain region and the first gate overlapping portion is increased, so that the vertical electric field intensity is reduced, and the GIDL of the device is reduced.
Other features, aspects, and advantages of the present application will become apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the application and together with the description, serve to explain the principles of the application, and in which:
FIG. 1 is a simplified flow diagram of a method of fabricating a semiconductor device according to one embodiment of the present application;
2-6B illustrate schematic diagrams of various stages of a method of fabricating a semiconductor device according to one embodiment of the present application;
FIGS. 7A-10 show schematic diagrams of stages of a method of fabricating a semiconductor device according to another embodiment of the present application;
fig. 11-20 show schematic diagrams of stages of a method of manufacturing a semiconductor device according to yet another embodiment of the present application.
Detailed Description
Various exemplary embodiments of the present application will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments should not be construed as limiting the scope of the present application unless specifically stated otherwise.
Further, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual scale, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of exemplary embodiments is merely illustrative and is not intended to limit the application and its applications or uses in any way.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification as applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
The inventors of the present application have conducted intensive studies on the problem of large GIDL ratio of some FinFET devices, and found that: in the existing manufacturing process, a gate dielectric layer on the top of a fin is relatively thin, and a power supply voltage applied to some devices during operation is relatively high, for example, the power supply voltage of an I/O device is 1.8V, so that electric field lines on the top of the fin are relatively dense, and an electric field is relatively large, thereby causing the GIDL of the device to be relatively large. Accordingly, the inventors propose the following solution.
Fig. 1 is a simplified flow diagram of a method of fabricating a semiconductor device according to one embodiment of the present application. Fig. 2-6B show schematic diagrams of various stages of a method of fabricating a semiconductor device according to an embodiment of the present application.
A method for manufacturing a semiconductor device according to an embodiment of the present application will be described in detail with reference to fig. 1 and 2 to 6B.
As shown in fig. 1, first, in step 102, a substrate structure is provided.
As shown in fig. 2, the substrate structure includes a substrate 201, a first fin 202 on the substrate 201 for a first device, and a first dummy gate structure 203 on a portion of the first fin 202. Here, the first device may be, for example, an I/O device, however, the present application is not limited thereto. For example, the first device may also be an electrostatic discharge (ESD) protection device, an LDMOS (laterally diffused metal oxide semiconductor) device, or the like.
The first dummy gate structure 203 may include a first dielectric layer 213 on a portion of the first fin 202 and a first dummy gate 223 on the first dielectric layer 213. In addition, the first dummy gate structure 203 may further include a first hard mask layer 233 on the first dummy gate 223 and a first spacer layer 243 on sidewalls of the first dummy gate 223 and the first hard mask layer 233.
The substrate 201 may be, for example, a silicon substrate, a semiconductor substrate of a III-V material, or the like. The material of the first fins 202 may be the same semiconductor material as the material of the substrate 201, or may be a different semiconductor material from the material of the substrate 201. The first dummy gate 223 may be, for example, polysilicon. The first hard mask layer 233 may be typically a silicon nitride, a silicon oxide, a silicon oxynitride, or the like. The first spacer layer 243 may be, for example, silicon nitride or the like.
It should be noted that another dummy gate structure may be formed on one or both end portions of the first fin 202, and the dummy gate structure may be the same as the first dummy gate structure 203, see fig. 2. The dummy gate structure is beneficial for controlling the appearance of the first source region 207 and the first drain region 208 formed by epitaxy.
It is further noted that the substrate structure may further include an isolation structure, such as a Shallow Trench Isolation (STI) structure.
Next, in step 104, an etching process is performed to remove a portion of the first fin 202 at the side of the first dummy gate structure 203, thereby forming a first recess 215 and a second recess 225, as shown in fig. 3A and 3B. Fig. 3B is a sectional view taken along B-B' shown in fig. 3A. As can be seen from fig. 3B, a first dielectric layer 213 is formed on the surface of the portion of the first fin 202 above the isolation structure 204. Additionally, while fig. 3B shows the first spacer layer 243 on the first dielectric layer 213 at the sides of the first fins 202, it is to be understood that this is not required. In other embodiments, the first spacer layer 243 may not be on the first dielectric layer 213 at the sides of the first fins 202.
Thereafter, at step 106, an oxidation process is performed to oxidize the surface of the first fin 202 under the first recess 215 and the second recess 225, thereby forming the first oxide layer 206, as shown in fig. 4A and 4B. Fig. 4B is a sectional view taken along B-B' shown in fig. 4A.
In one embodiment, the oxidation process also causes the surface of the first fin 202 under the portion between the edges of the first dielectric layer 213 to be oxidized, thereby forming a first oxide region adjacent to the first oxide layer 206. In another embodiment, the oxidation process also oxidizes the first dummy gate 223 on the edge of the first dielectric layer 213, thereby forming a second oxide region. In yet another embodiment, the oxidation process further causes the first dummy gate 223 on the portion between the edges 213 of the first dielectric layer to be oxidized, thereby forming a third oxide region adjacent to the second oxide region, the second oxide region having a thickness greater than a thickness of the third oxide region.
In one embodiment, the oxidation process may include, but is not limited to, a Rapid Thermal Oxidation (RTO) process, a furnace oxidation process, or an in-situ steam generation process (ISSG), among others. After the oxidation process, the first oxide layer 206 is formed at the edges of the first dielectric layer 213, i.e., under the portions near the first recess 215 and the second recess 225.
Thereafter, in step 108, a selective removal process is performed to selectively remove a portion of the first oxide layer 206, leaving a portion of the first oxide layer 206 under the edges of the first dielectric layer 213, as shown in fig. 5A and 5B. Fig. 5B is a sectional view taken along B-B' shown in fig. 5A. In the case of forming the first, second or third region, the first, second or third region is also correspondingly retained after the selective removal process. For example, in the case of forming the first region, the first region remains after the selective removal process. In the case where the second region is formed, the second region remains after the selective removal process. In the case where the third region is formed, the third region is also left after the selective removal process.
Preferably, a portion of the first oxide layer 206 may be selectively removed using hydrogen fluoride. The effect of the anisotropy of the gaseous hydrogen fluoride on the removal of the first oxide layer 206 is significant, so that the portion of the first oxide layer 206 below the edges of the first dielectric layer 213 remains.
Thereafter, at step 110, an epitaxial process is performed to epitaxially grow a semiconductor material in the first recess 215 and the second recess 225 to form a first source region 207 and a first drain region 208, as shown in fig. 6A and 6B. Fig. 6B is a sectional view taken along B-B' shown in fig. 6A.
In one embodiment, the first device may be a PMOS device and the epitaxial semiconductor material may be SiGe. In another embodiment, the first device may be an NMOS device, the epitaxial semiconductor material may be Si, and P may be doped in-situ during the epitaxial Si.
The method of manufacturing the semiconductor device according to one embodiment of the present application is described above. In the method of this embodiment, after the first recess and the second recess are formed, an oxidation process is performed, so that a first oxide layer is formed under the edge of the first dielectric layer, and the first dielectric layer and the first oxide layer under the edge of the first dielectric layer are used as a gate dielectric layer for the dummy gate.
After the first source region 207 and the first drain region 208 are formed, the first dummy gate 223 may be replaced with, for example, a metal gate, and a method of manufacturing a semiconductor device according to another embodiment of the present application will be described below with reference to fig. 7A to 10.
First, as shown in fig. 7A and 7B, an interlayer dielectric layer 301 is deposited and planarized, for example, Chemical Mechanical Planarization (CMP), to expose the first dummy gate 223.
Next, as shown in fig. 8, the first dummy gate 223 is removed to form a first trench 302 for the first device. Here, the dummy gate in the dummy gate structure on the end portion of the first fin 202 may also be removed at the same time when the first dummy gate 223 is removed. Alternatively, only the first dummy gate 223 may be removed, leaving the dummy gate in the dummy gate structure on the end of the first fin 202.
Then, as shown in FIG. 9, at the bottom of the first trench 302 (i.e., the first trench)Dielectric layer 213) is formed on the first high-k dielectric layer 303. Preferably, a first interface layer (not shown) may be formed on the bottom of the first trench 302 first, and then the first high-k dielectric layer 303 may be formed on the first interface layer, so that the interface performance between the first high-k dielectric layer 303 and the first dielectric layer 213 may be improved. Additionally, a first high-k dielectric layer 303 may also be formed on the sidewalls of the first trench 302. Illustratively, the material of the first high-k dielectric layer 303 may include, but is not limited to: la2O3、TiO2、Ta2O5、ZrO2、BaZrO、HfO2HfZrO, HfZrON, HfLaO, HfSiO, HfSiON, LaSiO, AlSiO, HfTaO, HfTiO, or the like.
Thereafter, as shown in fig. 10, a first gate 304 is formed on the first high-k dielectric layer 303 to fill the first trench 302. Here, the material of the first gate electrode 304 may be aluminum, tungsten, or other metal materials. For example, a first gate material may be deposited over the structure shown in fig. 9, followed by a planarization process to form the first gate 304.
After forming the first high-k dielectric layer 303, the first dielectric layer 213, the portion of the first oxide layer 206 under the edge of the first dielectric layer 213, and the first high-k dielectric layer 303 collectively function as a gate dielectric layer for the first gate 304 (hereinafter referred to as a first gate dielectric layer). A portion of the first gate dielectric layer adjacent to the first drain region 208 may be referred to as a first portion, a portion of the first gate dielectric layer adjacent to the first source region 207 may be referred to as a second portion, and a portion of the first gate dielectric layer between the first portion and the second portion may be referred to as a third portion. The first and second portions have a thickness greater than a thickness of the third portion.
Thus, the method of this embodiment increases the thickness of the first gate dielectric layer between the overlapping portions of the first drain region 208 and the first gate electrode 304, thereby reducing the vertical electric field strength and reducing the GIDL of the first device, as compared to the prior art.
Fig. 11-20 show schematic diagrams of various stages of a method of manufacturing a semiconductor device according to yet another embodiment of the present application. The following description focuses only on the differences between this embodiment and the embodiment shown in fig. 2-6B, and other similarities may be referred to the above description.
First, as shown in fig. 11, a substrate structure is provided. The substrate structure may further include a second fin 402 for a second device on the substrate 201 and a second dummy gate structure 403 on a portion of the second fin 402, as compared to the substrate structure shown in fig. 2. In one embodiment, the second device may include a core device.
The second dummy gate structure 403 may include a second dielectric layer 413 on a portion of the second fin 402 and a second dummy gate 423 on the second dielectric layer 413. The second dummy gate structure may further include a second hard mask layer 443 on the second dummy gate 423 and a second spacer layer 443 on sidewalls of the second dummy gate 423 and the second hard mask layer 443. The second dummy gate structure 403 is similar to the first dummy gate structure 203, and the materials of the layers corresponding to each other may be the same, for example, the materials of the first dielectric layer 213 and the second dielectric layer 413 may be the same.
In addition, there may be another dummy gate structure on one or both ends of the second fin 402, which may be the same as the second dummy gate structure 403, and the dummy gate structure is beneficial to controlling the topography of the second source region 407 and the second drain region 408 formed by subsequent epitaxy.
Next, as shown in fig. 12, an etching process is performed. The etching process in this embodiment not only forms the first recess 215 and the second recess 225, but also removes a portion of the second fin 402 at the side of the second dummy gate structure 403 to form a third recess 415 and a fourth recess 425.
Then, as shown in fig. 13, an oxidation process is performed. The oxidation process in this embodiment not only forms the first oxide layer 206, but also oxidizes the surfaces of the second fin 402 under the third recess 415 and the second recess 425, thereby forming the second oxide layer 406. After the oxidation process, the first oxide layer 206 is formed at the edges of the first dielectric layer 213, i.e., under the portions near the first recess 215 and the second recess 225; the second oxide layer 206 is formed at the edges of the second dielectric layer 413, i.e., under the portions near the third recess 415 and the fourth recess 425.
Thereafter, as shown in fig. 14, a selective removal process is performed. The selective removal process in this embodiment selectively removes not only a portion of the first oxide layer 206, but also a portion of the second oxide layer 406, leaving a portion of the second oxide layer 406 under the edges of the second dielectric layer 413.
Thereafter, as shown in fig. 15, an epitaxial process is performed. The epitaxial process in this embodiment not only forms the first source region 207 and the first drain region 208, but also epitaxially grows a semiconductor material in the third recess 415 and the fourth recess 425, thereby forming the second source region 407 and the second drain region 408.
After forming the first source region 207, the first drain region 208, the second source region 407, and the second drain region 408, the first dummy gate 223 and the second dummy gate 423 may be further replaced with, for example, a metal gate, as described below in conjunction with fig. 16-20.
First, as shown in fig. 16, an interlayer dielectric layer 301 is deposited and planarized to expose the first and second dummy gates 223 and 423.
Then, as shown in fig. 17, the first and second dummy gates 223 and 423 are removed to form a first trench 302 for the first device and a second trench 502 for the second device.
Thereafter, as shown in fig. 18, the second dielectric layer 413 and the portion of the second oxide layer 406 underlying the edge of the second dielectric layer 413 are removed. It is understood that in some cases, a portion of the second dielectric layer 413 underlying the second spacer layer 443 may remain.
Thereafter, as shown in fig. 19, a first high-k dielectric layer 303 is formed on the bottom of first trench 302, and a second high-k dielectric layer 503 is formed on the bottom of second trench 502. The material of the second high-k dielectric layer 503 may be similar to the example described above with reference to the material of the first high-k dielectric layer 303. Preferably, a first interface layer (not shown) may be formed on the bottom of the first trench 302, and then the first high-k dielectric layer 303 may be formed on the first interface layer. Preferably, a second interface layer 505 may be formed on the bottom of the second trench 502 and then a second high-k dielectric layer 503 may be formed on the second interface layer 505. In addition, a first high-k dielectric layer 303 may also be formed on the sidewalls of first trench 302 and a second high-k dielectric layer 503 may also be formed on the sidewalls of second trench 502.
Thereafter, as shown in fig. 20, a first gate 304 is formed on the first high-k dielectric layer 303 to fill the first trench 302. A second gate 504 is formed on second high-k dielectric layer 503 to fill second trench 502. The material of the second gate 504 may be the same metal material as the material of the first gate 304.
The method of this embodiment forms two devices simultaneously, first dielectric layer 213, the portion of first oxide layer 206 under the edge of first dielectric layer 213, and first high-k dielectric layer 303 as the gate dielectric layer for first gate 304 (referred to as the first gate dielectric layer), and second high-k dielectric layer 503 as the gate dielectric layer for second gate 504 (referred to as the second gate dielectric layer). This embodiment increases the thickness of the first gate dielectric layer between the overlapping portions of first drain region 208 and first gate 304, thereby reducing the vertical electric field strength and reducing the GIDL of the first device, as compared to the prior art.
The present application also provides a semiconductor device including:
the substrate 201 is, for example, a silicon substrate or the like.
A first fin 202 for a first device (e.g., an I/O device) on a substrate 201.
A first gate structure over a portion of the first fin 202, the first gate structure including a first gate dielectric layer over a portion of the first fin 202 and a first gate 304 over the first gate dielectric layer. The first gate structure may further include a first spacer layer 243 on sidewalls of the first gate 304.
A first source region 207 and a first drain region 208 at least partially in the first fin 202 on either side of the first gate structure. The first source region 207 and the first drain region 208 may be partially located in the first fin 202, and other portions may protrude from the first fin 202, that is, the first source region 207 and the first drain region 208 are raised active regions. Alternatively, the first source region 207 and the first drain region 208 may also be entirely located in the first fin 202.
Here, a portion of the first gate dielectric layer adjacent to the first drain region 208 is a first portion, a portion of the first gate dielectric layer adjacent to the first source region 207 is a second portion, and a portion of the first gate dielectric layer between the first portion and the second portion is a third portion. The thickness of the first portion is greater than the thickness of the third portion, or the thickness of both the first portion and the second portion is greater than the thickness of the third portion.
It is to be understood that the first portion, the second portion and the third portion are relative concepts, where the first portion and the second portion may be understood as end portions of the first gate dielectric layer and the third portion may be an intermediate portion located between the two end portions.
In one implementation, referring to fig. 10, the first gate dielectric layer may include a first dielectric layer 213 on a portion of the first fin 202, a first high-k dielectric layer 303 on the first dielectric layer 213, and a first oxide layer 206 under edges of the first dielectric layer 213.
In another implementation, the first gate dielectric layer may further include: a first oxide region under a portion between edges of the first dielectric layer 213, the first oxide region abutting the first oxide layer 206 under the edges of the first dielectric layer 213. Here, the thickness of the first oxide layer 206 is greater than the thickness of the first oxide region.
In another implementation, the first gate dielectric layer may further include: a second oxide region between the edge of first dielectric layer 213 and first high-k dielectric layer 303.
In yet another implementation, the first gate dielectric layer may include, in addition to the second oxide region: a third oxide region between the portion between the edges of the first dielectric layer 213 and the first high-k dielectric layer 303, which third oxide region adjoins the second oxide region and which second oxide region has a thickness which is larger than the thickness of the third oxide region.
Preferably, the first gate dielectric layer may further include a first interface layer between the first dielectric layer 213 and the first high-k dielectric layer 303. In addition, a first high-k dielectric layer 303 may also be present between the first gate 304 and the first spacer layer 243.
Here, the first oxide layer 206 may be formed by oxidizing the surface of the first fin 202, so the first oxide layer 206 may be embedded in the first fin 202, and the upper surface of the first oxide layer 206 is in contact with the first dielectric layer 213. The thickness of the end portions of the first gate dielectric layer is greater than the thickness of the middle portion due to the presence of the first oxide layer 206.
The present application also provides another semiconductor device, and referring to fig. 20, in contrast to the embodiment shown in fig. 10, the device of the embodiment shown in fig. 20 further includes a second fin 402 for a second device (e.g., a core device) on the substrate 201, a second gate structure on a portion of the second fin 402, and a second source region 407 and a second drain region 408 at least partially in the second fin on both sides of the second gate structure.
The second gate structure may include a second gate dielectric layer (which may be, for example, a second high-k dielectric layer 503) on a portion of the second fin 402 and a second gate 504 on the second gate dielectric layer. The second gate structure may further include a second spacer layer 443 on sidewalls of the second gate 504. In addition, a second high-k dielectric layer 503 may also be provided between the second gate 504 and the second spacer layer 443. The second gate dielectric layer may also include a second interface layer 505 between the surface of the portion of the second fin 402 and the second high-k dielectric layer 503.
Thus far, the semiconductor device and the manufacturing method thereof according to the embodiment of the present application have been described in detail. Some details which are well known in the art have not been described in order to avoid obscuring the concepts of the present application, and it will be fully apparent to those skilled in the art from the above description how the technical solutions disclosed herein may be implemented. In addition, the embodiments taught by the present disclosure can be freely combined. It will be appreciated by persons skilled in the art that numerous modifications may be made to the embodiments described above without departing from the spirit and scope of the present application as defined by the appended claims.

Claims (12)

1. A method for manufacturing a semiconductor device, comprising:
providing a substrate structure, the substrate structure comprising:
a substrate;
a first fin on the substrate for a first device; and
a first dummy gate structure on a portion of the first fin, the first dummy gate structure comprising a first dielectric layer on a portion of the first fin and a first dummy gate on the first dielectric layer;
performing an etching process to remove a part of the first fin on the side surface of the first dummy gate structure so as to form a first recess and a second recess;
performing an oxidation process to oxidize the surface of the first fin under the first recess and the second recess, thereby forming a first oxide layer;
performing a selective removal process to selectively remove a portion of the first oxide layer, leaving a portion of the first oxide layer under an edge of the first dielectric layer;
an epitaxial process is performed to epitaxially grow a semiconductor material in the first recess and the second recess to form a first source region and a first drain region.
2. The method of claim 1, wherein the first dummy gate structure further comprises a first hard mask layer on the first dummy gate and a first spacer layer on sidewalls of the first dummy gate and the first hard mask layer.
3. The method of claim 1, wherein the oxidation process further oxidizes a surface of the first fin under portions between edges of the first dielectric layer to form a first oxide region adjacent to the first oxide layer;
the first oxidation zone is also retained after the selective removal process.
4. The method of claim 1 or 3, wherein the oxidation process further oxidizes the first dummy gate on the edge of the first dielectric layer to form a second oxide region;
the second oxide region is also retained after the selective removal process.
5. The method of claim 4, wherein the oxidation process further causes the first dummy gate on the portion between the edges of the first dielectric layer to be oxidized, thereby forming a third oxide region adjacent to the second oxide region, the second oxide region having a thickness greater than a thickness of the third oxide region;
the third oxidation zone is also retained after the selective removal process.
6. The method of claim 1, wherein a portion of the first oxide layer is selectively removed using hydrogen fluoride.
7. The method of claim 1, wherein the oxidation process comprises a rapid thermal oxidation process, a furnace oxidation process, or an in situ steam generation process.
8. The method of claim 1, further comprising:
after the epitaxial process is carried out, depositing an interlayer dielectric layer and flattening to expose the first dummy gate;
removing the first dummy gate to form a first trench for a first device;
forming a first high-k dielectric layer on a bottom of the first trench;
forming a first gate on the first high-k dielectric layer;
wherein the first dielectric layer, the portion of the first oxide layer under the edge of the first dielectric layer, and the first high-k dielectric layer act as a first gate dielectric layer for a first gate.
9. The method of claim 1, wherein the substrate structure further comprises a second fin on the substrate for a second device and a second dummy gate structure on a portion of the second fin, the second dummy gate structure comprising a second dielectric layer on a portion of the second fin and a second dummy gate on the second dielectric layer;
the etching process also removes a part of the second fin on the side surface of the second pseudo gate structure to form a third recess and a fourth recess;
the oxidation process also oxidizes surfaces of the second fins under the third recess and the fourth recess, thereby forming a second oxide layer;
the selective removal process also selectively removes a portion of the second oxide layer, leaving a portion of the second oxide layer under the edge of the second dielectric layer;
the epitaxial process also epitaxially grows a semiconductor material in the third recess and the fourth recess, thereby forming a second source region and a second drain region.
10. The method of claim 9, further comprising:
after the epitaxial process is carried out, depositing an interlayer dielectric layer and flattening to expose the first dummy gate and the second dummy gate;
removing the first dummy gate and the second dummy gate to form a first trench for a first device and a second trench for a second device;
removing the second dielectric layer and the part of the second oxide layer, which is positioned below the edge of the second dielectric layer;
forming a first high-k dielectric layer on the bottom of the first trench and a second high-k dielectric layer on the bottom of the second trench;
forming a first gate on the first high-k dielectric layer and a second gate on the second high-k dielectric layer;
wherein the first dielectric layer, the portion of the first oxide layer under the edge of the first dielectric layer, and the first high-k dielectric layer act as a first gate dielectric layer for a first gate, and the second high-k dielectric layer act as a second gate dielectric layer for the second gate.
11. The method of claim 10, further comprising:
forming a first interfacial layer on a bottom of the first trench, the first high-k dielectric layer being formed on the first interfacial layer;
forming a second interfacial layer on a bottom of the second trench, the second high-k dielectric layer being formed on the second interfacial layer.
12. The method of claim 9, wherein the first device comprises an input/output device and the second device comprises a core device.
CN201710350087.9A 2017-05-18 2017-05-18 Semiconductor device and method for manufacturing the same Active CN108962985B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710350087.9A CN108962985B (en) 2017-05-18 2017-05-18 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710350087.9A CN108962985B (en) 2017-05-18 2017-05-18 Semiconductor device and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN108962985A CN108962985A (en) 2018-12-07
CN108962985B true CN108962985B (en) 2021-11-05

Family

ID=64461681

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710350087.9A Active CN108962985B (en) 2017-05-18 2017-05-18 Semiconductor device and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN108962985B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108962986B (en) * 2017-05-18 2021-07-06 中芯国际集成电路制造(上海)有限公司 Semiconductor device and method for manufacturing the same
CN111755336B (en) * 2019-03-28 2024-05-14 中芯国际集成电路制造(上海)有限公司 Preparation method of field effect transistor, field effect transistor and semiconductor substrate
KR20200136688A (en) * 2019-05-28 2020-12-08 삼성전자주식회사 Semiconductor device and method of fabricating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281006A (en) * 2006-04-03 2007-10-25 Seiko Epson Corp Semiconductor device and its manufacturing method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9412667B2 (en) * 2014-11-25 2016-08-09 International Business Machines Corporation Asymmetric high-k dielectric for reducing gate induced drain leakage

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007281006A (en) * 2006-04-03 2007-10-25 Seiko Epson Corp Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
CN108962985A (en) 2018-12-07

Similar Documents

Publication Publication Date Title
US9812559B2 (en) FINFET semiconductor devices and method of forming the same
US9184053B2 (en) Semiconductor device and method of manufacturing the same
US9397184B2 (en) Semiconductor device having metal gate and manufacturing method thereof
US9318609B2 (en) Semiconductor device with epitaxial structure
US8853013B2 (en) Method for fabricating field effect transistor with fin structure
US8343872B2 (en) Method of forming strained structures with compound profiles in semiconductor devices
JP5126930B2 (en) Manufacturing method of semiconductor device
TWI668866B (en) Semiconductor device and method for fabricating the same
CN108962986B (en) Semiconductor device and method for manufacturing the same
CN110034015B (en) Method for forming nanowire fence device
CN104051460A (en) Semiconductor device including dummy isolation gate structure and method of fabricating thereof
US11038039B2 (en) Method of forming a semiconductor device
CN105513967A (en) Transistor forming method
CN108962985B (en) Semiconductor device and method for manufacturing the same
CN103390637B (en) FinFET and manufacturing method thereof
KR20190114695A (en) Tunneling field-effect transistor and method for manufacturing thereof
US10658512B2 (en) Fin field effect transistor and fabrication method thereof
CN105633152B (en) Semiconductor structure and manufacturing method thereof
JP2016157798A (en) Semiconductor device
US20150084137A1 (en) Mechanism for forming metal gate structure
JP2004247341A (en) Semiconductor device
CN111463275B (en) Semiconductor structure and forming method thereof
TWI543370B (en) Mos transistor process
TW201448120A (en) Semiconductor device and fabrication method thereof
US20230162983A1 (en) Semiconductor devices with metal intercalated high-k capping

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant