CN117673118A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: a substrate including a first region and a second region; the first fin structure is positioned in the first region and comprises a plurality of first channel layers; the second fin structure is positioned in the second region and comprises a separation channel layer and a second channel layer, the second channel layer is made of silicon germanium doped with second doping ions, and the second doping ions are respectively different from the third doping ions and the first doping ions in electrical type. The second channel layer of the silicon germanium material is used as a channel region of the PMOS transistor, so that the requirement of the PMOS transistor on the hole mobility is met. By additionally arranging the isolating channel layer, the doping concentration of the third doping ions in the isolating channel layer enables the isolating channel layer not to be conducted when the transistor works, and therefore the problem of electric leakage at the bottom of the PMOS transistor is reduced. When the first grid structure is formed, damage to the grid structure of the second channel layer is avoided, and influence on the threshold voltage of the PMOS transistor is reduced.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Metal-oxide-semiconductor field effect transistors (MOSFETs) are one of the most important elements in modern integrated circuits, the basic structure of a MOSFET comprising: a semiconductor substrate; a gate structure on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; source and drain doped regions in the semiconductor substrate on both sides of the gate structure.

With the development of semiconductor technology, the control capability of a conventional planar MOSFET on channel current becomes weak, resulting in serious leakage current. Fin field effect transistors (Fin FETs) are an emerging type of multi-gate device that generally include a Fin protruding from a semiconductor substrate surface, a gate structure covering a portion of the top surface and sidewalls of the Fin, and source-drain doped regions in the Fin on either side of the gate structure. Compared with a planar MOSFET, the fin field effect transistor has stronger short channel inhibition capability and stronger working current.

With further development of semiconductor technology, conventional finfet has a limitation in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a MOSFET of a Gate All Around (GAA) structure is proposed, so that the volume for serving as a channel region is increased, further increasing the operating current of the GAA structure MOSFET.

However, there are still a number of problems in the device structure of GAA in the prior art.

Disclosure of Invention

The invention solves the technical problem of providing a semiconductor structure and a forming method thereof so as to improve the performance of the finally formed semiconductor structure.

In order to solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate comprising a first region and a second region; the first fin structure is positioned on the first region and comprises a plurality of layers of first channel layers which are overlapped and arranged along the normal direction of the surface of the substrate, and the first channel layers are made of silicon doped with first doping ions or undoped silicon; the second fin structure is located on the second region and comprises a separation channel layer and a plurality of second channel layers located on the separation channel layer, the separation channel layer and the second channel layers are overlapped and distributed along the normal direction of the surface of the substrate, silicon germanium doped with second doping ions is adopted as materials in the second channel layer, silicon doped with third doping ions is adopted as materials in the separation channel layer, the second doping ions are respectively different from the third doping ions and the first doping ions in electrical type, the third doping ions are the same as the first doping ions in electrical type, the first doping ions and the third doping ions are different ions in electrical type, and the doping concentration of the third doping ions in the separation channel layer enables the separation channel layer not to be conducted when the transistor works.

Optionally, the first doped ion is an N-type ion; the second doping ions are P-type ions; the third doped ion is an N-type ion.

Optionally, the method further comprises: a first gate structure located on the substrate across the first fin structure, the first gate structure surrounding the first channel layer; and a second gate structure on the substrate and crossing the second fin structure, wherein the second gate structure surrounds the isolation channel layer and the second channel layer.

Optionally, the method further comprises: an isolation trench located within the substrate; and the top surface of the isolation layer is flush with the bottom surface of the isolation channel layer.

Optionally, the method further comprises: the first source-drain doping layer is positioned in the first fin structure, and first source-drain ions are arranged in the first source-drain doping layer; and the second source-drain doping layer is positioned in the second fin structure, second source-drain ions are arranged in the second source-drain doping layer, and the electrical types of the first source-drain ions and the second source-drain ions are different.

Optionally, the first source-drain ions are N-type ions; and the second source-drain ions are P-type ions.

Optionally, the method further comprises: the side walls are positioned on the side walls of the first grid electrode structure and the second grid electrode structure; a first barrier layer between the first channel layer and the substrate, and between adjacent first channel layers; and a second barrier layer positioned between adjacent ones of the blocking channel layer and the second channel layer, and adjacent ones of the second channel layer.

Optionally, the method further comprises: and the dielectric layer is positioned on the substrate and covers the first grid electrode structure, the second grid electrode structure and the side wall, and the dielectric layer exposes the top surfaces of the first grid electrode structure, the second grid electrode structure and the side wall.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a first region and a second region; forming a first fin structure on the first region, wherein the first fin structure comprises a plurality of layers of first channel layers which are overlapped and arranged along the normal direction of the surface of the substrate, and the first channel layers are made of silicon doped with first doping ions or undoped silicon; and forming a second fin structure on the second region, wherein the second fin structure comprises a partition channel layer and a plurality of second channel layers positioned on the partition channel layer, the partition channel layer and the plurality of second channel layers are overlapped and distributed along the normal direction of the surface of the substrate, the material of the second channel layer adopts silicon germanium doped with second doping ions, the material of the partition channel layer adopts silicon doped with third doping ions, the second doping ions are respectively different from the third doping ions and the first doping ions in electrical type, the third doping ions are the same as the first doping ions in electrical type, the first doping ions and the third doping ions are different ions in electrical type, and the doping concentration of the third doping ions in the partition channel layer enables the partition channel layer not to be conducted when the transistor works.

Optionally, the first doped ion is an N-type ion; the second doping ions are P-type ions; the third doped ion is an N-type ion.

Optionally, after forming the first fin structure and the second fin structure, the method further includes: forming a first gate structure on the substrate across the first fin structure, the first gate structure surrounding the first channel layer; a second gate structure is formed on the substrate across the second fin structure, the second gate structure surrounding the blocking channel layer and the second channel layer.

Optionally, before forming the first fin structure and the second fin structure, the method further includes: and forming a partition channel material layer, a plurality of first channel material layers and a plurality of second channel material layers on the substrate, wherein the first channel material layers are positioned between adjacent partition channel material layers and the second channel material layers or between adjacent second channel material layers.

Optionally, after forming the partition channel material layer, the first channel material layer, and the second channel material layer, the method further includes: and carrying out graphical processing on the isolating channel material layer, the first channel material layers and the second channel material layers to form a first initial fin structure and a second initial fin structure, wherein the first initial fin structure comprises the isolating channel layer, the first channel layers and the second channel layers, the first channel layers are adjacent to each other, the isolating channel layers and the second channel layers are adjacent to each other, or the second channel layers are adjacent to each other, the second initial fin structure comprises the isolating channel layers, the first channel layers and the second channel layers, and the first channel layers are adjacent to each other, or the second channel layers are adjacent to each other.

Optionally, during the patterning process, the method further includes: etching the substrate to form an isolation trench in the substrate; after the patterning process, further comprising: an isolation layer is formed within the isolation trench, a top surface of the isolation layer being flush with a bottom surface of the isolation channel layer.

Optionally, after forming the first initial fin structure and the second initial fin structure, the method further includes: forming a dummy gate structure on the substrate, wherein the dummy gate structure spans the first initial fin structure and the second initial fin structure; forming a side wall material layer on the side wall and the top surface of the pseudo gate structure; forming a first patterned layer on the substrate, wherein the first patterned layer exposes the side wall material layer on the second region; etching the side wall material layer by taking the first patterned layer as a mask until the top surface of the pseudo gate structure is exposed, and forming a side wall on the side wall of the pseudo gate structure in the second region; etching the second initial fin structure by taking the first patterning layer, the pseudo gate structure and the side wall which are positioned on the second region as masks, and forming a second source drain opening in the second initial fin structure; etching part of the first channel layer exposed by the second source drain opening to form a second groove; removing the first patterning layer; depositing a second barrier film over the first region and the second region after removing the first patterned layer; forming a second patterned layer on the substrate, the second patterned layer exposing the second barrier film on the second region; etching the second barrier layer film by taking the second patterned layer as a mask, and forming a second barrier layer in the second groove; removing the second patterned layer after forming the second barrier layer; forming a second source-drain doping layer in the second source-drain opening after removing the second patterning layer, wherein second source-drain ions are arranged in the second source-drain doping layer; forming a third patterned layer on the substrate after forming the second source-drain doped layer, wherein the third patterned layer exposes the side wall material layer and the second barrier layer film on the first region; etching the side wall material layer and the second barrier layer film by taking the third patterned layer as a mask until the top surface of the pseudo gate structure is exposed, and forming a side wall on the side wall of the pseudo gate structure in the first region; etching the first initial fin structure by taking the third graphical layer, the pseudo gate structure and the side wall which are positioned on the first region as masks, and forming a first source drain opening in the first initial fin structure; etching part of the isolation channel layer and part of the second channel layer exposed by the first source drain opening to form a first groove; removing the third patterned layer; depositing a first barrier film over the first region and the second region after removing the third patterned layer; forming a fourth patterned layer on the substrate, the fourth patterned layer exposing the first barrier film on the first region; etching the first barrier layer film by taking the fourth patterned layer as a mask, and forming a first barrier layer in the first groove; removing the fourth patterned layer after forming the first barrier layer; forming a first source-drain doping layer in the first source-drain opening after removing the fourth patterning layer, wherein first source-drain ions are arranged in the first source-drain doping layer, and the electrical types of the first source-drain ions and the second source-drain ions are different; cleaning and removing the first barrier layer film on the second source-drain doping layer; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the pseudo gate structure, the side wall, the first source drain doping layer and the second source drain doping layer, and the dielectric layer exposes the top surfaces of the pseudo gate structure and the side wall.

Optionally, the first source-drain ions are N-type ions; and the second source-drain ions are P-type ions.

Optionally, the forming method of the first fin structure and the second fin structure includes: forming a fifth patterned layer on the dielectric layer, wherein the fifth patterned layer exposes the top surface of the pseudo gate structure on the second region; removing the pseudo gate structure on the second region by taking the fifth patterned layer as a mask to form a second gate opening; removing the first channel layer exposed by the second gate opening after the second gate opening is formed, and forming a second gate groove and the second fin structure; removing the fifth patterned layer after the second fin structure is formed, and forming a sixth patterned layer on the dielectric layer, wherein the sixth patterned layer exposes the top surface of the pseudo gate structure on the first region; removing the pseudo gate structure on the first region by taking the sixth patterned layer as a mask to form a first gate opening; removing the isolation channel layer and the second channel layer exposed by the first gate opening after the first gate opening is formed, and forming a first gate groove and the first fin structure; and removing the sixth patterning layer after the second fin structure is formed.

Optionally, the forming method of the first gate structure and the second gate structure includes: forming a gate oxide layer in the first gate opening, the first gate groove, the second gate opening and the second gate groove, wherein the gate oxide layer surrounds the first channel layer, the isolation channel layer and the second channel layer; forming a second grid work function layer on the surface of the grid oxide layer; forming a seventh patterned layer on the substrate, the seventh patterned layer exposing the second gate work function layer located on the first region; removing the second grid work function layer on the first region by taking the seventh patterned layer as a mask; removing the seventh patterned layer; forming a first gate work function layer on the surface of the gate oxide layer of the first region and the surface of the second gate work function layer of the second region; forming a gate material layer on the first gate work function layer and the dielectric layer; and flattening the gate material layer until the surface of the dielectric layer is exposed, forming a gate layer, forming a first gate structure by the gate oxide layer, the first gate work function layer and the gate layer which are positioned in the first region, and forming a second gate structure by the gate oxide layer, the first gate work function layer, the second gate work function layer and the gate layer which are positioned in the second region.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the semiconductor structure of the technical scheme of the invention, the second channel layer of the silicon germanium material with the second doping ions is used as the channel region of the PMOS transistor, so that the requirement of the PMOS transistor on the hole mobility can be met, and the performance of the finally formed semiconductor structure is further effectively improved. By additionally arranging the isolation channel layer, the isolation channel layer is made of silicon doped with third doping ions, and the third doping ions are opposite to the second doping ions in the second channel layer in electrical type, so that parasitic transistors formed at the bottom of the PMOS transistor are opposite to the PMOS transistor in type, and the problem of electric leakage at the bottom of the PMOS transistor is effectively reduced.

According to the method for forming the semiconductor structure, disclosed by the invention, the second channel layer of the silicon germanium material with the second doping ions is used as the channel region of the PMOS transistor, so that the requirement of the PMOS transistor on the hole mobility can be met, and the performance of the finally formed semiconductor structure is further effectively improved. By additionally arranging the isolation channel layer, the isolation channel layer is made of silicon doped with third doping ions, and the third doping ions are opposite to the second doping ions in the second channel layer in electrical type, so that parasitic transistors formed at the bottom of the PMOS transistor are opposite to the PMOS transistor in type, and the problem of electric leakage at the bottom of the PMOS transistor is effectively reduced. And the isolation channel layer is positioned below the second channel layer, so that when the first grid structure is formed subsequently, only the second grid structure coated on the isolation channel layer is damaged, and the second grid structure coated on the second channel layer is not damaged, thereby reducing the influence on the threshold voltage of the PMOS transistor and improving the performance of the finally formed semiconductor structure.

Further, the forming method of the first gate structure and the second gate structure includes: forming a gate oxide layer in the first gate opening, the first gate groove, the second gate opening and the second gate groove, wherein the gate oxide layer surrounds the first channel layer, the isolation channel layer and the second channel layer; forming a second grid work function layer on the surface of the grid oxide layer; forming a seventh patterned layer on the substrate, the seventh patterned layer exposing the second gate work function layer located on the first region; removing the second grid work function layer on the first region by taking the seventh patterned layer as a mask; removing the seventh patterned layer; forming a first gate work function layer on the surface of the gate oxide layer of the first region and the surface of the second gate work function layer of the second region; forming a gate material layer on the first gate work function layer and the dielectric layer; and flattening the gate material layer until the surface of the dielectric layer is exposed, forming a gate layer, forming a first gate structure by the gate oxide layer, the first gate work function layer and the gate layer which are positioned in the first region, and forming a second gate structure by the gate oxide layer, the first gate work function layer, the second gate work function layer and the gate layer which are positioned in the second region. Because the isolation channel layer is positioned below the second channel layer, when the second gate work function layer positioned on the first region is etched, only the second gate work function layer coating the isolation channel layer is damaged, and the second gate work function layer coating the second channel layer is not damaged, so that the influence on the threshold voltage of the PMOS transistor is reduced, and the performance of the finally formed semiconductor structure is improved.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

fig. 2 to 19 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As described in the background, there are still many problems in the device structure of GAA in the prior art. The following will make a detailed description with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a semiconductor structure.

Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes a first region I and a second region II adjacent to each other; forming a first fin structure parallel to the surface direction of the substrate 100 on the first region I, wherein the first fin structure comprises a plurality of layers of first channel layers 101 which are arranged at intervals along the surface normal direction of the substrate 100, and forming a second fin structure parallel to the surface direction of the substrate 100 on the second region II, and the second fin structure comprises a plurality of layers of second channel layers 102 which are arranged at intervals along the surface normal direction of the substrate; forming a first gate structure 103 on the substrate 100 across the first fin structure, the first gate structure 103 surrounding the first channel layer 101; a second gate structure 104 is formed on the substrate 100 across the second fin structure, the second gate structure 104 surrounding the second channel layer 102.

In this embodiment, the first fin structure is used to form an NMOS transistor, and the second fin structure is used to form a PMOS transistor. The PMOS transistor has a higher requirement for hole mobility in the second channel layer 102, but the hole mobility is lower along the (100) crystal direction of the second channel layer, which cannot meet the requirement of the PMOS transistor for hole mobility. In addition, since the first gate structure 103 and the second gate structure 104 also cover a portion of the substrate 100, parasitic transistors (as shown in a portion a of fig. 1) are formed at bottoms of the NMOS transistor and the PMOS transistor, which is liable to cause a leakage problem.

In this embodiment, the first patterning layer (not shown) is first used to cover the first fin structure, and the second gate structure 104 is deposited to form the PMOS transistor, because of the formation process of the first gate structure 103 and the second gate structure 104. After the PMOS transistor is formed, the formed PMOS transistor is covered with a second patterned layer (not shown), and the first gate structure 103 is deposited to form an NMOS transistor. The dummy gate structure (not shown) on the first region I needs to be removed before forming the first gate structure 103. However, during the process of removing the dummy gate structure in the first region I, damage may be caused to the second gate structure 104 (specific gate dielectric layer) to be formed, thereby affecting the threshold voltage of the PMOS transistor and reducing the performance of the finally formed semiconductor structure.

On the basis, the invention provides a semiconductor structure and a forming method thereof, wherein the material of the first channel layer is different from that of the second channel layer, and the second channel layer of the silicon germanium material with second doping ions is used as a channel region of a PMOS transistor, so that the requirement of the PMOS transistor on the hole mobility can be met, and the performance of the finally formed semiconductor structure is further effectively improved. By additionally arranging the isolation channel layer, the isolation channel layer is made of silicon doped with third doping ions, and the third doping ions are opposite to the second doping ions in the second channel layer in electrical type, so that parasitic transistors formed at the bottom of the PMOS transistor are opposite to the PMOS transistor in type, and the problem of electric leakage at the bottom of the PMOS transistor is effectively reduced. And the isolation channel layer is positioned below the second channel layer, so that when the first grid structure is formed subsequently, only the second grid structure coated on the isolation channel layer is damaged, and the second grid structure coated on the second channel layer is not damaged, thereby reducing the influence on the threshold voltage of the PMOS transistor and improving the performance of the finally formed semiconductor structure.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 2 to 19 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 2, a substrate 200 is provided, the substrate 200 including a first region I and a second region II.

The material of the substrate 200 may be silicon or silicon germanium; in this embodiment, the substrate 200 is made of silicon.

After providing the substrate 200, further comprising: and forming a first fin structure on the first region I and forming a second fin structure on the second region. The specific process is shown in fig. 3 to 19.

Referring to fig. 3, a separation channel material layer 201, a plurality of first channel material layers 202 and a plurality of second channel material layers 203 are formed on the substrate 200, wherein the first channel material layers 202 are located between adjacent separation channel material layers 201 and second channel material layers 203 or between adjacent second channel material layers 203.

In this embodiment, in the process of forming the partition channel material layer 201 and the first channel material layer 202, it further includes: doping first doping ions in the first channel material layer 202; doping second doping ions in the second channel material layer 203; doping first upper doping ions in the isolation channel material layer 201; the second dopant ions are of a different electrical type than the first dopant ions, and the third dopant ions are of the same electrical type as the first dopant ions.

In other embodiments, the first channel material layer may also be undoped with any dopant ions.

In this embodiment, the first doped ion is an N-type ion; the second doping ions are P-type ions; the third doping ion is an N-type ion, and the first doping ion and the third doping ion are different N-type ions.

Referring to fig. 4, the isolation channel material layer 201, the first channel material layers 202, and the second channel material layers 203 are patterned to form a first initial fin structure and a second initial fin structure.

In this embodiment, the first initial fin structure includes the blocking channel layer 204, a plurality of first channel layers 205, and a plurality of second channel layers 206, the first channel layers 205 are located between adjacent blocking channel layers 204 and second channel layers 206, or between adjacent second channel layers 206, the second initial fin structure includes the blocking channel layers 204, a plurality of first channel layers 205, and a plurality of second channel layers 206, and the first channel layers 205 are located between adjacent blocking channel layers 204 and second channel layers 206, or between adjacent second channel layers 206.

In this embodiment, the material of the first channel layer 205 is silicon doped with the first doping ions; the material of the second channel layer is silicon germanium doped with second doping ions, and the material of the isolating channel layer is silicon doped with third doping ions.

In other embodiments, the first channel layer may also be undoped with any dopant ions.

In this embodiment, the material of the second channel layer 206 is silicon germanium doped with the second doping ions, and the silicon germanium material has high hole mobility, which is typically 6-25 times that of the silicon material, so that the performance of the device can be greatly improved by using the silicon germanium material as the channel region material of the PMOS transistor.

In this embodiment, during the patterning process, the method further includes: the substrate 200 is etched to form isolation trenches 207 within the substrate 200.

Referring to fig. 5, after the patterning process, the method further includes: an isolation layer 208 is formed within the isolation trench 207, a top surface of the isolation layer 208 being flush with a bottom surface of the isolation channel layer 204.

In this embodiment, the method for forming the isolation layer 208 includes: forming an isolation material layer (not shown) within the isolation trench 207 and on the substrate 200, the isolation material layer covering the first and second initial fin structures; flattening the isolation material layer until the top surfaces of the first initial fin structure and the second initial fin structure are exposed, and forming an initial isolation layer (not shown); the initial isolation layer is etched back to form the isolation layer 208.

In this embodiment, the isolation layer 208 is made of silicon oxide.

Referring to fig. 6, a dummy gate structure 209 is formed on the substrate 200 to cross the first initial fin structure and the second initial fin structure adjacent to each other.

In this embodiment, the dummy gate structure 209 includes: the semiconductor device comprises a dummy gate dielectric layer and a dummy gate layer (not labeled) positioned on the dummy gate dielectric layer.

In this embodiment, the material of the dummy gate dielectric layer is silicon oxide.

In this embodiment, the material of the dummy gate layer is polysilicon; in other embodiments, amorphous silicon may also be used as the material of the dummy gate layer.

In this embodiment, the material of the sidewall 210 is silicon nitride.

Referring to fig. 7 to 8, fig. 8 is a schematic cross-sectional view taken along line A-A in fig. 7, and a sidewall material layer (not shown) is formed on the sidewalls and top surface of the dummy gate structure 209; forming a first patterned layer (not shown) on the substrate 200, the first patterned layer exposing the sidewall material layer on the second region II; etching the side wall material layer by taking the first patterned layer as a mask until the top surface of the dummy gate structure 209 is exposed, and forming a side wall 210 on the side wall of the dummy gate structure 209 in the second region II; and etching the second initial fin structure by taking the first patterned layer, the dummy gate structure 209 and the side wall 210 on the second region II as masks, and forming a second source drain opening 212 in the second initial fin structure.

In this embodiment, the second source-drain opening 212 provides a space for a second source-drain doped layer to be formed later.

Referring to fig. 9, the directions of the views in fig. 9 and fig. 8 are identical, and a portion of the first channel layer 205 exposed by the second source-drain opening 212 is etched to form a second groove 214.

In this embodiment, the second recess 214 is used to provide space for a second barrier layer to be formed later.

Referring to fig. 10, a second barrier layer 216 is formed in the second recess 214.

In this embodiment, the method for forming the second barrier layer 216 includes: removing the first patterning layer; depositing a second barrier film (not shown) on the first region I and the second region II after removing the first patterned layer; forming a second patterned layer (not shown) on the substrate 200, the second patterned layer exposing the second barrier film on the second region II; and etching the second barrier layer film by taking the second patterned layer as a mask to form the second barrier layer 216.

The process of forming the second barrier layer film includes a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. In this embodiment, the process of forming the second barrier layer film uses an atomic layer deposition process.

In this embodiment, the material of the second blocking layer 216 is silicon nitride.

Referring to fig. 11, after forming the second barrier layer 216, the second patterned layer is removed; after the second patterned layer is removed, a second source-drain doped layer 218 is formed within the second source-drain opening 212, the second source-drain doped layer 218 having second source-drain ions therein.

In this embodiment, the second source-drain ions are P-type ions.

Referring to fig. 12 to 13, fig. 13 is a schematic cross-sectional view taken along line B-B in fig. 12, after the second source-drain doped layer 218 is formed, a third patterned layer (not shown) is formed on the substrate 200, and the third patterned layer exposes the sidewall material layer and the second barrier film on the first region I; etching the side wall material layer and the second barrier layer film by taking the third patterned layer as a mask until the top surface of the dummy gate structure 209 is exposed, and forming a side wall 210 on the side wall of the dummy gate structure 209 in the first region I; and etching the first initial fin structure by taking the third patterned layer, the dummy gate structure 209 positioned on the first region I and the side wall as masks, and forming a first source drain opening 211 in the first initial fin structure.

In this embodiment, the first source-drain opening 211 provides a space for a first source-drain doped layer to be formed later.

Referring to fig. 14, the view directions of fig. 14 and fig. 13 are identical, and a portion of the isolation channel layer 204 and a portion of the second channel layer 206 exposed by the first source-drain opening 211 are etched to form a first groove 213.

In this embodiment, the first recess 213 is used to provide a space for a first barrier layer to be formed later.

Referring to fig. 15, a first barrier layer 215 is formed in the first recess 213.

In this embodiment, the method for forming the first barrier layer 215 includes: removing the third patterned layer; depositing a first barrier film (not shown) on the first region I and the second region II after removing the third patterned layer; forming a fourth patterned layer (not shown) on the substrate 200, the fourth patterned layer exposing the first barrier film on the first region I; and etching the first barrier layer film by taking the fourth patterned layer as a mask to form the first barrier layer 215.

The process of forming the first barrier layer film includes a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. In this embodiment, the process of forming the first barrier layer film uses an atomic layer deposition process.

In this embodiment, the material of the first blocking layer 215 is silicon nitride.

Referring to fig. 16, after forming the first barrier layer 21, the fourth patterned layer is removed; after the fourth patterned layer is removed, a first source-drain doped layer 217 is formed in the first source-drain opening 211, wherein first source-drain ions are contained in the first source-drain doped layer 217, and the electrical types of the first source-drain ions and the second source-drain ions are different.

In this embodiment, the first source-drain ions are N-type ions.

In this embodiment, a CMOS transistor is constituted by the formed PMOS transistor and NMOS transistor.

Referring to fig. 17 and 18, fig. 18 is a schematic cross-sectional view taken along line C-C in fig. 17, wherein the first barrier film on the second source-drain doped layer 218 is removed by cleaning; a dielectric layer 219 is formed on the substrate 200, the dielectric layer 219 covers the dummy gate structure 209, the sidewall 210, the first source-drain doped layer 217 and the second source-drain doped layer 218, and the dielectric layer 219 exposes the top surfaces of the dummy gate structure 209 and the sidewall 210.

In this embodiment, the material of the dielectric layer 219 is silicon oxide.

Referring to fig. 19, the view directions of fig. 19 and fig. 18 are identical, and after the dielectric layer 219 is formed, the first fin structure and the second fin structure are formed.

In this embodiment, the forming method of the first fin structure and the second fin structure includes: forming a fifth patterned layer (not shown) on the dielectric layer 219, the fifth patterned layer exposing a top surface of the dummy gate structure 209 located on the second region II; removing the dummy gate structure 209 on the second region II with the fifth patterned layer as a mask to form a second gate opening (not labeled); after forming the second gate opening, removing the first channel layer 205 exposed by the second gate opening, and forming a second gate recess (not labeled) and the second fin structure; after forming the second fin structure, removing the fifth patterned layer and forming a sixth patterned layer (not shown) on the dielectric layer 219, the sixth patterned layer exposing a top surface of the dummy gate structure 209 located on the first region I; removing the dummy gate structure 209 on the first region I with the sixth patterned layer as a mask to form a first gate opening (not shown); after forming the first gate opening, removing the blocking channel layer 204 and the second channel layer 206 exposed by the first gate opening, forming a first gate recess (not shown) and the first fin structure; and removing the sixth patterning layer after the second fin structure is formed.

In this embodiment, the blocking channel layer and the ions doped in the first channel layer are of the same electrical type, but are different ions of the same electrical type, so that the blocking channel layer is retained when the first channel layer is removed, because the blocking channel layer and the ions doped in the first channel layer have different selection ratios to the removal reagent.

With continued reference to fig. 19, after forming the first fin portion and the second fin portion, the method further includes: forming a gate oxide layer (not shown) within the first gate opening, the first gate recess, the second gate opening, and the second gate recess, the gate oxide layer surrounding the first channel layer 205, the blocking channel layer 204, and the second channel layer 206; forming a second gate work function layer (not labeled) on the surface of the gate oxide layer; forming a seventh patterned layer (not shown) on the substrate 200, the seventh patterned layer exposing the second gate work function layer on the first region I; removing the second grid work function layer on the first region I by taking the seventh patterned layer as a mask; removing the seventh patterned layer; forming a first gate work function layer (not labeled) on the surface of the gate oxide layer of the first region I and the surface of the second gate work function layer of the second region II; forming a gate material layer (not shown) on the first gate work function layer and on the dielectric layer; the gate material layer is planarized until the surface of the dielectric layer 219 is exposed, a gate layer is formed, a first gate structure 220 is formed by the gate oxide layer, the first gate work function layer, and the gate layer in the first region II, and a second gate structure 221 is formed by the gate oxide layer, the first gate work function layer, the second gate work function layer, and the gate layer in the second region II.

In this embodiment, the first gate work function layer is used to adjust the threshold voltage of the NMOS transistor, and the second gate work function layer is used to adjust the threshold voltage of the PMOS transistor.

In this embodiment, the second channel layer 206 of the silicon germanium material with the second doped ions is used as the channel region of the PMOS transistor, so as to meet the requirement of the PMOS transistor on the mobility of the hole, thereby effectively improving the performance of the finally formed semiconductor structure. By adding the isolation channel layer 204, the isolation channel layer 204 is made of silicon doped with a third doping ion, and the third doping ion is opposite to the second doping ion in the second channel layer 206 in electrical type, so that a parasitic transistor formed at the bottom of the PMOS transistor is opposite to the PMOS transistor in type, and the problem of leakage at the bottom of the PMOS transistor is effectively reduced.

Since the isolation channel layer 204 is located below the second channel layer 206, when the second gate work function layer located on the first region I is etched, only the second gate work function layer covering the isolation channel layer 204 is damaged, and the second gate work function layer covering the second channel layer 206 is not damaged, so that the influence on the threshold voltage of the PMOS transistor is reduced, and the performance of the finally formed semiconductor structure is improved.

Accordingly, in an embodiment of the present invention, there is further provided a semiconductor structure, please continue to refer to fig. 19, including: a substrate 200, said substrate 200 comprising a first region I and a second region II; the first fin structure is located on the first region I, and includes a plurality of layers of first channel layers 205 arranged in an overlapping manner along a surface normal direction of the substrate 200, where a material of the first channel layers 205 is silicon doped with a first doping ion or undoped silicon; the second fin structure located on the second region II includes a blocking channel layer 204, and a plurality of second channel layers 206 located on the blocking channel layer 204, where the blocking channel layer 204 and the plurality of second channel layers 206 are arranged in an overlapping manner along a surface normal direction of the substrate 200, silicon germanium doped with second doping ions is adopted as a material in the second channel layer 206, silicon doped with third doping ions is adopted as a material in the blocking channel layer 204, the second doping ions are respectively different from the third doping ions and the first doping ions in electrical type, the third doping ions are the same as the first doping ions in electrical type, the first doping ions and the third doping ions are different ions in electrical type, and a doping concentration of the third doping ions in the blocking channel layer 204 makes the blocking channel layer 204 unable to be turned on when the transistor works.

In this embodiment, the second channel layer 206 of the silicon germanium material with the second doped ions is used as the channel region of the PMOS transistor, so as to meet the requirement of the PMOS transistor on the mobility of the hole, thereby effectively improving the performance of the finally formed semiconductor structure. By adding the isolation channel layer 204, the isolation channel layer 204 is made of silicon doped with a third doping ion, and the third doping ion is opposite to the second doping ion in the second channel layer 206 in electrical type, so that a parasitic transistor formed at the bottom of the PMOS transistor is opposite to the PMOS transistor in type, and the problem of leakage at the bottom of the PMOS transistor is effectively reduced. And the isolation channel layer 204 is located below the second channel layer 206, so that when the first gate structure 220 is formed later, only the second gate structure 221 located on the isolation channel layer 204 is damaged, and the second gate structure 221 coated on the second channel layer 206 is not damaged, thereby reducing the influence on the threshold voltage of the PMOS transistor and improving the performance of the finally formed semiconductor structure.

In this embodiment, further comprising: the first doping ions are N-type ions; the second doping ions are P-type ions; the third doping ion is an N-type ion, and the first doping ion and the third doping ion are different N-type ions.

In this embodiment, further comprising: a first gate structure 220 located on the substrate 200 across the first fin structure, the first gate structure 220 surrounding the first channel layer 205; a second gate structure 221 located on the substrate 200 across the second fin structure, the second gate structure 221 surrounding the blocking channel layer 204 and the second channel layer 206.

In this embodiment, further comprising: an isolation trench 207 located within the substrate 200; an isolation layer 208 located in the isolation trench 207, a top surface of the isolation layer 208 being flush with a bottom surface of the isolation channel layer 204.

In this embodiment, further comprising: the first source-drain doped layer 211 is located in the first fin structure, and first source-drain ions are located in the first source-drain doped layer 211; and the second source-drain doping layer 212 is positioned in the second fin structure, second source-drain ions are arranged in the second source-drain doping layer 212, and the electrical types of the first source-drain ions and the second source-drain ions are different.

In this embodiment, the first source-drain ions are N-type ions; and the second source-drain ions are P-type ions.

In this embodiment, further comprising: side walls 210 located on sidewalls of the first gate structure 220 and the second gate structure 221; a first barrier layer 215 between the first channel layer 205 and the substrate 200, and between adjacent first channel layers 205; a second barrier layer 216 located between adjacent ones of the blocking channel layer 204 and the second channel layer 206, and adjacent ones of the second channel layer 206.

In this embodiment, further comprising: the dielectric layer 219 is located on the substrate 200, the dielectric layer 219 covers the first gate structure 220, the second gate structure 221 and the sidewall 210, and the dielectric layer 219 exposes the top surfaces of the first gate structure 220, the second gate structure 221 and the sidewall 210.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A semiconductor structure, comprising:

A substrate comprising a first region and a second region;

the first fin structure is positioned on the first region and comprises a plurality of layers of first channel layers which are overlapped and arranged along the normal direction of the surface of the substrate, and the first channel layers are made of silicon doped with first doping ions or undoped silicon;

the second fin structure is located on the second region and comprises a separation channel layer and a plurality of second channel layers located on the separation channel layer, the separation channel layer and the second channel layers are overlapped and distributed along the normal direction of the surface of the substrate, silicon germanium doped with second doping ions is adopted as materials in the second channel layer, silicon doped with third doping ions is adopted as materials in the separation channel layer, the second doping ions are respectively different from the third doping ions and the first doping ions in electrical type, the third doping ions are the same as the first doping ions in electrical type, the first doping ions and the third doping ions are different ions in electrical type, and the doping concentration of the third doping ions in the separation channel layer enables the separation channel layer not to be conducted when the transistor works.

2. The semiconductor structure of claim 1, wherein the first dopant ions are N-type ions; the second doping ions are P-type ions; the third doped ion is an N-type ion.

3. The semiconductor structure of claim 1, further comprising: a first gate structure located on the substrate across the first fin structure, the first gate structure surrounding the first channel layer; and a second gate structure on the substrate and crossing the second fin structure, wherein the second gate structure surrounds the isolation channel layer and the second channel layer.

4. The semiconductor structure of claim 1, further comprising: an isolation trench located within the substrate; and the top surface of the isolation layer is flush with the bottom surface of the isolation channel layer.

5. The semiconductor structure of claim 1, further comprising: the first source-drain doping layer is positioned in the first fin structure, and first source-drain ions are arranged in the first source-drain doping layer; and the second source-drain doping layer is positioned in the second fin structure, second source-drain ions are arranged in the second source-drain doping layer, and the electrical types of the first source-drain ions and the second source-drain ions are different.

6. The semiconductor structure of claim 5, wherein the first source drain ions are N-type ions; and the second source-drain ions are P-type ions.

7. The semiconductor structure of claim 3, further comprising: the side walls are positioned on the side walls of the first grid electrode structure and the second grid electrode structure; a first barrier layer between the first channel layer and the substrate, and between adjacent first channel layers; and a second barrier layer positioned between adjacent ones of the blocking channel layer and the second channel layer, and adjacent ones of the second channel layer.

8. The semiconductor structure of claim 7, further comprising: and the dielectric layer is positioned on the substrate and covers the first grid electrode structure, the second grid electrode structure and the side wall, and the dielectric layer exposes the top surfaces of the first grid electrode structure, the second grid electrode structure and the side wall.

9. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a first region and a second region;

forming a first fin structure on the first region, wherein the first fin structure comprises a plurality of layers of first channel layers which are overlapped and arranged along the normal direction of the surface of the substrate, and the first channel layers are made of silicon doped with first doping ions or undoped silicon;

And forming a second fin structure on the second region, wherein the second fin structure comprises a partition channel layer and a plurality of second channel layers positioned on the partition channel layer, the partition channel layer and the plurality of second channel layers are overlapped and distributed along the normal direction of the surface of the substrate, the material of the second channel layer adopts silicon germanium doped with second doping ions, the material of the partition channel layer adopts silicon doped with third doping ions, the second doping ions are respectively different from the third doping ions and the first doping ions in electrical type, the third doping ions are the same as the first doping ions in electrical type, the first doping ions and the third doping ions are different ions in electrical type, and the doping concentration of the third doping ions in the partition channel layer enables the partition channel layer not to be conducted when the transistor works.

10. The method of forming a semiconductor structure of claim 9, wherein the first dopant ions are N-type ions; the second doping ions are P-type ions; the third doped ion is an N-type ion.

11. The method of forming a semiconductor structure of claim 9, further comprising, after forming the first fin structure and the second fin structure: forming a first gate structure on the substrate across the first fin structure, the first gate structure surrounding the first channel layer; a second gate structure is formed on the substrate across the second fin structure, the second gate structure surrounding the blocking channel layer and the second channel layer.

12. The method of forming a semiconductor structure of claim 11, further comprising, prior to forming the first fin structure and the second fin structure: and forming a partition channel material layer, a plurality of first channel material layers and a plurality of second channel material layers on the substrate, wherein the first channel material layers are positioned between adjacent partition channel material layers and the second channel material layers or between adjacent second channel material layers.

13. The method of forming a semiconductor structure of claim 12, further comprising, after forming the isolating channel material layer, the first channel material layer, and the second channel material layer: and carrying out graphical processing on the isolating channel material layer, the first channel material layers and the second channel material layers to form a first initial fin structure and a second initial fin structure, wherein the first initial fin structure comprises the isolating channel layer, the first channel layers and the second channel layers, the first channel layers are adjacent to each other, the isolating channel layers and the second channel layers are adjacent to each other, or the second channel layers are adjacent to each other, the second initial fin structure comprises the isolating channel layers, the first channel layers and the second channel layers, and the first channel layers are adjacent to each other, or the second channel layers are adjacent to each other.

14. The method of forming a semiconductor structure of claim 13, further comprising, during the patterning process: etching the substrate to form an isolation trench in the substrate; after the patterning process, further comprising: an isolation layer is formed within the isolation trench, a top surface of the isolation layer being flush with a bottom surface of the isolation channel layer.

15. The method of forming a semiconductor structure of claim 13, further comprising, after forming the first initial fin structure and the second initial fin structure: forming a dummy gate structure on the substrate, wherein the dummy gate structure spans the first initial fin structure and the second initial fin structure; forming a side wall material layer on the side wall and the top surface of the pseudo gate structure; forming a first patterned layer on the substrate, wherein the first patterned layer exposes the side wall material layer on the second region; etching the side wall material layer by taking the first patterned layer as a mask until the top surface of the pseudo gate structure is exposed, and forming a side wall on the side wall of the pseudo gate structure in the second region; etching the second initial fin structure by taking the first patterning layer, the pseudo gate structure and the side wall which are positioned on the second region as masks, and forming a second source drain opening in the second initial fin structure; etching part of the first channel layer exposed by the second source drain opening to form a second groove; removing the first patterning layer; depositing a second barrier film over the first region and the second region after removing the first patterned layer; forming a second patterned layer on the substrate, the second patterned layer exposing the second barrier film on the second region; etching the second barrier layer film by taking the second patterned layer as a mask, and forming a second barrier layer in the second groove; removing the second patterned layer after forming the second barrier layer; forming a second source-drain doping layer in the second source-drain opening after removing the second patterning layer, wherein second source-drain ions are arranged in the second source-drain doping layer; forming a third patterned layer on the substrate after forming the second source-drain doped layer, wherein the third patterned layer exposes the side wall material layer and the second barrier layer film on the first region; etching the side wall material layer and the second barrier layer film by taking the third patterned layer as a mask until the top surface of the pseudo gate structure is exposed, and forming a side wall on the side wall of the pseudo gate structure in the first region; etching the first initial fin structure by taking the third graphical layer, the pseudo gate structure and the side wall which are positioned on the first region as masks, and forming a first source drain opening in the first initial fin structure; etching part of the isolation channel layer and part of the second channel layer exposed by the first source drain opening to form a first groove; removing the third patterned layer; depositing a first barrier film over the first region and the second region after removing the third patterned layer; forming a fourth patterned layer on the substrate, the fourth patterned layer exposing the first barrier film on the first region; etching the first barrier layer film by taking the fourth patterned layer as a mask, and forming a first barrier layer in the first groove; removing the fourth patterned layer after forming the first barrier layer; forming a first source-drain doping layer in the first source-drain opening after removing the fourth patterning layer, wherein first source-drain ions are arranged in the first source-drain doping layer, and the electrical types of the first source-drain ions and the second source-drain ions are different; cleaning and removing the first barrier layer film on the second source-drain doping layer; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the pseudo gate structure, the side wall, the first source drain doping layer and the second source drain doping layer, and the dielectric layer exposes the top surfaces of the pseudo gate structure and the side wall.

16. The method of claim 15, wherein the first source drain ions are N-type ions; and the second source-drain ions are P-type ions.

17. The method of forming a semiconductor structure of claim 15, wherein the method of forming the first fin structure and the second fin structure comprises: forming a fifth patterned layer on the dielectric layer, wherein the fifth patterned layer exposes the top surface of the pseudo gate structure on the second region; removing the pseudo gate structure on the second region by taking the fifth patterned layer as a mask to form a second gate opening; removing the first channel layer exposed by the second gate opening after the second gate opening is formed, and forming a second gate groove and the second fin structure; removing the fifth patterned layer after the second fin structure is formed, and forming a sixth patterned layer on the dielectric layer, wherein the sixth patterned layer exposes the top surface of the pseudo gate structure on the first region; removing the pseudo gate structure on the first region by taking the sixth patterned layer as a mask to form a first gate opening; removing the isolation channel layer and the second channel layer exposed by the first gate opening after the first gate opening is formed, and forming a first gate groove and the first fin structure; and removing the sixth patterning layer after the second fin structure is formed.

18. The method of forming a semiconductor structure of claim 17, wherein the method of forming the first gate structure and the second gate structure comprises: forming a gate oxide layer in the first gate opening, the first gate groove, the second gate opening and the second gate groove, wherein the gate oxide layer surrounds the first channel layer, the isolation channel layer and the second channel layer; forming a second grid work function layer on the surface of the grid oxide layer; forming a seventh patterned layer on the substrate, the seventh patterned layer exposing the second gate work function layer located on the first region; removing the second grid work function layer on the first region by taking the seventh patterned layer as a mask; removing the seventh patterned layer; forming a first gate work function layer on the surface of the gate oxide layer of the first region and the surface of the second gate work function layer of the second region; forming a gate material layer on the first gate work function layer and the dielectric layer; and flattening the gate material layer until the surface of the dielectric layer is exposed, forming a gate layer, forming a first gate structure by the gate oxide layer, the first gate work function layer and the gate layer which are positioned in the first region, and forming a second gate structure by the gate oxide layer, the first gate work function layer, the second gate work function layer and the gate layer which are positioned in the second region.