CN117199127A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and method of forming the same, wherein the structure comprises: the semiconductor device comprises a substrate, wherein the substrate is provided with a fin structure, and the fin structure comprises a plurality of channel layers; a gate structure on the substrate, sidewalls of the gate structure between adjacent channel layers being recessed relative to sidewalls of the channel layers; source-drain doped layers in fin structures at two sides of the gate structure; the barrier layer is positioned between the source-drain doping layer and the grid structure; and a protective layer between the barrier layer and the gate structure. In the process of forming the protective layer by adopting the first epitaxial growth process, the sacrificial layer is also continuously consumed, so that the depth of the groove is deepened, and the interval between the gate structure and the source-drain doped layer is further increased. In addition, the material of the protective layer formed on the surface of the groove is different from that of the sacrificial layer, and in the subsequent process of removing the sacrificial layer, the damage of etching to the source-drain doped layer can be effectively avoided through the protective layer, so that the performance of the finally formed semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

Metal-oxide-semiconductor field effect transistors (MOSFETs) are one of the most important elements in modern integrated circuits, the basic structure of a MOSFET comprising: a semiconductor substrate; a gate structure on a surface of a semiconductor substrate, the gate structure comprising: the gate electrode layer is positioned on the surface of the gate dielectric layer; source and drain doped regions in the semiconductor substrate on both sides of the gate structure.

With the development of semiconductor technology, the control capability of a conventional planar MOSFET on channel current becomes weak, resulting in serious leakage current. Fin field effect transistors (Fin FETs) are an emerging type of multi-gate device that generally include a Fin protruding from a semiconductor substrate surface, a gate structure covering a portion of the top surface and sidewalls of the Fin, and source-drain doped regions in the Fin on either side of the gate structure. Compared with a planar MOSFET, the fin field effect transistor has stronger short channel inhibition capability and stronger working current.

With further development of semiconductor technology, conventional finfet has a limitation in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a MOSFET of a Gate All Around (GAA) structure is proposed, so that the volume for serving as a channel region is increased, further increasing the operating current of the GAA structure MOSFET.

However, there are still a number of problems in the device structure of GAA in the prior art.

Disclosure of Invention

The invention solves the technical problem of providing a semiconductor structure and a forming method thereof so as to improve the performance of the finally formed semiconductor structure.

In order to solve the above problems, the present invention provides a semiconductor structure, comprising: the semiconductor device comprises a substrate, wherein the substrate is provided with a fin structure, and the fin structure comprises a plurality of channel layers which are overlapped and arranged along the normal direction of the surface of the substrate; the grid structure is positioned on the substrate, spans across the fin part structure, is positioned between adjacent channel layers and coats a plurality of layers of the channel layers, and the side wall of the grid structure positioned between the adjacent channel layers is sunken relative to the side wall of the channel layer; source-drain doped layers in the fin structures at both sides of the gate structure; the barrier layer is positioned between the source-drain doped layer and the gate structure and is positioned on the side wall of the gate structure between the adjacent channel layers; and a protective layer between the barrier layer and the gate structure.

Optionally, the protective layer is further located between the source-drain doped layer and the channel layer.

Optionally, the material of the protective layer is the same as the material of the channel layer.

Optionally, the thickness of the protective layer is 2 nm-5 nm.

Optionally, the material of the channel layer includes: silicon or silicon germanium.

Optionally, the method further comprises: and the dielectric layer is positioned on the substrate and covers the side wall of the grid structure.

Optionally, the material of the barrier layer includes: silicon nitride.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a fin structure, the fin structure comprises a plurality of channel layers and a plurality of sacrificial layers which are overlapped and arranged along the normal direction of the surface of the substrate, and the channel layers and the sacrificial layers are made of different materials; forming a dummy gate structure on the substrate, the dummy gate structure crossing the fin structure; etching the fin portion structure by taking the pseudo gate structure as a mask, and forming source and drain openings in the fin portion structure; etching part of the sacrificial layer exposed by the source drain opening to form a groove; and forming a protective layer on the surface of the groove by adopting a first epitaxial growth process, wherein the material of the protective layer is different from that of the sacrificial layer.

Optionally, in the process of forming the protective layer on the surface of the groove, the method further includes: and forming the protective layer on the side wall of the channel layer exposed by the source drain opening.

Optionally, the material of the protective layer is the same as the material of the channel layer.

Optionally, the thickness of the protective layer is 2 nm-5 nm.

Optionally, the material of the channel layer includes: silicon or silicon germanium; the material of the sacrificial layer comprises germanium silicon or silicon.

Optionally, the sacrificial layer is located between adjacent channel layers and the substrate, or between adjacent channel layers.

Optionally, the sacrificial layer includes a bottom region, a middle region located on the bottom region, and a top region located on the middle region, and the germanium atom content in the middle region is higher than the germanium atom content in the bottom region and the top region.

Optionally, after forming the protective layer, the method further includes: forming a barrier layer in the groove; forming a source-drain doping layer in the source-drain opening; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall of the pseudo gate structure.

Optionally, the method for forming the barrier layer includes: forming a first initial barrier layer in the groove, on the side wall and the bottom surface of the source drain opening, and on the side wall and the top surface of the pseudo gate structure; etching back the first initial barrier layer until the bottom surfaces of the source and drain openings and the top surfaces of the pseudo gate structures are exposed, and forming a second initial barrier layer; and etching back the second initial barrier layer until the side wall of the channel layer is exposed, so as to form the barrier layer.

Optionally, the material of the barrier layer includes: silicon nitride.

Optionally, after forming the dielectric layer, the method further includes: removing the pseudo gate structure and forming a gate opening in the dielectric layer; removing the sacrificial layers after the gate openings are formed, and forming gate grooves between adjacent channel layers and between the adjacent channel layers and the substrate; and forming a gate structure in the gate opening and the gate groove, wherein the gate structure wraps a plurality of layers of channel layers.

Compared with the prior art, the technical scheme of the invention has the following advantages:

in the structure of the technical scheme of the invention, because the protective layer is formed by adopting the first epitaxial growth process, the sacrificial layer is also continuously consumed in the process of forming the protective layer by adopting the first epitaxial growth process, so that the depth of the groove is deepened, the depth direction is the direction vertical to the side wall of the grid structure, and the interval between the grid structure and the source-drain doped layer is further increased. In addition, the protection layer is located between the barrier layer and the gate structure, and the material of the protection layer is different from that of the sacrificial layer, so that damage of etching to the source-drain doped layer can be effectively avoided through the protection layer in the subsequent removal process of the sacrificial layer, and the performance of the finally formed semiconductor structure is improved.

Furthermore, the protective layer is also positioned between the source-drain doped layer and the channel layer, so that the distance between the gate structure and the source-drain doped layer can be continuously increased, and short circuit between the gate structure and the source-drain doped layer is avoided.

Further, the material of the protective layer is the same as that of the channel layer, so that electrical connection between the channel layer and the source-drain doped layer can be ensured.

Further, the thickness of the protective layer is 2 nm-5 nm. When the thickness of the protective layer is larger than 5nm, the material of the ring gate sacrificial layer is excessively consumed, so that the filling width of the ring gate metal material is smaller, and the control capability of the ring gate on a channel is reduced; when the thickness of the protective layer is smaller than 2nm, the effect of improving the trailing of the etching profile of the side wall gap of the sacrificial layer cannot be achieved, and the side wall forming defect is caused.

In the forming method of the technical scheme of the invention, the sacrificial layer is consumed continuously in the process of forming the protective layer by adopting the first epitaxial growth process, so that the depth of the groove is deepened, the depth direction is perpendicular to the side wall of the pseudo gate structure, and the interval between the gate structure formed subsequently and the source-drain doped layer is further increased. In addition, the protective layer is formed on the surface of the groove, and the material of the protective layer is different from that of the sacrificial layer, so that the damage of etching to the source-drain doped layer can be effectively avoided through the protective layer in the subsequent removal process of the sacrificial layer, and the performance of the finally formed semiconductor structure is improved.

Further, in the process of forming the protective layer on the surface of the groove, the method further comprises: and forming the protective layer on the side wall of the channel layer exposed by the source-drain opening, so that the distance between the gate structure and the source-drain doped layer can be continuously increased, and short circuit between the gate structure and the source-drain doped layer is avoided.

Further, the material of the protective layer is the same as that of the channel layer, so that electrical connection between the channel layer and the source-drain doped layer can be ensured.

Further, the thickness of the protective layer is 2-5 nm. When the thickness of the protective layer is larger than 5nm, the material of the ring gate sacrificial layer is excessively consumed, so that the filling width of the ring gate metal material is smaller, and the control capability of the ring gate on a channel is reduced; when the thickness of the protective layer is smaller than 2nm, the effect of improving the trailing of the etching profile of the side wall gap of the sacrificial layer cannot be achieved, and the side wall forming defect is caused.

Drawings

FIGS. 1-3 are schematic views of steps of a method for forming a semiconductor structure;

fig. 4 to 13 are schematic structural views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As described in the background, there are still many problems in the device structure of GAA in the prior art. The following will make a detailed description with reference to the accompanying drawings.

Fig. 1 to 3 are schematic structural views illustrating steps of a method for forming a semiconductor structure.

Referring to fig. 1 and 2, fig. 2 is an enlarged schematic view of a portion a in fig. 1, providing a substrate 100, wherein the substrate 100 has a fin structure thereon, the fin structure includes a plurality of channel layers 101 and a plurality of sacrificial layers 102 that are arranged in an overlapping manner along a surface normal direction of the substrate 100, and the sacrificial layers 102 are located between adjacent channel layers 101 and the substrate 100 or between adjacent channel layers 101; forming a dummy gate structure 103 on the substrate 100, the dummy gate structure 103 crossing the fin structure; etching the fin portion structure by taking the dummy gate structure 103 as a mask, and forming a source drain opening 104 in the fin portion structure; portions of the sacrificial layer 102 exposed by the source-drain openings 104 are etched to form grooves 105.

Referring to fig. 3, the view directions of fig. 3 and fig. 1 are consistent; forming a barrier layer 106 within the recess 105; forming a source-drain doped layer 107 in the source-drain opening 104; forming a dielectric layer 108 on the substrate 100, wherein the dielectric layer 108 covers the side wall of the dummy gate structure 103; removing the dummy gate structure 103, and forming a gate opening (not labeled) in the dielectric layer 108; removing the sacrificial layer 102 exposed by the gate opening to form a gate groove; a gate structure 109 is formed within the gate opening and the gate recess.

In this embodiment, the material of the channel layer 101 is silicon, and the material of the sacrificial layer 102 is silicon germanium. The sacrificial layer 102 includes a bottom region I, a middle region II located on the bottom region I, and a top region III located on the middle region II. Since the sacrificial layer 102 is formed by an epitaxial growth process, the epitaxial growth process results in a lower germanium atom content in the bottom region I and the top region III, and a higher germanium atom content in the middle region II.

In the process of etching and removing part of the sacrificial layer 102 to form the groove 105, the etching rate of the middle region II with higher content of germanium atoms is faster, and the etching rates of the bottom region I and the top region III with lower content of germanium atoms are slower, so that the formed groove 105 is in an arc shape.

Since the bottom region I and the top region III are removed by a smaller amount, the thickness of the barrier layer 106 formed in the bottom region I and the top region III is also smaller. In the process of removing the sacrificial layer 102, the barrier layer 106 located in the bottom region I and the top region III is easily completely consumed, and thus, etching damage (as shown in part B in fig. 3) is also caused to the source-drain doped layer 107, and meanwhile, a short circuit occurs between the formed gate structure 109 and the source-drain doped layer 107.

On the basis, the invention provides a semiconductor structure and a forming method thereof, and because the sacrificial layer is continuously consumed in the process of forming the protective layer by adopting the first epitaxial growth process, the depth of the groove is deepened, the depth direction is perpendicular to the side wall of the pseudo gate structure, and the interval between the gate structure formed subsequently and the source-drain doped layer is further increased. Meanwhile, a protective layer is formed on the side wall of the channel layer exposed by the source-drain opening, so that the distance between the grid structure and the source-drain doped layer can be increased. In addition, the protective layer is formed on the surface of the groove, and the material of the protective layer is different from that of the sacrificial layer, so that the damage of etching to the source-drain doped layer can be effectively avoided through the protective layer in the subsequent removal process of the sacrificial layer, and the performance of the finally formed semiconductor structure is improved.

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 4 to 13 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 4 and 5, fig. 5 is an enlarged schematic view of the sacrificial layer in fig. 4, a substrate 200 is provided, and the substrate 200 has a fin structure thereon, wherein the fin structure includes a plurality of channel layers 201 and a plurality of sacrificial layers 202 that are arranged in an overlapping manner along a normal direction of a surface of the substrate 200, and materials of the channel layers 201 and the sacrificial layers 202 are different.

The material of the substrate 200 may be silicon or silicon germanium; in this embodiment, the substrate 200 is made of silicon.

In this embodiment, the method for forming the fin structure includes: forming a plurality of channel material layers (not shown) and a plurality of sacrificial material layers (not shown) which are overlapped and arranged along the normal direction of the surface of the substrate 200 on the substrate 200, wherein the channel material layers and the sacrificial material layers are made of different materials; and carrying out a patterning process on the channel materials and the sacrificial material layers to form the fin structure.

In this embodiment, the sacrificial material layer is located between the adjacent channel material layer and the substrate, or between the adjacent channel material layers, and thus the sacrificial layer 202 is also formed between the adjacent channel layer 201 and the substrate 200, or between the adjacent channel layers 201.

In this embodiment, the material of the channel material layer is silicon, the material of the sacrificial material layer is germanium-silicon, so that the material of the channel layer 201 is also silicon, and the material of the sacrificial layer 202 is germanium-silicon.

In other embodiments, the material of the channel material layer may be silicon germanium, the material of the sacrificial material layer may be silicon, the material of the channel layer correspondingly formed may be silicon germanium, and the material of the sacrificial layer may be silicon.

In this embodiment, since the sacrificial material layer is formed by an epitaxial growth process, the epitaxial growth process may cause the germanium atom content of the sacrificial material layer to increase from bottom to top and then decrease. The sacrificial layer 202 correspondingly formed thus comprises a bottom region I, a middle region II located on the bottom region I, and a top region III located on the middle region II, and the germanium atom content in the middle region II is higher than the germanium atom content in the bottom region I and the top region III.

With continued reference to fig. 4, in this embodiment, during the patterning process of the channel material layers and the sacrificial material layers, a portion of the substrate 200 is removed, and an isolation trench (not labeled) is formed in the substrate 200; after forming the isolation trench, an isolation layer 203 is formed within the isolation trench, a top surface of the isolation layer 203 being lower than a top surface of the substrate 200.

In this embodiment, the method for forming the isolation layer 203 includes: forming an isolation material layer (not shown) within the isolation trench and on the substrate 200, the isolation material layer covering the fin structure; flattening the isolation material layer until the top surface of the fin structure is exposed, and forming an initial isolation layer (not shown); the initial isolation layer is etched back to form the isolation layer 203.

In this embodiment, the material of the isolation layer 203 is silicon oxide.

Referring to fig. 6, after forming the isolation layer 203, a dummy gate structure 204 is formed on the substrate 200, and the dummy gate structure 204 spans the fin structure.

In this embodiment, the dummy gate structure 204 includes: the semiconductor device comprises a dummy gate dielectric layer and a dummy gate layer (not labeled) positioned on the dummy gate dielectric layer.

In this embodiment, the material of the dummy gate dielectric layer is silicon oxide.

In this embodiment, the material of the dummy gate layer is polysilicon; in other embodiments, amorphous silicon may also be used as the material of the dummy gate layer.

With continued reference to fig. 6, after the dummy gate structure is formed, a sidewall 205 is formed on the sidewall of the dummy gate structure 204.

In this embodiment, the material of the side wall 205 is silicon nitride.

Referring to fig. 7, the fin structure is etched using the dummy gate structure 204 as a mask, and source and drain openings 206 are formed in the fin structure.

It should be noted that when etching the fin structure, the method further includes: the sidewall 205 is used as a mask.

In this embodiment, the source-drain openings 206 provide space for a source-drain doped layer to be formed later.

Referring to fig. 8, a recess 207 is formed by etching a portion of the sacrificial layer 202 exposed by the source-drain opening 206.

In this embodiment, the recess 207 serves to provide space for a barrier layer to be formed later. The barrier layer can ensure the electrical isolation between the gate structure formed later and the source-drain doped layer.

In this embodiment, during the process of etching and removing part of the sacrificial layer 202 to form the groove 207, the etching rate of the middle region II with higher content of germanium atoms is faster, and the etching rates of the bottom region I and the top region III with lower content of germanium atoms are slower, so that the groove 207 is formed in a circular arc shape.

Referring to fig. 9, a first epitaxial growth process is used to form a protection layer 208 on the surface of the recess 207, where the material of the protection layer 208 is different from the material of the sacrificial layer 202.

In this embodiment, the sacrificial layer 202 is consumed continuously during the process of forming the protective layer 208 by the first epitaxial growth process, so that the depth of the groove 207 is deepened, and the depth direction is perpendicular to the sidewall of the dummy gate structure 204, so that the interval between the subsequently formed gate structure and the source-drain doped layer is increased. At the same time, the sidewall of the channel layer 201 exposed by the source-drain opening 206 forms a protection layer 208, which also increases the space between the gate structure and the source-drain doped layer. In addition, the protection layer 208 formed on the surface of the groove 207, where the material of the protection layer 208 is different from that of the sacrificial layer 202, can effectively avoid the damage of etching to the source-drain doped layer by the protection layer 208 in the subsequent process of removing the sacrificial layer 202, so as to improve the performance of the finally formed semiconductor structure.

In this embodiment, in the process of forming the protective layer 208 on the surface of the groove 207, the method further includes: the protective layer 208 is formed on the sidewall of the channel layer 201 exposed by the source-drain opening 206, so that the distance between the gate structure and the source-drain doped layer can be continuously increased, and short circuit between the gate structure and the source-drain doped layer is avoided.

In this embodiment, the material of the protection layer 208 is the same as that of the channel layer 201, so that electrical connection between the channel layer 201 and the source-drain doped layer can be ensured.

In this embodiment, the thickness of the protection layer 208 is 2 nm-5 nm, and when the thickness of the protection layer 208 is greater than 5nm, the gate-all-around sacrificial layer material is excessively consumed, so that the gate-all-around metal material is smaller in filling width, and the control capability of the gate-all-around on the channel is reduced; when the thickness of the protective layer 208 is less than 2nm, the effect of improving the trailing of the etching profile of the side wall gap of the sacrificial layer cannot be achieved, and the side wall forming defect is caused.

Referring to fig. 10, after the protective layer 208 is formed, a barrier layer 209 is formed in the recess 207.

In this embodiment, the method for forming the barrier layer 209 includes: forming a first initial barrier layer (not shown) within the recess 207, the source drain opening 206 sidewalls and bottom surfaces, and the sidewalls and top surfaces of the dummy gate structure 204; etching back the first initial barrier layer until the bottom surfaces of the source and drain openings 206 and the top surfaces of the dummy gate structures 204 are exposed, forming a second initial barrier layer (not shown); the second initial barrier layer is etched back until the sidewalls of the channel layer 201 are exposed, forming the barrier layer 209.

The process of forming the first initial barrier layer includes a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. In this embodiment, the first initial barrier layer is formed by a chemical vapor deposition process.

In this embodiment, the material of the blocking layer 209 is silicon nitride.

Referring to fig. 11, after the barrier layer 209 is formed, a source-drain doped layer 210 is formed in the source-drain opening 206.

In this embodiment, the source-drain doped layer 210 has source-drain ions therein, and the source-drain ions are N-type ions. In other embodiments, the source-drain ions may also be P-type ions.

Referring to fig. 12, after the source-drain doped layer 210 is formed, a dielectric layer 211 is formed on the substrate 200, and the dielectric layer 211 covers the sidewalls of the dummy gate structure 204.

In this embodiment, the material of the dielectric layer 211 is silicon oxide.

Referring to fig. 13, after the dielectric layer 211 is formed, a gate structure 212 is formed.

In this embodiment, the method for forming the gate structure 212 includes: removing the dummy gate structure 204, and forming a gate opening (not labeled) in the dielectric layer 211; after forming the gate openings, removing the sacrificial layers 202 to form gate recesses (not shown) between adjacent channel layers 201 and the substrate 200; a gate structure 212 is formed within the gate opening and the gate recess, the gate structure 212 encasing several layers of the channel layer 201.

Accordingly, in an embodiment of the present invention, there is further provided a semiconductor structure, please continue to refer to fig. 13, including: a substrate 200, wherein the substrate 200 is provided with a fin structure, and the fin structure comprises a plurality of channel layers 201 which are overlapped and arranged along the normal direction of the surface of the substrate 200; a gate structure 212 on the substrate 200, the gate structure 212 crossing the fin structure, the gate structure 212 being located between adjacent channel layers 201 and surrounding a plurality of the channel layers 201, sidewalls of the gate structure 212 between adjacent channel layers 201 being recessed with respect to sidewalls of the channel layers 201; source-drain doped layers 210 located within the fin structure on both sides of the gate structure 212; a blocking layer 209 between the source/drain doped layer 210 and the gate structure 212, the blocking layer 209 being located on the sidewall of the gate structure 212 between the adjacent channel layers 201; a protective layer 208 located between the barrier layer 209 and the gate structure 212.

In this embodiment, since the protection layer 208 is formed by using the first epitaxial growth process, the sacrificial layer 202 is consumed continuously during the process of forming the protection layer 208 by using the first epitaxial growth process, so that the depth of the recess 207 is deepened, and the depth direction is perpendicular to the sidewall of the gate structure 212, so that the interval between the gate structure 212 and the source-drain doped layer 210 is increased. In addition, the protection layer 208 formed on the surface of the groove 207, where the material of the protection layer 208 is different from that of the sacrificial layer 202, can effectively avoid the damage of etching to the source-drain doped layer 210 by the protection layer 208 in the subsequent process of removing the sacrificial layer 202, so as to improve the performance of the finally formed semiconductor structure.

In this embodiment, the protection layer 208 is further located between the source-drain doped layer 210 and the channel layer 201, so that the space between the gate structure 212 and the source-drain doped layer 210 can be continuously increased, and short circuit between the gate structure 212 and the source-drain doped layer 210 is avoided.

In this embodiment, the material of the protection layer 208 is the same as that of the channel layer 201, so that the electrical connection between the channel layer 201 and the source-drain doped layer 210 can be ensured.

In this embodiment, the thickness of the protective layer 208 is 2nm to 5nm. When the thickness of the protective layer 208 is greater than 5nm, the gate-all-around sacrificial layer material is excessively consumed, so that the gate-all-around metal material has smaller filling width, and the control capability of the gate-all-around on the channel is reduced; when the thickness of the protective layer 208 is less than 2nm, the effect of improving the trailing of the etching profile of the side wall gap of the sacrificial layer cannot be achieved, and the side wall forming defect is caused. In this embodiment, silicon is used as the material of the channel layer 201; in other embodiments, the channel layer may also be made of silicon germanium.

In this embodiment, further comprising: and a dielectric layer 211 on the substrate 200, wherein the dielectric layer 211 covers the side wall of the gate structure 212.

In this embodiment, the material of the blocking layer 209 is silicon nitride.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (18)

1. A semiconductor structure, comprising:

the semiconductor device comprises a substrate, wherein the substrate is provided with a fin structure, and the fin structure comprises a plurality of channel layers which are overlapped and arranged along the normal direction of the surface of the substrate;

the grid structure is positioned on the substrate, spans across the fin part structure, is positioned between adjacent channel layers and coats a plurality of layers of the channel layers, and the side wall of the grid structure positioned between the adjacent channel layers is sunken relative to the side wall of the channel layer;

source-drain doped layers in the fin structures at both sides of the gate structure;

the barrier layer is positioned between the source-drain doped layer and the gate structure and is positioned on the side wall of the gate structure between the adjacent channel layers;

and a protective layer between the barrier layer and the gate structure.

2. The semiconductor structure of claim 1, wherein the protective layer is further located between the source drain doped layer and the channel layer.

3. The semiconductor structure of claim 1, wherein a material of the protective layer is the same as a material of the channel layer.

4. The semiconductor structure of claim 1, wherein the protective layer has a thickness of 2nm to 5nm.

5. The semiconductor structure of claim 1, wherein the material of the channel layer comprises: silicon or silicon germanium.

6. The semiconductor structure of claim 1, further comprising: and the dielectric layer is positioned on the substrate and covers the side wall of the grid structure.

7. The semiconductor structure of claim 1, wherein the material of the barrier layer comprises: silicon nitride.

8. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate is provided with a fin structure, the fin structure comprises a plurality of channel layers and a plurality of sacrificial layers which are overlapped and arranged along the normal direction of the surface of the substrate, and the channel layers and the sacrificial layers are made of different materials;

forming a dummy gate structure on the substrate, the dummy gate structure crossing the fin structure;

etching the fin portion structure by taking the pseudo gate structure as a mask, and forming source and drain openings in the fin portion structure;

etching part of the sacrificial layer exposed by the source drain opening to form a groove;

and forming a protective layer on the surface of the groove by adopting a first epitaxial growth process, wherein the material of the protective layer is different from that of the sacrificial layer.

9. The method of forming a semiconductor structure of claim 8, wherein during forming a protective layer on a surface of the recess, further comprising: and forming the protective layer on the side wall of the channel layer exposed by the source drain opening.

10. The method of forming a semiconductor structure of claim 8, wherein a material of the protective layer is the same as a material of the channel layer.

11. The method of forming a semiconductor structure of claim 8, wherein the protective layer has a thickness of 2nm to 5nm.

12. The method of forming a semiconductor structure of claim 8, wherein the material of the channel layer comprises: silicon or silicon germanium; the material of the sacrificial layer comprises germanium silicon or silicon.

13. The method of forming a semiconductor structure of claim 8, wherein the sacrificial layer is located between adjacent channel layers and the substrate or between adjacent channel layers.

14. The method of forming a semiconductor structure of claim 8, wherein the sacrificial layer comprises a bottom region, a middle region on the bottom region, and a top region on the middle region, and the germanium atom content in the middle region is higher than the germanium atom content in the bottom region and the top region.

15. The method of forming a semiconductor structure of claim 8, further comprising, after forming the protective layer: forming a barrier layer in the groove; forming a source-drain doping layer in the source-drain opening; and forming a dielectric layer on the substrate, wherein the dielectric layer covers the side wall of the pseudo gate structure.

16. The method of forming a semiconductor structure of claim 15, wherein the method of forming a barrier layer comprises: forming a first initial barrier layer in the groove, on the side wall and the bottom surface of the source drain opening, and on the side wall and the top surface of the pseudo gate structure; etching back the first initial barrier layer until the bottom surfaces of the source and drain openings and the top surfaces of the pseudo gate structures are exposed, and forming a second initial barrier layer; and etching back the second initial barrier layer until the side wall of the channel layer is exposed, so as to form the barrier layer.

17. The method of forming a semiconductor structure of claim 15, wherein the material of the barrier layer comprises: silicon nitride.

18. The method of forming a semiconductor structure of claim 15, further comprising, after forming the dielectric layer: removing the pseudo gate structure and forming a gate opening in the dielectric layer; removing the sacrificial layers after the gate openings are formed, and forming gate grooves between adjacent channel layers and between the adjacent channel layers and the substrate; and forming a gate structure in the gate opening and the gate groove, wherein the gate structure wraps a plurality of layers of channel layers.