CN117374073A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN117374073A
CN117374073A CN202210766098.6A CN202210766098A CN117374073A CN 117374073 A CN117374073 A CN 117374073A CN 202210766098 A CN202210766098 A CN 202210766098A CN 117374073 A CN117374073 A CN 117374073A
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layer
fin
forming
top fin
dielectric layer
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate, wherein the substrate comprises a substrate and a plurality of fin structures which are separated on the substrate, and the fin structures comprise bottom fin parts, sacrificial layers positioned on the bottom fin parts and top fin parts positioned on the sacrificial layers; forming an isolation layer surrounding the bottom fin portion and the sacrificial layer on the substrate, wherein the isolation layer exposes the top fin portion; forming a gate structure on the isolation layer across the top fin; removing the isolation layer with partial thickness of the exposed gate structure and the top fin part, and exposing the side wall of the sacrificial layer; removing the sacrificial layer, and forming a gap between the bottom fin part and the top fin part; the dielectric layer sealing the gap is formed, so that isolation between the top fin portion and the bottom fin portion is realized, parasitic devices are prevented from being formed in the bottom fin portion, leakage current of a semiconductor structure is correspondingly reduced, electrical performance of the devices is improved, and the device is compatible with a process for forming a fin field effect transistor, and process compatibility is improved and cost is reduced.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
To better accommodate the demands of device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as: fin field effect transistors (finfets), and Gate-all-around (GAA) transistors, among others. In the Fin-type field effect transistor, three sides of a gate surround a channel of a Fin shape (Fin); in a fully-surrounding gate transistor, the gate surrounds the region where the channel is located from the periphery. Compared with a planar transistor, the fin field effect transistor and the gate electrode of the full-surrounding gate transistor have stronger control capability on a channel, and can better inhibit short channel effect.
However, the leakage current problem of the current device is still serious. Taking a Gate-all-around (GAA) as an example, the source-drain doped layer is located on and also in contact with the raised portion, which results in parasitic devices being formed in the raised portion under the channel structure layer, causing leakage currents to also be generated in the raised portion under the channel structure layer. In particular, when the source-drain doped layer is further embedded in the protruding portion, a raised fin structure is formed between the source-drain doped layers located at two sides of the gate structure, so that a parasitic channel is formed in the fin structure, the leakage current of the device is more serious, and when the depth of the source-drain doped layer embedded in the protruding portion is deeper, the leakage current of the device is more serious.
There are two approaches currently in an attempt to reduce the leakage current of semiconductor structures. Referring to fig. 1, there is shown a schematic structural diagram of a semiconductor structure, which includes: a base 10, wherein a plurality of discrete protrusions 16 are formed on the base 10; a channel structure layer 11 located on the raised portion 16 and spaced apart from the raised portion 16, the channel structure layer 11 including one or more channel layers 12 spaced apart from each other; a gate structure 13 crossing the channel structure layer 11 and also located between adjacent channel layers 12 or between a raised portion 16 and a channel layer 12 adjacent to the raised portion 16, the gate structure 20 surrounding the channel layer 12; source-drain doped layers 14 located on both sides of the gate structure 13 and covering the sidewalls of the channel structure layer 11; and an isolation layer 15 located between the raised portion 16 and the source-drain doped layer 14.
In the semiconductor structure shown in fig. 1, the isolation layer 15 is disposed between the source-drain doped layer 14 and the raised portion 16 to isolate the source-drain doped layer 14 from the raised portion 16, so that the source-drain doped layer 14 cannot contact the raised portion 16 to reduce leakage current generated in the raised portion 16 under the channel structure layer 11. However, the source/drain doped layer 14 is usually formed by an epitaxy process, and the isolation layer 15 is disposed between the bottom of the source/drain doped layer 14 and the raised portion 16, which greatly affects the epitaxy process for forming the source/drain doped layer 14, and further results in poor quality of the formation of the source/drain doped layer 14 and poor performance of the semiconductor structure.
Referring to fig. 2, there is shown a schematic structural diagram of another semiconductor structure, which includes: a base 20, the base 20 having a plurality of discrete protrusions 26 formed thereon; an isolating layer 25 on the boss 26; a channel structure layer 21 on the isolation layer 25 and spaced apart from the isolation layer 25, the channel structure layer 21 including one or more channel layers 22 spaced apart from each other; a gate structure 23 crossing the channel structure layer 21 and also located between adjacent channel layers 22 or between an isolation layer 25 and a channel layer 22 adjacent to the isolation layer 25, the gate structure 23 surrounding the channel layer 22; and a source-drain doped layer 24 which is positioned on the isolating layers 25 at two sides of the gate structure 23 and covers the side wall of the channel structure layer 21.
In the semiconductor structure shown in fig. 2, the isolation layer 25 is disposed below the channel structure layer 21, the gate structure 23 and the source-drain doped layer 24, so that the whole device is isolated from the protruding portion 26 by the isolation layer 25, and accordingly leakage current generated in the protruding portion 26 is reduced. The isolation layer 25 is disposed between the bottom of the source/drain doped layer 24 and the raised portion 26, which also affects the epitaxy process for forming the source/drain doped layer 24, resulting in poor quality of the source/drain doped layer 24 and poor performance of the semiconductor structure. Also, a specific method of forming the isolation layer 25 is not disclosed at present.
For fin field effect transistors (finfets), the above-described problems also exist by providing an isolation layer at the bottom of the source-drain doped layer, or below the source-drain doped layer and the active fin.
Therefore, a new method is needed to reduce the leakage current of the device.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, reducing leakage current and improving process compatibility.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; the fin structures are separated on the substrate and comprise bottom fin parts and top fin parts which are suspended on the bottom fin parts, and gaps are reserved between the bottom fin parts and the top fin parts; a dielectric layer sealing the gap; an isolation layer on the substrate and surrounding the bottom fin; a device gate structure located on the isolation layer and crossing the top fin; and the source-drain doped region is positioned in the top fin parts at two sides of the grid electrode structure.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a plurality of fin structures which are separated on the substrate, and the fin structures comprise bottom fin parts, sacrificial layers positioned on the bottom fin parts and top fin parts positioned on the sacrificial layers; forming an isolation layer surrounding the bottom fin portion and the sacrificial layer on the substrate, wherein the isolation layer exposes the top fin portion; forming a gate structure on the isolation layer across the top fin; removing the isolation layer with partial thickness of the exposed gate structure and the top fin portion after forming the gate structure, and exposing the side wall of the sacrificial layer; removing the sacrificial layer, and forming a gap between the bottom fin portion and the top fin portion; forming a dielectric layer sealing the gap; after forming the dielectric layer, source-drain doped regions are formed in the top fin portions at two sides of the gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the semiconductor structure provided by the embodiment of the invention, the fin structure comprises a bottom fin part and a top fin part suspended on the bottom fin part, and a gap is formed between the bottom fin part and the top fin part; the dielectric layer seals the gap, thereby realizing the isolation between the top fin part and the bottom fin part, being beneficial to preventing parasitic devices from being formed in the bottom fin part, correspondingly reducing the leakage current of the semiconductor structure, improving the electrical property of the devices, being compatible with the process for forming the fin field effect transistor, being beneficial to improving the process compatibility and reducing the cost.
In the method for forming a semiconductor structure provided by the embodiment of the invention, in the step of providing the substrate, the fin structure further comprises a sacrificial layer positioned between the bottom fin portion and the top fin portion; after forming the gate structure, exposing the side wall of the sacrificial layer except for the gate structure and the isolation layer with partial thickness of the exposed top fin part; removing the sacrificial layer, and forming a gap between the bottom fin portion and the top fin portion; and then forming a dielectric layer for sealing the gap, thereby realizing the isolation between the top fin part and the bottom fin part, being beneficial to preventing parasitic devices from being formed in the bottom fin part, correspondingly reducing the leakage current of the semiconductor structure, improving the electrical property of the devices, being compatible with the process for forming the fin field effect transistor, and being beneficial to improving the process compatibility and reducing the cost.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
FIG. 2 is a schematic diagram of another semiconductor structure;
FIGS. 3-6 are schematic diagrams illustrating an embodiment of a semiconductor structure according to the present invention;
fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
In view of the background art, a new method is needed to reduce the leakage current of the device.
In order to solve the technical problems, the embodiment of the invention provides a semiconductor structure, which comprises a bottom fin part and a top fin part suspended on the bottom fin part, wherein a gap is formed between the bottom fin part and the top fin part; the dielectric layer seals the gap, thereby realizing the isolation between the top fin part and the bottom fin part, being beneficial to preventing parasitic devices from being formed in the bottom fin part, correspondingly reducing the leakage current of the semiconductor structure, improving the electrical property of the devices, being compatible with the process for forming the fin field effect transistor, being beneficial to improving the process compatibility and reducing the cost.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Referring to fig. 3-6, schematic structural diagrams of an embodiment of the semiconductor structure of the present invention are shown. Wherein fig. 3 is a perspective view, fig. 4 is a cross-sectional view of fig. 3 along the direction of extension of the top fin, fig. 5 is a cross-sectional view of fig. 4 along the direction B1-B1, fig. 6 is a cross-sectional view of fig. 4 along the direction B2-B2,
as shown in fig. 3 to 6, in the present embodiment, the semiconductor structure includes: a substrate 100; a plurality of fin structures 110, separated on the substrate 100, wherein the fin structures 110 comprise a bottom fin 10 and a top fin 20 suspended on the bottom fin 10, and a gap is formed between the bottom fin 10 and the top fin 20; a dielectric layer 50 sealing the gap; an isolation layer 420 on the substrate 100 and surrounding the bottom fin 10; a device gate structure 470 located on the isolation layer 420 and crossing the top fin 20; the source-drain doped regions 200 are located in the top fin 20 at two sides of the gate structure 270.
The substrate 100 is used to provide a process platform for the formation of semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is monocrystalline silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.
The fin structure 110 is used for forming a top fin 20 that is suspended from the bottom fin 10 at intervals.
The bottom fin 10 and the top fin 20 have a gap therebetween, so that the gap is sealed by the dielectric layer 50, thereby isolating the bottom fin 10 and the top fin 20.
Wherein the bottom fin 10 is used to provide support for the top fin 20. The bottom fin 10 also serves to provide a process basis for forming the isolation layer 420 such that the isolation layer 420 can surround the bottom fin 10 and can expose the top fin 20, thereby enabling isolation between adjacent bottom fins 10, as well as isolating the substrate 100 and the device gate structure 470.
The material of the bottom fin 10 is a semiconductor material. The material of the bottom fin 10 includes one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.
In this embodiment, the bottom fin 10 and the substrate 100 are integrally formed. The material of the bottom fin 10 is the same as the material of the substrate 100, both being silicon.
The top fin 20 serves as an active fin, and the top fin 20 serves to provide a conductive channel for the field effect transistor during operation of the device.
The material of the top fin 20 is a semiconductor material. In this embodiment, the material of the top fin 20 includes one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.
It should be noted that, in the direction perpendicular to the substrate 100, the distance between the top surface of the bottom fin 10 and the bottom surface of the top fin 20 should not be too small or too large. The distance between the top surface of the bottom fin portion 10 and the bottom surface of the top fin portion 20 is too small, so that the difficulty in forming the gap is easily increased; if the distance between the top surface of the bottom fin 10 and the bottom surface of the top fin 20 is too large, the height of the fin structure 110 is easily too large, and the difficulty of the process for forming the fin structure 110 is easily increased. For this reason, in the present embodiment, the distance between the top surface of the bottom fin 10 and the bottom surface of the top fin 20 is 5nm to 15nm in the direction perpendicular to the substrate 100.
Note that the fin structure 110 is formed by a process of a fin field effect transistor. In this embodiment, the width of the top fin 20 is the first dimension along the direction perpendicular to the extending direction of the fin structure 110; the top fin 20 has a height of a second dimension along a direction perpendicular to the substrate 100; the first dimension is smaller than the second dimension, i.e., the aspect ratio of the top fin 20 is relatively large, satisfying the characteristics of the fin structure.
As an example, the ratio of the first size to the second size ranges from 1:2 to 1:5.
It should also be noted that the fin structure 110 is formed by a process of a fin field effect transistor. In this embodiment, along the direction perpendicular to the extending direction of the fin structure 110, the top width of the top fin 20 is smaller than the bottom width of the top fin 20, that is, along the direction perpendicular to the extending direction of the fin structure 110, the cross section of the top fin 20 is a structure with a smaller top and a larger bottom, which also satisfies the morphological feature of the fin structure.
The dielectric layer 50 seals the gap, thereby achieving isolation between the top fin 20 and the bottom fin 10, facilitating prevention of parasitic devices from forming in the bottom fin 10, correspondingly reducing leakage current of the semiconductor structure, improving electrical performance of the device, and also being compatible with processes for forming fin field effect transistors, facilitating improved process compatibility and reduced cost.
The material of the dielectric layer 50 is an insulating dielectric material, for example: the material of the dielectric layer 50 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the dielectric layer 50 is the same as the material of the isolation layer 420, which is advantageous for further improving process compatibility. In this embodiment, the material of the isolation layer 420 is silicon oxide, and the material of the dielectric layer 50 is also silicon oxide. In other embodiments, the material of the dielectric layer may also be different from the material of the isolation layer.
In this embodiment, taking the example that the dielectric layer 50 fills the gap 40 as an example, it is beneficial to improve the isolation effect of the dielectric layer 50 between the bottom fin 10 and the top fin 20. In other embodiments, the dielectric layer 50 may also seal only the gap.
The isolation layer 420 is used to achieve electrical isolation between the bottom fins 10.
In this embodiment, the isolation layer 420 surrounds the bottom fin 10 and exposes the top fin 20, so that the device gate structure 470 can span the top fin 20 and cover a portion of the top and a portion of the sidewalls of the top fin 20, thereby forming a conductive channel in the top fin 20 covered by the device gate structure 470 when the device is in operation. In addition, the device gate structure 470 is formed on the isolation layer 420, and the isolation layer 420 surrounds the bottom fin 10, so that the depth of the bottom of the device gate structure 470 is too deep, which is beneficial to keeping a certain distance between the bottom of the device gate structure 470 and the bottom fin 10, and further reducing the probability of parasitic devices generated in the bottom fin 10.
In this embodiment, the isolation layer 420 is a shallow trench isolation structure (Shallow trench isolation, STI). In this embodiment, the material of the isolation layer 420 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other insulating materials such as silicon oxynitride.
In this embodiment, the isolation layer 420 between the substrate 100 and the device gate structure 470 serves as a first isolation layer (not shown); the spacer 420 on the substrate 100 on the side of the device gate structure 470 acts as a second spacer (not shown).
Wherein a top surface of the first isolation layer is in contact with a bottom surface of the device gate structure 470; the top surface of the second isolation layer is lower than the top surface of the first isolation layer, and the second isolation layer exposes the dielectric layer 50.
The top surface of the second isolation layer is lower than the top surface of the first isolation layer, and the second isolation layer exposes the dielectric layer 50, because a sacrificial layer is further formed between the bottom fin 10 and the top fin 20 during the formation of the semiconductor structure, and the gap is formed by removing the sacrificial layer. During the formation of the semiconductor structure, the sacrificial layer can be removed by removing a portion of the thickness of the gate structure exposing the spacer 420 to expose the sacrificial layer. Accordingly, after the sacrificial layer is removed to form the gap, the top surface of the isolation layer 420 at the side of the gate structure is lower than the top surface of the isolation layer 420 under the gate structure, i.e., the top surface of the second isolation layer is lower than the top surface of the first isolation layer, and the second isolation layer exposes the dielectric layer 50, i.e., the second isolation layer exposes the gap during the formation of the semiconductor structure, so as to form the dielectric layer 50 in the gap.
The device gate structure 470 is used to control the opening and closing of the conduction channel during device operation.
In this embodiment, the device Gate structure 470 is a Metal Gate (Gate) structure, and the device Gate structure 470 is formed by a process of forming a Metal Gate (high k last Metal Gate last) by forming a high-k Gate dielectric layer.
In this embodiment, the device gate structure 470 includes a work function layer (not shown) and a gate electrode layer (not shown) on the work function layer.
The work function layer is used for adjusting the work function of the metal gate structure, so that the effect of adjusting the threshold voltage of the transistor is achieved. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
The electrode material layer is used as an electrode for leading out the electricity of the metal gate structure, so that the metal gate structure is electrically connected with an external circuit. In this embodiment, the material of the electrode material layer is W. In other embodiments, the material of the electrode material layer may also be Al, cu, ag, au, pt, ni or Ti, etc.
In this embodiment, a gate dielectric layer 70 is further formed between the device gate structure 470 and the top fin 20, and the gate dielectric layer 70 is used to electrically isolate the device gate structure 470 from the top fin 20.
In this embodiment, the gate dielectric layer 70 comprises a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. As an example, the material of the high-k gate dielectric layer is hafnium oxide (HfO 2 )。
In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer. Wherein, the material of the gate oxide layer comprises one or two of silicon oxide and silicon oxynitride. In still other embodiments, the gate dielectric layer may also include only a gate oxide layer.
In this embodiment, a sidewall 460 is further formed on the sidewall of the device gate structure 470, and the sidewall 460 is used for protecting the sidewall of the device gate structure 470 and defining the formation position of the source-drain doped region 200.
In this embodiment, the side wall 460 is further formed on the side wall of the top fin 20, so that the side wall 460 can protect the side wall of the top fin 20 in the step of forming the gap in the process of forming the semiconductor structure.
In an embodiment, the sidewall 460 may include a plurality of sub-sidewalls (not shown) sequentially stacked on the sidewall of the device gate structure 470; wherein, the material of at least one of the sub-side walls is the same as the material of the dielectric layer 50.
The material of at least one sub-sidewall in the sidewall 460 is the same as the material of the dielectric layer 50, so that the sub-sidewall can be formed by using the process step of forming the dielectric layer 50 in the process of the semiconductor structure, and the forming process of the dielectric layer 50 and the forming process of the sidewall 460 can be combined, thereby further improving the process integration degree and the process compatibility.
As an example, the material of the side wall 460 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the side wall 460 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 460 has a single-layer structure, and the material of the side wall 460 is silicon nitride.
The source-drain doped region 200 is used as a source or drain of a field effect transistor, and the source-drain doped region 200 is used to provide a carrier source when the field effect transistor is operating.
In this embodiment, the source-drain doped region 200 includes a stress layer doped with ions, and the source-drain doped region 200 is further used to provide stress to the channel, so as to improve the carrier mobility of the channel.
Specifically, when the NMOS transistor is formed, the material of the source-drain doped region 200 is a stress layer doped with N-type ions, the material of the stress layer includes Si or SiC, and the stress layer provides a tensile stress effect for the channel region of the NMOS transistor, so that it is beneficial to improve the carrier mobility of the NMOS transistor, where the N-type ions are P ions, as ions, or Sb ions.
When forming a PMOS transistor, the material of the source-drain doped region 200 is a stress layer doped with P-type ions, where the material of the stress layer includes Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
It should be noted that, in this embodiment, the bottom surface of the source-drain doped region 200 is higher than the bottom surface of the top fin portion 20, so as to prevent the source-drain doped region 200 from contacting the dielectric layer 50 located below the top fin portion 20, further ensure that the formation process of the source-drain doped region 200 is not affected by the dielectric layer 50, and accordingly ensure the formation quality of the source-drain doped region 200.
In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 90 is located on the isolation layer 420 on the side of the device gate structure 470.
Interlayer dielectric layer 90 is used to isolate adjacent device gate structures 470, thereby achieving electrical isolation between adjacent devices. The interlayer dielectric layer 90 may have a single layer or a stacked structure. The material of interlayer dielectric layer 90 is an insulating material such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
Correspondingly, the invention further provides a method for forming the semiconductor structure. Fig. 7 to 17 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
The method for forming the semiconductor structure of the present embodiment will be described in detail below with reference to the accompanying drawings.
Referring to fig. 7, a base is provided comprising a substrate 100 and a plurality of fin structures 110 separated on the substrate 100, the fin structures 110 comprising a bottom fin 10 and a sacrificial layer 30 on the bottom fin 10, and a top fin 20 on the sacrificial layer 30.
The substrate is used for providing a process platform for subsequent processes.
In this embodiment, the substrate 100 is a silicon substrate, that is, the material of the substrate 100 is monocrystalline silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.
The fin structure 110 is used to subsequently form a top fin 20 spaced apart from the bottom fin 10.
Wherein the bottom fin 10 is used to provide support for the sacrificial layer 30 and the top fin 20. The bottom fin 10 also serves to provide a process basis for the subsequent formation of an isolation layer so that the isolation layer can surround the bottom fin 10 and the sacrificial layer 30 and can expose the top fin 20, thereby enabling isolation between adjacent bottom fins 10, as well as isolating the substrate 100 and the gate structure.
The material of the bottom fin 10 is a semiconductor material. The material of the bottom fin 10 includes one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.
In this embodiment, the bottom fin 10 and the substrate 100 are integrally formed. The material of the bottom fin 10 is the same as the material of the substrate 100, both being silicon.
In this embodiment, the fin structure 110 further includes a sacrificial layer 30, so that the sacrificial layer 30 is removed subsequently, and a gap is formed between the bottom fin portion 10 and the top fin portion 20, so as to form a dielectric layer for sealing the gap, thereby realizing isolation between the top fin portion 20 and the bottom fin portion 10, being beneficial to preventing parasitic devices from being formed in the bottom fin portion 10, and correspondingly reducing leakage current of the semiconductor structure. Furthermore, by providing the sacrificial layer 30 in the fin structure 110, it is also compatible with the process of forming the fin field effect transistor, which is advantageous for improving the process compatibility and reducing the cost.
For this reason, the sacrificial layer 30 is made of a material having etching selectivity to the materials of the bottom fin 10 and the top fin 20, so as to achieve a high etching selectivity between the sacrificial layer 30 and the bottom fin 10 and between the sacrificial layer 30 and the top fin 20 in the subsequent step of removing the sacrificial layer 30, thereby reducing the difficulty of removing the sacrificial layer 30 and reducing the damage probability of the top fin 20 and the bottom fin 10.
In this embodiment, in the step of providing the substrate, the material of the sacrificial layer 30 includes one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide. The material of the sacrificial layer 30 is different from the material of both the bottom fin 10 and the top fin 20. Specifically, in this embodiment, the material of the bottom fin 10 is silicon, and the material of the sacrificial layer 30 is silicon germanium.
The thickness of the sacrificial layer 30 should not be too small or too large. If the thickness of the sacrificial layer 30 is too small, the difficulty of the subsequent process for removing the sacrificial layer 30 is easily increased; if the thickness of the sacrificial layer 30 is too large, the height of the fin structure 110 is easily increased, and thus the process difficulty of forming the fin structure 110 is easily increased. For this purpose, in this embodiment, the thickness of the sacrificial layer is 5nm to 15nm.
The top fin 20 serves as an active fin, and the top fin 20 serves to provide a conductive channel for the field effect transistor during operation of the device.
The material of the top fin 20 is a semiconductor material. In this embodiment, the material of the top fin 20 includes one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide.
As one example, the step of providing a substrate includes: forming a first semiconductor layer (not shown), a sacrificial material layer (not shown), and a second semiconductor layer (not shown) stacked in this order; patterning the second semiconductor layer, the sacrificial material layer and a portion of the thickness of the first semiconductor layer, the remaining second semiconductor layer being used as the top fin, the remaining sacrificial material layer being used as the sacrificial layer, and forming a substrate and the bottom fin protruding from the substrate in the remaining first semiconductor layer.
In this embodiment, the material of the sacrificial material layer is a semiconductor material, and the process of forming the sacrificial material layer includes an epitaxial process.
With continued reference to fig. 7, an isolation layer 420 is formed on the substrate 100 surrounding the bottom fin 10 and the sacrificial layer 30, the isolation layer 420 exposing the top fin 20.
The isolation layer 420 is used to achieve electrical isolation between the bottom fins 10.
In this embodiment, the isolation layer 420 surrounds the bottom fin 10 and the sacrificial layer 30, and exposes the top fin 20, so that the subsequently formed gate structure can span the top fin 20 and cover part of the top and part of the sidewalls of the top fin 20, and thus a conductive channel can be formed in the top fin 20 covered by the gate structure when the device is in operation. And, the subsequent gate structure is formed on the isolation layer 420, the isolation layer 420 surrounds the bottom fin 10 and the sacrificial layer 30, so that the depth of the bottom of the gate structure is prevented from being too deep, a certain distance is kept between the bottom of the gate structure and the bottom fin 10, and the probability of parasitic devices in the bottom fin 10 is further reduced.
In implementations, the isolation layer 420 may cover the sidewalls of the bottom fin 10 and the sacrificial layer 30, i.e., the top surface of the isolation layer 420 is flush with the top surface of the sacrificial layer 30. In other embodiments, the isolation layer may cover the sidewalls of the bottom fin and portions of the sidewalls of the sacrificial layer, i.e., the top surface of the isolation layer may be lower than the top surface of the sacrificial layer.
In this embodiment, the isolation layer 420 is a shallow trench isolation structure (Shallow trench isolation, STI). In this embodiment, the material of the isolation layer 420 is silicon oxide. In other embodiments, the material of the isolation layer may be silicon nitride or other insulating materials such as silicon oxynitride.
Referring to fig. 8, a gate structure 440 is formed on the isolation layer 420 across the top fin 20.
In this embodiment, the gate structure 440 is a dummy gate structure, and the dummy gate structure is used to occupy a space for forming the gate structure of the device.
In other embodiments, the gate structure may also be a device gate structure.
In this embodiment, the gate structure 440 spans across the top fin 20 and covers a portion of the top and a portion of the sidewalls of the top fin 20.
In this embodiment, the gate structure 440 is a dummy gate structure, and the dummy gate structure includes a dummy gate layer. The material of the dummy gate layer comprises polysilicon or amorphous silicon.
In this embodiment, a dummy gate oxide layer 430 is further formed between the gate structure 440 and the top fin 20, where the dummy gate oxide layer 430 is used to isolate the top fin 20 from the gate structure 440, and is also used to perform an etching stop function in a subsequent process of removing the gate structure 440, thereby reducing the probability of damage to the top fin 20.
The material of the dummy gate oxide layer 430 is silicon oxide or silicon oxynitride.
In this embodiment, a gate mask layer 450 is further formed on top of the gate structure 440, and the gate mask layer 450 is used as an etching mask for forming the gate structure 440 and also used for protecting the top of the gate structure 440.
In this embodiment, the material of the gate mask layer 440 is silicon nitride.
Referring to fig. 9, in this embodiment, the method for forming a semiconductor structure further includes: after forming the gate structure 440, a sidewall 460 is formed on the sidewall of the gate structure 440, and the sidewall 460 is also formed on the sidewall of the top fin 20, before removing the gate structure 440 and the spacer 420 of the exposed portion of the thickness of the top fin 20.
The sidewall 460 is used for protecting the sidewall of the gate structure 440 and defining the formation location of the subsequent source-drain doped region.
In this embodiment, the sidewall 460 is further formed on the sidewall of the top fin 20, so that the sidewall of the top fin 20 can be protected during the subsequent steps of removing the gate structure 440 and the isolation layer 420 with the exposed portion of the thickness of the top fin 20, and removing the sacrificial layer 30.
The material of the side wall 460 may be one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide or silicon oxycarbonitride, boron nitride and boron carbonitride, and the side wall 460 may have a single-layer structure or a stacked-layer structure. In this embodiment, the side wall 460 has a single-layer structure, and the material of the side wall 460 is silicon nitride.
In this embodiment, the sidewall 460 also covers the sidewall of the gate mask layer 450.
As an example, the forming of the sidewall 460 includes: forming a sidewall material layer (not shown) on the top and sidewalls of the gate structure 440, the top and sidewalls of the top fin 20, and the top surface of the isolation layer 420; the sidewall material layer on top of the gate structure 440 and the top fin 20 and the isolation layer 420 is removed by an anisotropic etching process, and the remaining sidewall material layer on the sidewalls of the gate structure 440 and the top fin 20 is used as the sidewall 460.
Referring to fig. 10, after the gate structure 440 is formed, the isolation layer 420 is removed to expose the sidewalls of the sacrificial layer 30, and the gate structure 440 and the exposed portion of the top fin 20.
The gate structure 440 and the exposed portion of the thickness of the isolation layer 420 of the top fin 20 are removed, exposing the sidewalls of the sacrificial layer 30, so that the sacrificial layer 30 is subsequently removed through the exposed sidewalls of the sacrificial layer 30.
In this embodiment, before removing the isolation layer 420 with the exposed portion of the thickness of the gate structure 440 and the top fin 20, a sidewall 460 is further formed on the sidewalls of the gate structure 440 and the top fin 20, so that the step of removing the isolation layer 420 with the exposed portion of the thickness of the gate structure 440 and the top fin 20 includes: removing the exposed part of the thickness isolation layer 420 of the gate structure 440, the top fin 20 and the sidewall 460; the isolation layer 420 at the bottom of the sidewall 460 of the top fin 20 is removed, and the sidewall of the sacrificial layer 30 is exposed.
After removing the isolation layer 420 with the thickness of the exposed portion of the gate structure 440, the top fin 20 and the sidewall 460, the isolation layer 420 at the bottom of the sidewall 460 of the sidewall of the top fin 20 is also removed, so that the sidewall of the sacrificial layer 30 is exposed, so that the sacrificial layer 30 is removed through the exposed sidewall of the sacrificial layer 30.
In this embodiment, an anisotropic etching process is used to remove the portion of the thickness of the isolation layer 420 exposed by the gate structure 440, the top fin 20, and the sidewall 460, so as to achieve thickness reduction of the isolation layer 420 along the direction perpendicular to the substrate 100.
In particular embodiments, the anisotropic etching process may include an anisotropic dry etching process.
In this embodiment, an isotropic etching process is used to remove the isolation layer 420 at the bottom of the sidewall 460 of the sidewall of the top fin 20. The isotropic etching process has an isotropic etching property, so that the isolation layer 420 can be laterally etched along a direction parallel to the substrate 100, and the isolation layer 420 located at the bottom of the sidewall 460 of the sidewall of the top fin 20 can be removed to expose the sidewall of the sacrificial layer 30.
In a specific embodiment, the isotropic etching process may be an isotropic dry etching process or an isotropic wet etching process, or a combination of isotropic dry etching and wet etching process.
In this embodiment, the spacer 420 is taken as an example to remove the exposed portion of the gate structure 440 and the top fin 20 after the sidewall 460 is formed.
In other embodiments, the method for forming a semiconductor structure further includes: after the grid structure is formed, before the grid structure and the isolation layer with the partial thickness exposed by the top fin portion are removed, a first side wall is formed on the side wall of the grid structure, and the first side wall is also formed on the side wall of the top fin portion. The first sidewall is used for protecting the sidewall of the gate structure, and the first sidewall can be used as a part of the sidewall, or the first sidewall can be used as a sacrificial sidewall, and the first sidewall is removed correspondingly. Correspondingly, the thickness of the first side wall is smaller, and the step of removing the isolation layer with the thickness of the exposed part of the gate structure and the top fin part comprises the following steps: and removing the grid structure, the top fin part and the isolation layer with partial thickness exposed from the first side wall. In the step of removing the gate structure, the top fin portion and the part of the isolation layer with the thickness exposed from the first side wall, the part of the isolation layer with the thickness below the first side wall of the top fin portion is conveniently removed in an over-etching mode due to the smaller thickness of the first side wall, so that the side wall of the sacrificial layer is exposed.
Specifically, an anisotropic etching process is adopted to remove the gate structure, the top fin portion and the isolation layer with partial thickness exposed from the first side wall.
Referring to fig. 11, the sacrificial layer 30 is removed, forming a gap 40 between the bottom fin 10 and the top fin 20.
The sacrificial layer 30 is removed and a gap 40 is formed so that a dielectric layer is subsequently formed in the gap 40, whereby isolation between the bottom fin 10 and the top fin 20 is achieved by the dielectric layer.
In this embodiment, the process of removing the sacrificial layer 30 includes an isotropic etching process. The isotropic etching process has an isotropic etching characteristic, so that the sacrificial layer 30 can be etched in a direction parallel to the substrate 100, thereby removing the sacrificial layer 30.
In a specific embodiment, the isotropic etching process includes one or both of isotropic dry etching and wet etching.
Referring to fig. 12, a dielectric layer 50 is formed that seals the gap 40.
The formation of the dielectric layer 50 sealing the gap 40, thereby achieving isolation between the top fin 20 and the bottom fin 10, facilitating the prevention of parasitic devices formed in the bottom fin 10, correspondingly reducing leakage current of the semiconductor structure, improving electrical performance of the device, and also being compatible with processes for forming fin field effect transistors, facilitating improved process compatibility and reduced cost.
The material of the dielectric layer 50 is an insulating dielectric material, for example: the material of the dielectric layer 50 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. As an example, the material of the dielectric layer 50 is the same as the material of the isolation layer 420, which is advantageous for further improving process compatibility. In this embodiment, the material of the isolation layer 420 is silicon oxide, and the material of the dielectric layer 50 is also silicon oxide. In other embodiments, the material of the dielectric layer may also be different from the material of the isolation layer.
In this embodiment, taking the example that the dielectric layer 50 fills the gap 40 as an example, it is beneficial to improve the isolation effect of the dielectric layer 50 between the bottom fin 10 and the top fin 20. In other embodiments, the dielectric layer 50 may also seal only the gap.
As one example, the dielectric layer 50 is formed using an atomic layer deposition process. The atomic layer deposition process has a strong gap filling capability, which is beneficial to improving the filling quality of the dielectric layer 50 in the gap 40. In other embodiments, other suitable deposition processes may be used to form the dielectric layer. For example: and forming a dielectric layer by adopting a chemical vapor deposition process.
In other embodiments, after the gate structure is formed, before the isolation layer with the thickness of the exposed portion of the gate structure and the top fin is removed, a first sidewall is further formed on the sidewall of the gate structure, and when the first sidewall is further formed on the sidewall of the top fin, correspondingly, in the step of forming the dielectric layer, the dielectric layer is further formed on the sidewall of the first sidewall, the dielectric layer formed on the sidewall of the first sidewall is used as a second sidewall, and the second sidewall and the first sidewall are used to form the gate sidewall, so that the steps of forming the dielectric layer and forming the gate sidewall are integrated, which is beneficial to improving process integration and simplifying process flow.
Alternatively, in other embodiments, after removing the sacrificial layer and before forming the dielectric layer, the method of forming the semiconductor structure further includes: removing the first side wall; in the step of forming the dielectric layer, the dielectric layer is further formed on the side wall of the gate structure, and the dielectric layer formed on the side wall of the gate structure is used as the third side wall, so that the step of forming the dielectric layer and the gate side wall can be integrated, thereby being beneficial to improving the process integration degree and simplifying the process flow.
It should be noted that, in the step of forming the dielectric layer 50, the dielectric layer 50 is further formed on the top and the sidewalls of the top fin 20; after forming the dielectric layer 50 and before forming the source-drain doped regions, the method of forming the semiconductor structure further includes: the dielectric layer 50 on top of the top fin 20 is removed, exposing the top fin 20 for subsequent formation of source drain doping regions in the top fin 20.
Referring to fig. 13, after forming the dielectric layer 50, source-drain doped regions 200 are formed in the top fin 20 on both sides of the gate structure 440.
The source-drain doped region 200 is used as a source or drain of a field effect transistor, and the source-drain doped region 200 is used to provide a carrier source when the field effect transistor is operating.
In this embodiment, the source-drain doped region 200 includes a stress layer doped with ions, and the source-drain doped region 200 is further used to provide stress to the channel, so as to improve the carrier mobility of the channel.
Specifically, when the NMOS transistor is formed, the material of the source-drain doped region 200 is a stress layer doped with N-type ions, the material of the stress layer includes Si or SiC, and the stress layer provides a tensile stress effect for the channel region of the NMOS transistor, so that it is beneficial to improve the carrier mobility of the NMOS transistor, where the N-type ions are P ions, as ions, or Sb ions.
When forming a PMOS transistor, the material of the source-drain doped region 200 is a stress layer doped with P-type ions, where the material of the stress layer includes Si or SiGe, and the stress layer provides compressive stress to the channel region of the PMOS transistor, so as to facilitate improving carrier mobility of the PMOS transistor, and the P-type ions are B ions, ga ions, or In ions.
It should be noted that, in the step of forming the source-drain doped region 200 in this embodiment, the bottom surface of the source-drain doped region 200 is higher than the bottom surface of the top fin portion 20, so as to prevent the source-drain doped region 200 from contacting the dielectric layer 50 located below the top fin portion 20, further ensure that the formation process of the source-drain doped region 200 is not affected by the dielectric layer 50, and correspondingly ensure the formation quality of the source-drain doped region 200.
In a specific embodiment, the step of forming the source-drain doped region 200 may include: forming grooves (not shown) in the top fin 20 on both sides of the gate structure 440; the source-drain doped region 200 is formed in the recess.
Specifically, the process of forming the source-drain doped region 200 in the recess includes an epitaxial process. The bottom of the groove is correspondingly higher than the bottom surface of the top fin portion 20, so that the exposed material of the top fin portion 20 is ensured, and the formation quality of an epitaxial process for forming the source-drain doped region 200 in the groove is further ensured.
As an example, in this embodiment, the gate structure 440 is a dummy gate structure.
Accordingly, referring to fig. 14 to 17 in combination, fig. 14 is a perspective view based on fig. 13, fig. 15 is a cross-sectional view of fig. 14 along the extension direction of the top fin, fig. 16 is a cross-sectional view of fig. 15 along the direction B1-B1, and fig. 17 is a cross-sectional view of fig. 15 along the direction B2-B2, after forming the source-drain doped region 200, the method for forming a semiconductor structure further includes: forming an interlayer dielectric layer 90 on the isolation layer 420 at the side of the gate structure 440; removing the dummy gate structure, and forming a gate opening (not shown) in the interlayer dielectric layer 90; a device gate structure 470 is formed within the gate opening.
Interlayer dielectric layer 90 is used to isolate adjacent device gate structures 470, thereby achieving electrical isolation between adjacent devices. The interlayer dielectric layer 90 may have a single layer or a stacked structure. The material of interlayer dielectric layer 90 is an insulating material such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.
In this embodiment, in the step of forming the interlayer dielectric layer 90, the gate mask layer 450 is further removed, so as to expose the top of the gate structure 440, and then the gate structure 440 can be removed later.
The gate openings are used to provide a spatial location for forming the device gate structure 470.
The device gate structure 470 is used to control the opening and closing of the conduction channel during device operation.
In this embodiment, the device Gate structure 470 is a Metal Gate (Gate) structure, and the device Gate structure 470 is formed by a process of forming a Metal Gate (high k last Metal Gate last) by forming a high-k Gate dielectric layer.
In this embodiment, the device gate structure 470 includes a work function layer (not shown) and a gate electrode layer (not shown) on the work function layer.
The work function layer is used for adjusting the work function of the metal gate structure, so that the effect of adjusting the threshold voltage of the transistor is achieved. When the NMOS transistor is formed, the work function layer is an N-type work function layer, and the material of the work function layer comprises one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when the PMOS transistor is formed, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride, and tantalum carbide.
The electrode material layer is used as an electrode for leading out the electricity of the metal gate structure, so that the metal gate structure is electrically connected with an external circuit. In this embodiment, the material of the electrode material layer is W. In other embodiments, the material of the electrode material layer may also be Al, cu, ag, au, pt, ni or Ti, etc.
In this embodiment, a gate dielectric layer 70 is further formed between the device gate structure 470 and the top fin 20, and the gate dielectric layer 70 is used to electrically isolate the device gate structure 470 from the top fin 20.
In this embodiment, the gate dielectric layer 70 comprises a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material; the high-k dielectric material refers to a dielectric material with a relative dielectric constant larger than that of silicon oxide. As an example, the material of the high-k gate dielectric layer is hafnium oxide (HfO 2 )。
In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer on the gate oxide layer. Wherein, the material of the gate oxide layer comprises one or two of silicon oxide and silicon oxynitride. In still other embodiments, the gate dielectric layer may also include only a gate oxide layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (24)

1. A semiconductor structure, comprising:
a substrate;
The fin structures are separated on the substrate and comprise bottom fin parts and top fin parts which are suspended on the bottom fin parts, and gaps are reserved between the bottom fin parts and the top fin parts;
a dielectric layer sealing the gap;
an isolation layer on the substrate and surrounding the bottom fin;
a device gate structure located on the isolation layer and crossing the top fin;
and the source-drain doped region is positioned in the top fin parts at two sides of the grid electrode structure.
2. The semiconductor structure of claim 1, wherein a distance between a top surface of the bottom fin and a bottom surface of the top fin is 5nm to 15nm in a direction perpendicular to the substrate.
3. The semiconductor structure of claim 1, wherein the dielectric layer fills the gap.
4. The semiconductor structure of claim 1, wherein an isolation layer located between the substrate and the device gate structure is used as a first isolation layer, a top surface of the first isolation layer being in contact with a bottom surface of the device gate structure; the isolation layer is located on the substrate at the side part of the device grid structure and serves as a second isolation layer, the top surface of the second isolation layer is lower than the top surface of the first isolation layer, and the second isolation layer exposes the dielectric layer.
5. The semiconductor structure of claim 1, wherein a width of the top fin is a first dimension along a direction perpendicular to an extension of the fin structure; the height of the top fin part is a second size along the direction perpendicular to the substrate; the first dimension is smaller than the second dimension.
6. The semiconductor structure of claim 5, wherein a ratio of the first dimension to the second dimension ranges from 1:2 to 1:5.
7. The semiconductor structure of claim 1, wherein a top width of the top fin is less than a bottom width of the top fin in a direction perpendicular to an extension of the fin structure.
8. The semiconductor structure of claim 1, in which a bottom surface of the source-drain doped region is higher than a bottom surface of the top fin.
9. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: the side wall is positioned on the side wall of the device grid structure; the side wall comprises a plurality of sub side walls which are sequentially stacked on the side wall of the grid structure of the device; the material of at least one sub-side wall is the same as that of the dielectric layer.
10. The semiconductor structure of claim 1, wherein the material of the substrate comprises one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium arsenide;
the material of the bottom fin portion comprises one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium arsenide;
the material of the top fin portion comprises one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide and indium gallium arsenide;
the material of the isolation layer comprises one or more of silicon oxide, silicon nitride and silicon oxynitride;
the material of the dielectric layer comprises one or more of silicon oxide, silicon nitride and silicon oxynitride.
11. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a plurality of fin structures which are separated on the substrate, and the fin structures comprise bottom fin parts, sacrificial layers positioned on the bottom fin parts and top fin parts positioned on the sacrificial layers;
forming an isolation layer surrounding the bottom fin portion and the sacrificial layer on the substrate, wherein the isolation layer exposes the top fin portion;
forming a gate structure on the isolation layer across the top fin;
Removing the isolation layer with partial thickness of the exposed gate structure and the top fin portion after forming the gate structure, and exposing the side wall of the sacrificial layer;
removing the sacrificial layer, and forming a gap between the bottom fin portion and the top fin portion;
forming a dielectric layer sealing the gap;
after forming the dielectric layer, source-drain doped regions are formed in the top fin portions at two sides of the gate structure.
12. The method of forming a semiconductor structure of claim 11, wherein in the step of providing a substrate, the material of the sacrificial layer comprises one or more of silicon, germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.
13. The method of forming a semiconductor structure of claim 11, wherein the step of providing a substrate comprises: forming a first semiconductor layer, a sacrificial material layer and a second semiconductor layer stacked in this order;
patterning the second semiconductor layer, the sacrificial material layer and a portion of the thickness of the first semiconductor layer, the remaining second semiconductor layer being used as the top fin, the remaining sacrificial material layer being used as the sacrificial layer, and forming a substrate and the bottom fin protruding from the substrate in the remaining first semiconductor layer.
14. The method of forming a semiconductor structure of claim 13, wherein the process of forming the layer of sacrificial material comprises an epitaxial process.
15. The method of forming a semiconductor structure of claim 11, further comprising: after the grid electrode structure is formed, forming a side wall on the side wall of the grid electrode structure before removing the grid electrode structure and the isolation layer with the partial thickness of the exposed top fin part, wherein the side wall is also formed on the side wall of the top fin part;
the step of removing the gate structure and the isolation layer with the exposed part of the top fin portion comprises the following steps: removing the isolation layers with partial thickness, which are exposed out of the grid structure, the top fin part and the side wall; and removing the isolation layer at the bottom of the side wall of the top fin part to expose the side wall of the sacrificial layer.
16. The method of claim 15, wherein an anisotropic etching process is used to remove portions of the gate structure, the top fin, and the sidewall exposed spacer; and removing the isolation layer at the bottom of the side wall of the top fin part by adopting an isotropic etching process.
17. The method of forming a semiconductor structure of claim 11, further comprising: after the grid structure is formed, forming a first side wall on the side wall of the grid structure before removing the grid structure and the isolation layer with the partial thickness of the exposed top fin part, wherein the first side wall is also formed on the side wall of the top fin part;
the step of removing the gate structure and the isolation layer with the exposed part of the top fin portion comprises the following steps: and removing the grid structure, the top fin part and the isolation layer with partial thickness exposed from the first side wall.
18. The method of claim 17, wherein in the step of forming a dielectric layer, the dielectric layer is further formed on a sidewall of the first sidewall, the dielectric layer formed on the sidewall of the first sidewall is used as a second sidewall, and the second sidewall and the first sidewall are used to form a gate sidewall;
or,
after removing the sacrificial layer and before forming the dielectric layer, the method of forming the semiconductor structure further comprises: removing the first side wall;
in the step of forming the dielectric layer, the dielectric layer is further formed on the side wall of the gate structure, and the dielectric layer formed on the side wall of the gate structure is used as the third side wall.
19. The method of claim 17, wherein an anisotropic etching process is used to remove portions of the gate structure, the top fin, and the exposed first sidewall spacer.
20. The method of forming a semiconductor structure of claim 11, wherein the process of removing the sacrificial layer comprises an isotropic etching process.
21. The method of forming a semiconductor structure of claim 11, wherein in the step of forming the dielectric layer, the dielectric layer fills the gap.
22. The method of claim 11, wherein in the step of forming a dielectric layer, the dielectric layer is further formed on top and sidewalls of the top fin; after forming the dielectric layer and before forming the source-drain doped region, the method for forming the semiconductor structure further comprises the following steps: and removing the dielectric layer positioned at the top of the top fin part to expose the top fin part.
23. The method of claim 11, wherein in forming the source-drain doped region, a bottom surface of the source-drain doped region is higher than a bottom surface of the top fin.
24. The method of forming a semiconductor structure of claim 11, wherein the gate structure is a dummy gate structure;
after forming the source-drain doped region, the method for forming the semiconductor structure further comprises the following steps: forming an interlayer dielectric layer on the isolation layer at the side part of the grid structure; removing the pseudo gate structure and forming a gate opening in the interlayer dielectric layer; and forming a device gate structure in the gate opening.
CN202210766098.6A 2022-07-01 2022-07-01 Semiconductor structure and forming method thereof Pending CN117374073A (en)

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