CN115763371A

CN115763371A - Semiconductor structure and forming method thereof

Info

Publication number: CN115763371A
Application number: CN202111027312.8A
Authority: CN
Inventors: 郑二虎; 张海洋
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2021-09-02
Filing date: 2021-09-02
Publication date: 2023-03-07

Abstract

A semiconductor structure and a method of forming the same, the method comprising: providing a substrate comprising a device unit area, wherein the device unit area comprises a plurality of adjacent sub-device areas, one or more stacked channel lamination layers are respectively formed on the substrate of each sub-device area, each channel lamination layer comprises a first sacrificial layer and a first channel layer positioned on the first sacrificial layer, and a separation wall is formed on the substrate between the adjacent sub-device areas; removing the first sacrificial layer through the gate opening to form a through groove; and forming second channel layers on the top surface, the bottom surface and the side surface of the first channel layer exposed from the gate opening and the through groove, wherein an included angle between the end surface of the second channel layer and the side wall of the isolation wall exposed from the first channel layer is an acute angle at the junction of the top surface of the first channel layer and the side wall of the isolation wall and at the junction of the bottom surface of the first channel layer and the side wall of the isolation wall.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background

With the rapid development of semiconductor manufacturing technology, semiconductor devices are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration of semiconductor devices increase, the channel length of transistors has to be continuously shortened in order to accommodate the reduction of process nodes.

In order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar transistors to three-dimensional transistors with higher power efficiency, such as Gate-all-around (GAA) transistors and forkgate (forkheet) transistors.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of the semiconductor structure.

To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate including a discrete device cell region including a plurality of sub-device regions adjacent in a first direction; the channel structure layers extend along a second direction, are respectively positioned on the substrate of the sub-device region and are arranged at intervals with the substrate, the second direction is vertical to the first direction, and the channel structure layers comprise one or more first channel layers arranged at intervals; the isolation wall is positioned on the substrate between the adjacent sub-device regions and extends along the second direction, the isolation wall covers the side walls of the channel structure layer on two sides, and the top of the isolation wall is higher than that of the channel structure layer; the second channel layer is positioned on the top surface, the bottom surface and the side surfaces of the first channel layer exposed by the isolation wall, the intersection between the top surface of the first channel layer and the side wall of the isolation wall and the intersection between the bottom surface of the first channel layer and the side wall of the isolation wall form an acute angle, and the second channel layer and the first channel layer are used for forming a channel layer; the gate structure is positioned on the substrate of the sub-device region and transversely crosses the channel structure layer along the first direction, the gate structure covers the top and the side wall of the channel structure layer of the sub-device region, and the gate structure comprises a gate dielectric layer which surrounds a second channel layer covering the device region and a gate electrode layer which covers the gate dielectric layer; and the source-drain doped layers are positioned on the substrate at two sides of the gate structure of the sub-device region and cover the end surface of the channel structure layer below the gate structure, and the source-drain doped layers of the adjacent sub-device regions are isolated by the isolation wall.

Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate comprising discrete device unit regions, wherein the device unit regions comprise a plurality of sub-device regions adjacent to each other in a first direction, laminated structures extending along a second direction are respectively formed on the substrate of the plurality of sub-device regions, the second direction is perpendicular to the first direction, the laminated structures comprise one or more stacked channel laminated layers, each channel laminated layer comprises a first sacrificial layer and a first channel layer located on the first sacrificial layer, and isolation walls extending along the second direction are formed on the substrate between the adjacent sub-device regions and cover the side walls of the laminated structures on two sides; forming a dielectric layer covering part of the laminated structure on the substrate, wherein a gate opening penetrating through the dielectric layer and extending along the first direction is formed in the dielectric layer, and the gate opening crosses the laminated structure and the isolation wall of the device unit region and exposes part of the top and part of the side wall of the laminated structure; removing the first sacrificial layer through the grid opening to form a through groove communicated with the grid opening; after the through groove is formed, forming a second channel layer on the top surface, the bottom surface and the side surface of the first channel layer exposed from the grid opening and the through groove, wherein an included angle between the end surface of the second channel layer and the side wall of the isolation wall exposed from the first channel layer is an acute angle at the junction of the top surface of the first channel layer and the side wall of the isolation wall and at the junction of the bottom surface of the first channel layer and the side wall of the isolation wall, and the second channel layer and the first channel layer are used for forming a channel layer; and forming a gate structure in the gate opening and the through groove, wherein the gate structure comprises a gate dielectric layer surrounding and covering the second channel layer and a gate electrode layer covering the gate dielectric layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

in the semiconductor structure provided by the embodiment of the present invention, the top surface, the bottom surface and the side surface of the first channel layer exposed by the partition wall are formed with the second channel layer, and an included angle between an end surface of the second channel layer and the partition wall sidewall exposed by the first channel layer is an acute angle at a boundary between the top surface of the first channel layer and the partition wall sidewall, and the second channel layer and the first channel layer are used to form the channel layer.

In the method for forming a semiconductor structure according to an embodiment of the present invention, after the first sacrificial layer is removed through the gate opening, the second channel layer is formed on the top surface, the bottom surface, and the side surface of the first channel layer exposed from the gate opening and the through groove, and the included angle between the end surface of the second channel layer and the exposed sidewall of the isolation wall of the first channel layer is an acute angle at the boundary between the top surface of the first channel layer and the sidewall of the isolation wall, as compared with a scheme in which the second channel layer is not formed.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

FIGS. 2-3 are schematic structural diagrams of a semiconductor structure according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of another embodiment of a semiconductor structure of the present invention;

FIGS. 5-14 are schematic structural diagrams corresponding to steps of a method of forming a semiconductor structure according to an embodiment of the present invention;

fig. 15 to 16 are schematic structural diagrams corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

At present, the performance of the semiconductor structure still needs to be improved. The reasons for the performance of a semiconductor structure to be improved are now analyzed in conjunction with the structure.

Fig. 1 is a schematic structural diagram of a semiconductor structure.

The semiconductor structure includes: a base including a discrete device unit region 10A, the device unit region 10A including a plurality of sub-device regions 10d adjacent to each other in a first direction (as shown in an X direction in fig. 1), the base including a substrate (not shown) and a fin 10 protruding from the substrate; channel structure layers 20 extending along a second direction (shown as a Y direction in fig. 1) and respectively located on the fins 10 of the sub-device regions 10d and spaced apart from the fins 10, wherein the second direction is perpendicular to the first direction, and the channel structure layers 20 include one or more channel layers 25 spaced apart from each other; the isolation structure 30 is located on the substrate on the side of the fin portion 10, and the isolation structure 30 covers the sidewall of the fin portion 10 and exposes the channel structure layer 20; a partition wall 50 located on the substrate between the adjacent sub-device regions 10d and extending along the second direction, wherein the partition wall 50 covers sidewalls of the channel structure layer 20 at two sides, and a top of the partition wall 50 is higher than a top of the channel structure layer 20; and the gate structure 40 is positioned on the isolation structure 30, and the gate structure 40 crosses the channel structure layer 20 and covers part of the top, part of the side wall and part of the bottom of the channel structure layer 20 in a surrounding manner.

The isolation wall 50 is located on the substrate between the adjacent sub-device regions 10d, and the isolation wall 50 covers the sidewalls of the channel structure layer 20 on both sides, so that the gate structure 40 is difficult to completely cover each surface of the channel layer 25, that is, under the shielding of the isolation wall 50, the gate structure 40 only covers the top surface, the bottom surface, and the sidewall facing away from the isolation wall 50 of the channel layer 25, and the sidewall where the channel layer 25 and the isolation wall 50 are in contact with each other is difficult to cover by the gate structure 40, so that the gate structure 40 has poor control capability on the channel at the position close to the sidewall of the isolation wall 50, and further the device leakage current is large, and accordingly the performance of the semiconductor structure is poor.

In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including a second channel layer located on a top surface, a bottom surface, and a side surface of a first channel layer exposed by a partition wall, where an included angle between an end surface of the second channel layer and a sidewall of the partition wall exposed by the first channel layer is an acute angle, and the second channel layer and the first channel layer are used to form a channel layer at a boundary between the top surface of the first channel layer and the sidewall of the partition wall and a boundary between the bottom surface of the first channel layer and the sidewall of the partition wall; compared with the scheme without the second channel layer, in the embodiment of the invention, the channel layer is retracted inwards at the junction of the top surface of the channel layer and the side wall of the isolation wall and at the junction of the bottom surface of the channel layer and the side wall of the isolation wall, so that on one hand, the channel width at the position close to the isolation wall is favorably reduced, and on the other hand, the grid structure can also cover the end surface, facing the isolation wall, of the second channel layer, the contact surface area of the grid structure and the channel layer at the position close to the isolation wall is increased, and therefore, the wrapping capacity of the grid structure on the channel layer is improved.

In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

Fig. 2 to 3 are schematic structural diagrams of a semiconductor structure according to an embodiment of the invention. Fig. 2 is a plan view, fig. 3 (a) is a cross-sectional view of fig. 2 taken along the direction AA1, and fig. 3 (b) is a cross-sectional view of fig. 2 taken along the direction BB 1.

The semiconductor structure includes: a substrate (not labeled) including a discrete device cell region 300A, the device cell region 300A including a plurality of sub-device regions 300A adjacent in a first direction (as shown in the Y direction in fig. 2); a plurality of channel structure layers 330 extending in a second direction (as shown in the X direction in fig. 2) on the substrate of the sub-device region 300a and spaced apart from the substrate, respectively, the second direction being perpendicular to the first direction, the channel structure layers 330 including one or more first channel layers 332 spaced apart from each other; a partition wall 370 located on the substrate between the adjacent sub-device regions 300a and extending along the second direction, wherein the partition wall 370 covers sidewalls of the channel structure layer 330 on two sides, and a top of the partition wall 370 is higher than a top of the channel structure layer 330; a second channel layer 333 positioned on the top, bottom and side surfaces of the first channel layer 332 exposed by the partition wall 370, wherein an included angle α (shown in fig. 3) between an end surface of the second channel layer 333 and the sidewall of the partition wall 370 exposed by the first channel layer 332 is an acute angle at a boundary between the top surface of the first channel layer 332 and the sidewall of the partition wall 370 and at a boundary between the bottom surface of the first channel layer 332 and the sidewall of the partition wall 370, and the second channel layer 333 and the first channel layer 332 are configured to form a channel layer 335; a gate structure 400 located on the substrate of the sub-device region 300a and crossing the channel structure layer 330 along the first direction, wherein the gate structure 400 covers the top and the sidewall of the channel structure layer 330 of the sub-device region 300a, and the gate structure includes a gate dielectric layer 410 surrounding the second channel layer 333 covering the device region 300a and a gate electrode layer 420 covering the gate dielectric layer 410; the source-drain doping layers 350 are located on the substrates on the two sides of the gate structure 400 of the sub-device region 300a, cover the end surfaces of the channel structure layer 330 below the gate structure 400, and the source-drain doping layers 350 adjacent to the sub-device region 300a are isolated by the isolation wall 370.

The substrate is used for providing a process platform for the formation of a semiconductor structure.

In this embodiment, the semiconductor structure is a fork gate (forkheet) transistor.

Thus, the substrate includes a discrete device cell region 300A, and the device cell region 300A includes a plurality of sub-device regions 300A adjacent in the first direction. In the fork gate transistor, the adjacent sub-device regions 300a are isolated by a isolation wall (dielectric wall).

In the present embodiment, in the device cell region 300A, the device cell region 300A includes two sub-device regions 300A. Specifically, the sub-device region 300a includes a first sub-device region 300n for forming a first type transistor and a second sub-device region 300p for forming a second type transistor, the first type transistor and the second type transistor having different channel conductivity types.

As an example, the first sub-device region 300n is used to form an NMOS transistor and the second sub-device region 300p is used to form a PMOS transistor. In other embodiments, the first sub-device region is used to form PMOS transistors and the second sub-device region is used to form NMOS transistors. In other embodiments, the device unit region may further include other numbers of sub-device regions, and the types of transistors used for forming the respective sub-device regions may be the same or different.

In this embodiment, the base is a three-dimensional structure, and includes a substrate 300 and a fin 310 protruding from the substrate 300 of the device cell area 300A. In other embodiments, the base may also be a planar substrate.

In this embodiment, the substrate 300 is made of silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

In this embodiment, the fin 310 and the substrate 300 are made of the same material, and the fin 310 is made of silicon.

Correspondingly, in this embodiment, the channel structure layer 330 is respectively located on the fin 310 of the sub-device region 300a and spaced apart from the fin 310, and the extending directions of the channel structure layer 330 and the fin 310 are the same.

The channel structure layer 330 includes one or more first channel layers 332 disposed at intervals in a direction perpendicular to the surface of the substrate 300, that is, in the channel structure layer 330, a stacking direction of the first channel layers 332 is perpendicular to the surface of the substrate 300.

The first channel layer 332 is intended to be part of a channel layer 335, thereby providing a conductive channel for a transistor.

The material of the first channel layer 332 includes silicon, silicon germanium, or a group iii-v semiconductor material. The material of the first channel layer 332 depends on the channel conductivity type and performance requirements of the transistor in the sub-device region 300a.

As an example, the material of the first channel layer 332 of the first sub-device region 300n and the second sub-device region 300p is the same, and the material of the first channel layer 332 is silicon. In other embodiments, the first channel layer material of the first and second sub-device regions may also be different.

In this embodiment, each channel structure layer 330 includes two stacked first channel layers 332 as an example. In other embodiments, the number of first channel layers in each channel structure layer may also be other.

In this embodiment, the semiconductor structure further includes: the isolation structure 301 is located on the substrate 300 at the side of the fin 310, and the isolation structure 301 covers the sidewall of the fin 310 and exposes the channel structure layer 330.

The isolation structure 301 is used to isolate adjacent fins 310. The isolation structure 301 is also used to isolate the gate structure 400 from the substrate 300.

The isolation structure 301 is made of an insulating material. As an example, the material of the isolation structure 301 is silicon oxide. The silicon oxide has better insulating property, and the stress generated by the silicon oxide is smaller, thereby being beneficial to improving the process reliability. In other embodiments, the material of the isolation structure may also be an appropriate insulating material such as silicon oxynitride.

The isolation wall 370 is located between the channel structure layers 330 of the adjacent sub-device regions 300a, the isolation wall 370 covers the sidewalls of the channel structure layers 330 on both sides, and the isolation wall 370 is used to isolate the channel structure layers 330 of the adjacent sub-device regions 300a, so as to isolate the transistors of the adjacent sub-device regions 300a, thereby achieving a smaller interval between the transistors in the adjacent sub-device regions 300a.

In this embodiment, the substrate includes a first sub-device region 300n and a second sub-device region 300p that are adjacent to each other, and thus, the isolation wall 370 is located on the substrate between the first sub-device region 300n and the second sub-device region 300 p. Specifically, the isolation wall 370 is located between the channel structure layer 330 of the first sub-device region 300n and the channel structure layer 330 of the second sub-device region 300 p.

The material of the isolation wall 370 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride and silicon carbonitride. In this embodiment, the isolation wall 370 is made of silicon nitride.

In this embodiment, the top of the isolation wall 370 is higher than the top of the channel structure layer 330, so as to improve the isolation effect of the isolation wall 370. In other embodiments, the top surface of the isolation wall can be flush with the top surface of the channel structure layer.

As an example, the bottom of the isolation wall 370 extends into the fin portion 310, that is, the isolation wall 370 is embedded in the fin portion 310, and the bottom of the isolation wall 370 is lower than the top of the fin portion 310, so as to further improve the isolation effect of the isolation wall 370.

The first channel layer 332 and the second channel layer 333 on the surface of the first channel layer 332 constitute a channel layer 335, thereby collectively providing a conductive channel of a transistor. That is, each of the channel layers 335 includes one first channel layer 332, and a second channel layer 333 covering a top surface, a bottom surface, and side surfaces of the first channel layer 332.

The second channel layer 333 is located on the top surface, the bottom surface and the side surface of the first channel layer 332 exposed by the isolation wall 370, an included angle α between the end surface of the second channel layer 333 and the side wall of the isolation wall 370 exposed by the first channel layer 332 is acute at the boundary between the top surface of the first channel layer 332 and the side wall of the isolation wall 370, that is, at the boundary between the top surface of the channel layer 335 and the side wall of the isolation wall 370, and at the boundary between the bottom surface of the channel layer 335 and the side wall of the isolation wall 370, the channel layer 335 is retracted inward, which is advantageous for reducing the channel width near the location of the isolation wall on the one hand, and for enabling the gate structure 400 to cover the end surface of the second channel layer 333 facing the isolation wall 370 on the other hand, so that the contact surface area of the gate structure 400 and the channel layer 335 near the location of the isolation wall 370 is increased, thereby improving the cladding capability of the gate structure 400 to the channel layer 335, and improving the performance of the semiconductor structure.

In which the channel layer 335 is easily retracted inward with reduced process risk (for example, avoiding the introduction of an etching process) by disposing the second channel layer 333 on the surface of the first channel layer 332.

Specifically, the second channel layer 333 is epitaxially grown on the surface of the first channel layer 332. Wherein the growth rate of the epitaxial growth process is generally greater in the <111> crystal plane than in other crystal planes (e.g., <100> crystal plane), and thus, at the corners of the end and top surfaces of the first channel layer 332, the corners of the end and bottom surfaces of the first channel layer 332, the junctions of the top surface of the first channel layer 132 and the sidewalls of the isolation wall 370, and the junctions of the bottom surface of the first channel layer 332 and the sidewalls of the isolation wall 170, the surface of the second channel layer 333 is closer to the <111> crystal plane, that is, the second channel layer 333 has a slope such that the angle α between the end surface of the second channel layer 333 and the sidewalls of the isolation wall 370 is an acute angle at the junctions of the top surface of the first channel layer 332 and the sidewalls of the first channel layer 332 and the junctions of the bottom surface of the sidewalls of the isolation wall 370 exposed from the first channel layer 332.

An included angle α between the end surface of the second channel layer 333 and the exposed sidewall of the isolation wall 370 of the first channel layer 332 is not too small or too large. If the included angle α is too small, the filling capability of the gate structure 400 between the end surface of the second channel layer 333 and the sidewall of the isolation wall 370 is easily deteriorated, so that the cladding capability of the gate structure 400 on the channel layer 335 at a position close to the isolation wall 370 is poor; if the included angle α is too large, it is easy to cause that the end surface of the second channel layer 333 is difficult to obtain a significant slope at a position close to the isolation wall 370, so that the inward retracting effect of the channel layer 335 is not good, and the control capability of the gate structure 400 on the channel at a position close to the sidewall of the isolation wall 370 is not good. For this reason, in the present embodiment, an angle α between the end surface of the second channel layer 333 and the exposed sidewall of the isolation wall 370 of the first channel layer 332 is 35 degrees to 75 degrees. For example, an included angle α between an end surface of the second channel layer 333 and a sidewall of the isolation wall 370 exposed from the first channel layer 332 is 45 degrees or 55 degrees.

It should be noted that in the actual process, appropriate epitaxial process parameters may be adjusted according to the material characteristics of the first channel layer 332, so as to obtain the included angle α meeting the requirement.

The second channel layer 333 and the first channel layer 332 together constitute a channel layer 335, and thus, the material of the second channel layer 333 includes silicon, silicon germanium, or a iii-v semiconductor material.

Specifically, the material of the second channel layer 333 depends on the type of transistor and performance requirements. For example, if the first sub-device region 300n is used to form an NMOS transistor and the second sub-device region 300p is used to form a PMOS transistor, the material of the second channel layer 333 located in the first sub-device region 300n is silicon, and the material of the second channel layer 333 located in the second sub-device region 300p is silicon germanium.

It should be noted that, since the second channel layer 333 is located on the surface of the first channel layer 332 exposed by the isolation wall 370, the thickness of the channel layer 335 is equal to the sum of the thickness of the first channel layer 332 and twice the thickness of the second channel layer 333 in the direction perpendicular to the substrate surface, and the width of the channel layer 335 is equal to the width of the first channel layer 332 and the thickness of the second channel layer 333 in the direction perpendicular to the sidewall of the isolation wall 370.

The thickness of the second channel layer 333 is not necessarily too small, nor too large.

If the thickness of the second channel layer 333 is too small, it is easy to cause that a sufficiently obvious slope is difficult to obtain at the boundary between the top surface of the first channel layer 332 and the sidewall of the isolation wall 370 and at the boundary between the bottom surface of the first channel layer 332 and the sidewall of the isolation wall 370, so that the end surface of the second channel layer 333 facing the end surface of the isolation wall 370 is not covered well by the gate structure 400, and thus the controllability of the gate structure 400 on the channel at the position close to the sidewall of the isolation wall 370 is not improved, and the smaller the thickness of the second channel layer 333, the smaller the formation process window of the second channel layer 333 is, which accordingly tends to cause the poor formation quality of the second channel layer 333, and both of the above aspects tend to cause the poor performance of the semiconductor structure.

If the thickness of the second channel layer 333 is too large, the distance between adjacent channel layers 335 is easily too small along the direction perpendicular to the substrate surface, so that the window of the forming process of the gate electrode layer 420 in the gate structure 400 is easily reduced, or, when the thickness of the channel layer 335 meets the process requirement, the thickness of the first channel layer 332 is correspondingly too small, which not only easily reduces the mechanical performance of the first channel layer 332 and increases the probability of deformation of the first channel layer 332, but also affects the height of the source-drain doping layer 350, thereby affecting the volume of the source-drain doping layer 350 and correspondingly affecting the performance of the source-drain doping layer 350.

For this reason, in the present embodiment, the second channel layer 333 has a thickness of

To

For example, the second channel layer 333 has a thickness of

Or

It is understood that, according to actual process requirements, the thickness of the first channel layer 332 may be appropriately reduced compared to a scheme in which a second channel layer is not formed, so that the thickness and the width of the channel layer 335 meet the process requirements.

The gate structure 400 is used to control the conduction channel of the corresponding transistor to be turned on or off.

Specifically, the gate structure 400 includes a gate dielectric layer 410 and a gate electrode layer 420 covering the gate dielectric layer 410.

The gate dielectric layer 410 is used to isolate the gate electrode layer 420 from the conductive channel.

The material of the gate dielectric layer 410 comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La ₂ O ₃ One or more of (a).

In this embodiment, the gate structure 400 is a metal gate structure. Thus, the gate dielectric layer 410 comprises a high-k gate dielectric layer.

The high-k gate dielectric layer is made of a high-k dielectric material, wherein the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide. In particular, the material of the high-k gate dielectric layer may be selected from HfO ₂ 、ZrO ₂ HfSiO, hfSiON, hfTaO, hfTiO, hfZrO or Al ₂ O ₃ And so on. As an example, the material of the high-k gate dielectric layer is HfO ₂ 。

It is noted that the gate dielectric layer 410 may further include a gate oxide layer between the high-k gate dielectric layer and the second channel layer 333. As an example, the material of the gate oxide layer may be silicon oxide.

The gate electrode layer 420 is used to electrically conduct the gate structure 400.

The material of the gate electrode layer 420 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC.

In this embodiment, the gate electrode layer 420 includes a work function layer 421 and an electrode layer 422 covering the work function layer 421. The work function layer 421 is used to adjust the threshold voltage of the corresponding transistor.

In other embodiments, the gate electrode layer may include only the work function layer

As an example, the first sub-device region 300n is used to form an NMOS transistor, and the second sub-device region 300p is used to form a PMOS transistor, so that the work function layer 421 located in the first sub-device region 300n is different from the work function layer 421 located in the second sub-device region 300p in material, the work function layer 421 located in the first sub-device region 300n is used to adjust the threshold voltage of the NMOS transistor, and the work function layer 421 located in the second sub-device region 300p is used to adjust the threshold voltage of the PMOS transistor.

It should be noted that the isolation wall 370 is disposed on the substrate between the adjacent sub-device regions 300a, which is beneficial to reduce the probability of the mutual influence between the work function layers 421 of the adjacent sub-device regions 300a (for example, reduce the probability of the mutual diffusion of ions in the work function layers 421), thereby being beneficial to further improving the performance of the semiconductor structure.

It should be noted that the top of the isolation wall 370 is higher than the top of the channel structure layer 330, and therefore, the gate structure 400 also covers the sidewall of the isolation wall 370 higher than the top surface of the channel structure layer 330.

As an example, the top of the gate structures 400 and the top of the isolation wall 370 are flush, so that the gate structures 400 of the adjacent sub-device regions 300a are isolated from each other by the isolation wall 370, thereby further reducing the probability of mutual influence between the gate structures 400 of the adjacent sub-device regions 300a.

In other embodiments, the electrode layer may be shared by the sub-device regions in the same device unit region.

The source-drain doped layer 350 is used as a source region or a drain region of the transistor.

Specifically, the doping type of the source-drain doping layer 350 is the same as the channel conductivity type of the corresponding transistor. When the transistor is a PMOS transistor, the material of the source-drain doping layer 350 includes silicon germanium doped with P-type ions or silicon doped with P-type ions, and the P-type ions include B, ga or In. When the transistor is an NMOS transistor, the material of the source-drain doping layer 350 includes silicon doped with N-type ions or silicon carbide doped with N-type ions, and the N-type ions include P, as or Sb.

In this embodiment, in the first direction, the source and drain doping layers 350 adjacent to the sub-device region 300a are isolated by the isolation wall 370, so that the probability of bridging between the source and drain doping layers 350 adjacent to the sub-device region 300a is reduced.

In this embodiment, the semiconductor structure further includes: and a gate sidewall spacer 405 covering a sidewall of the gate structure 400. The gate sidewall spacers 405 are used to protect the sidewalls of the gate structure 400 and also to define the formation position of the source-drain doping layer 350.

The gate sidewall 405 may have a single-layer structure or a stacked-layer structure, and the material of the gate sidewall 405 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 405 has a single-layer structure, and the gate sidewall 405 is made of silicon nitride.

It should be noted that the gate structure 400 surrounds the second channel layer 333 covering the sub-device region 300a, and therefore, the portions of the gate structure 400 between adjacent channel layers 335 and between the channel layer 335 and the substrate are referred to as a first portion 400a (as shown in fig. 3 (b)), and the remaining portion of the gate structure 400 is referred to as a second portion 400b (as shown in fig. 3 (b)).

In this embodiment, the semiconductor structure further includes: and an inner spacer (inner spacer) 360 between the source-drain doping layer 350 and the first portion 400 a.

The inner sidewall 360 plays a role in isolating the gate structure 400 from the source-drain doping layer 350, and increases the distance between the first portion 400a and the source-drain doping layer 350, thereby facilitating reduction of parasitic capacitance between the gate structure 400 and the source-drain doping layer 350.

The material of the inner sidewall spacers 360 may include one or more of silicon nitride, silicon oxide, silicon oxynitride, a low-k dielectric material (the low-k dielectric material refers to a dielectric material having a relative dielectric constant greater than or equal to 2.6 and less than or equal to 3.9), and an ultra-low-k dielectric material (the ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant less than 2.6). In this embodiment, the inner sidewall spacers 360 are made of silicon nitride.

In this embodiment, the top surface of the source/drain doped layer 350 is higher than the top surface of the channel structure layer 330, and the inner sidewall 360 is further located between the source/drain doped layer 350 and the second portion 400 b.

In order to enable the gate structure 400 to surround the second channel layer 333 covering the device region 300a, first sacrificial layers are formed between adjacent first channel layers 332 and between the first channel layers 332 and the substrate, and a second sacrificial layer is further formed on top of the topmost first channel layer 332, during the formation of the semiconductor structure, the second sacrificial layer can play a role of protecting the top of the first channel layer 332 in the process of removing the space between the first sacrificial layer and the second sacrificial layer. After the first sacrificial layer and the second sacrificial layer with partial widths are etched laterally to form an inner groove, the inner sidewall 360 is formed in the inner groove, so that the inner sidewall 360 is further located between the source-drain doping layer 350 and the second portion 400b due to the existence of the second sacrificial layer.

In other embodiments, the second sacrificial layer may not be formed, and accordingly, the inner sidewall may also be located only between the source/drain doping layer and the first portion.

In this embodiment, the semiconductor structure further includes: the interlayer dielectric layer 302 is located on the substrate at the side of the gate structure 400, and the interlayer dielectric layer 302 covers the source-drain doping layer 350 and also covers the side wall of the gate structure 400. Specifically, the interlayer dielectric layer 302 covers the sidewalls of the gate spacers 405.

The interlayer dielectric layer 302 is used to achieve electrical isolation between adjacent devices.

The interlayer dielectric layer 302 is made of an insulating material. As an example, the material of the interlayer dielectric layer 302 is silicon oxide.

FIG. 4 is a schematic structural diagram of another embodiment of a semiconductor structure according to the present invention. Wherein, fig. 4 (a) is a sectional view along a direction perpendicular to a side wall of the partition wall, and fig. 4 (b) is a sectional view along an extending direction of the partition wall at a side of the partition wall.

The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that: the semiconductor structure further includes: an isolation layer 580 is disposed under the channel structure layer (not labeled) and between the bottom of the gate structure layer (not labeled) and the top of the substrate.

Specifically, the isolation layer 580 is located on top of the fin 510. Accordingly, the isolation wall 570 penetrates the isolation layer 580.

As an example, the isolation structure 501 is located on a substrate (not labeled) at the side of the fin 510 and covers the sidewalls of the fin 510 and the sidewalls of the isolation layer 580. Specifically, the top of the isolation structure 501 is flush with the top of the isolation layer 580.

The isolation layer 580 is used to isolate the gate structure from the substrate, thereby reducing the probability of generating leakage current between the gate structure and the substrate, and facilitating the suppression of the formation of parasitic devices.

Specifically, the second channel layer (not shown) is epitaxially grown on the surface of the first channel layer exposed by the isolation wall (not shown), and since the isolation layer 580 covers the substrate below the channel structure layer, the second channel layer may not be formed on the surface of the isolation layer 580 during the process of epitaxially growing the second channel layer, so that the bottom of the gate structure 500 is in contact with the isolation layer 580.

The material of the isolation layer 580 comprises a dielectric material. In particular, the dielectric material comprises one or more of silicon oxide, silicon oxynitride and silicon nitride. As an example, the material of the isolation layer 580 is silicon oxide.

In this embodiment, the isolation layer 580 is a film structure, and compared with a scheme in which an isolation layer is formed by performing ion implantation on a substrate (that is, a scheme in which an isolation layer is an ion doped layer), this embodiment can avoid a problem that parasitic capacitance is increased due to the ion implantation on the substrate.

In this embodiment, the isolation layer 580 further extends to a position between the bottom of the source-drain doping layer 550 and the top of the substrate, so that the source-drain doping layer 550 is effectively isolated by the isolation layer 580, and the probability of punch-through between the source-drain doping layers 550 is reduced.

In other embodiments, the source-drain doping layer may also be only located between the bottom of the gate structure and the top of the substrate, that is, the source-drain doping layer is in contact with the substrate, so as to improve the growth rate of the source-drain doping layer, improve the growth quality of the source-drain doping layer, and reduce defects generated in the growth process.

Fig. 5 to 14 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.

Referring to fig. 5 and 6 in combination, fig. 5 is a top view, fig. 6 (a) is a cross-sectional view of fig. 5 along the direction AA1, fig. 6 (b) is a cross-sectional view of fig. 5 along the direction BB1, a substrate (not labeled) is provided, the substrate includes a discrete device unit region 100A, the device unit region 100A includes a plurality of sub-device regions 100A adjacent to each other in a first direction (as shown in the direction Y in fig. 5), a stacked structure 120 extending in a second direction (as shown in the direction X in fig. 5) is formed on the substrate of each of the plurality of sub-device regions 100A, the second direction is perpendicular to the first direction, the stacked structure 120 includes one or more stacked channel stacks 130, the channel stack 130 includes a first sacrificial layer 131 and a first channel layer 132 on the first sacrificial layer 131, a separation wall 170 extending in the second direction is formed on the substrate between the adjacent sub-device regions 100A, and the separation wall 170 covers sidewalls of the stacked structure 120 on both sides.

In this embodiment, the substrate is used to provide a process platform for forming a fork gate (forkheet) transistor.

Thus, the substrate includes a discrete device cell region 100A, the device cell region 100A including a plurality of sub device regions 100A adjacent in the first direction. In the fork gate transistor, adjacent sub-device regions 100a are isolated by isolation walls 170.

In the present embodiment, in the device cell region 100A, the device cell region 100A includes two sub device regions 100A. Specifically, the sub-device region 100a includes a first sub-device region 100n for forming a first type transistor and a second sub-device region 100p for forming a second type transistor, the first type transistor and the second type transistor having different channel conductivity types.

As an example, the first sub-device region 100n is used to form an NMOS transistor and the second sub-device region 100p is used to form a PMOS transistor. In other embodiments, the first sub-device region is used to form PMOS transistors and the second sub-device region is used to form NMOS transistors. In other embodiments, the device unit region may further include other numbers of sub-device regions, and the types of transistors used for forming the respective sub-device regions may be the same or different.

In this embodiment, the base is a three-dimensional structure, and includes a substrate 100 and a fin 110 protruding from the substrate 100 in the device unit region 100A. In other embodiments, the base may also be a planar substrate.

In this embodiment, the substrate 100 is made of silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon carbide, gallium arsenide, and indium gallium arsenide, and the substrate may also be a silicon substrate on an insulator or other types of substrates such as a germanium substrate on an insulator.

In this embodiment, the fin 110 and the substrate 100 are made of the same material, and the fin 110 is made of silicon.

Accordingly, in the present embodiment, the stacked structure 120 is separated from the top of the fin 110, and the extending direction of the stacked structure 120 is the same as that of the fin 110.

The stack structure 120 includes one or more stacked channel stacks 130, each channel stack 130 including a first sacrificial layer 131 and a first channel layer 132 on the first sacrificial layer 131. In the same stack structure 120, the stacking direction of the channel stack 130 is perpendicular to the surface of the substrate 100.

The channel stack 130 provides a process foundation for the subsequent formation of the first channel layer 132 disposed at a floating interval.

Specifically, the first sacrificial layer 131 is used to support the first channel layer 132, so that the first channel layer 132 can be spaced and suspended after the first sacrificial layer 131 is subsequently removed, and the first sacrificial layer 131 is also used to occupy space for a gate structure to be subsequently formed.

The first channel layer 132 is intended to be part of a channel layer, thereby providing a conductive channel of a transistor.

Specifically, along the extending direction of the stacked structure 120, the stacked structure 120 includes a channel region (not labeled) whose channel layer is used to provide a conductive channel of a transistor, that is, the channel region is used to define a position where a gate structure is subsequently formed.

The material of the first channel layer 132 includes silicon, silicon germanium, or a iii-v semiconductor material. The material of the first channel layer 132 depends on the channel conductivity type and performance requirements of the transistor.

Correspondingly, according to the material of the first channel layer 132, the first sacrificial layer 131 is selected from a material having an etching selection ratio with respect to the first channel layer 132, and the material of the first sacrificial layer 131 satisfies: the first sacrificial layer 131 and the first channel layer 132 can be alternately formed.

In this embodiment, the materials of the first channel layer 132 of the first sub-device region 100n and the second sub-device region 100p are the same, and the materials of the first sacrificial layer 131 of the first sub-device region 100n and the second sub-device region 100p are also the same.

As an example, the material of the first channel layer 132 is silicon, and the material of the first sacrificial layer 131 is silicon germanium. In the subsequent process of removing the first sacrificial layer 131, the etching selectivity of silicon germanium and silicon is relatively high, and the material of the first sacrificial layer 131 is set to be silicon germanium, so that the influence of the removal process of the first sacrificial layer 131 on the first channel layer 132 can be effectively reduced, and the quality of the first channel layer 132 can be ensured.

In other embodiments, the first sacrificial layer may also be other types of materials depending on the material of the first channel layer in each sub-device region, such as: in the same stacked structure, when the material of the first channel layer is silicon germanium, the material of the first sacrificial layer is silicon.

In other embodiments, the first channel layer material of the first sub-device region and the second sub-device region may also be different, and the first sacrificial layer material of the first sub-device region and the second sacrificial layer material of the second sub-device region may also be different accordingly.

In this embodiment, the stacked structure 120 includes two stacked channel stacks 130 as an example. In other embodiments, the number of channel stacks in each stack structure may be other.

In this embodiment, in the step of providing the substrate, the stack structure 120 further includes a second sacrificial layer 140 located on top of the topmost channel stack 130, and the second sacrificial layer 140 and the first sacrificial layer 131 are made of the same material.

The second sacrificial layer 140 is used to protect the top of the first channel layer 132 during the subsequent process of removing the dummy gate structure, so as to reduce the probability of damage to the first channel layer 132.

Moreover, the second sacrificial layer 140 and the first sacrificial layer 131 are made of the same material, so that the second sacrificial layer 140 and the first sacrificial layer 131 are removed in the same step, thereby simplifying the process steps.

In this embodiment, in the step of providing the base, an isolation structure 101 is further formed on the substrate 100 at the side of the fin 110, and the isolation structure 101 covers the sidewall of the fin 110 and exposes the stacked structure 120.

The isolation structure 101 is used to isolate adjacent fins 110. The isolation structure 101 is also used to isolate a subsequently formed gate structure from the substrate 100.

The isolation structure 101 is made of an insulating material. As an example, the material of the isolation structure 101 is silicon oxide. The silicon oxide has better insulating property, and the stress generated by the silicon oxide is smaller, thereby being beneficial to improving the process reliability. In other embodiments, the material of the isolation structure may also be an appropriate insulating material such as silicon oxynitride.

The isolation wall 170 is located between the stacked structures 120 of the adjacent sub-device regions 100a, the isolation wall 170 covers the sidewalls of the stacked structures 120 on both sides, and the isolation wall 170 is used to isolate the stacked structures 120 of the adjacent sub-device regions 100a in a first direction (as shown in the Y direction in fig. 5), so as to isolate the transistors of the adjacent sub-device regions 100a, thereby achieving a smaller interval between the transistors in the adjacent sub-device regions 100a.

Moreover, in the process of subsequently removing the second sacrificial layer 140 and the first sacrificial layer 131 through the gate opening to form the through trenches, along the first direction, the through trenches of the adjacent sub-device regions 100a are isolated by the isolation wall 170, and the adjacent channel layers are isolated by the isolation wall 170, which is beneficial to preventing process processes when forming corresponding gate structures in different sub-device regions from affecting each other (for example, reducing the probability of ions in the work function layers of the adjacent sub-device regions from diffusing into each other).

In this embodiment, the substrate includes a first sub-device region 100n and a second sub-device region 100p adjacent to each other, and thus the isolation wall 170 is formed on the substrate between the first sub-device region 100n and the second sub-device region 100 p. Specifically, the isolation wall 170 is located between the stacked structure 120 of the first sub-device region 100n and the stacked structure 120 of the second sub-device region 100 p.

The material of the isolation wall 170 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride and silicon carbonitride boride, so as to ensure that the isolation wall 170 can achieve a better isolation effect. In this embodiment, the isolation wall 170 is made of silicon nitride.

In this embodiment, the top of the partition wall 170 is higher than the top of the stacked structure 120, so as to improve the partition effect of the partition wall.

Specifically, before forming the isolation walls 170, a mask layer is formed on the top of the stacked structure 120, the mask layer is used as an etching mask in the process of forming the stacked structure 120, in the process of forming the isolation walls 170, the top of the isolation walls 170 is made to be flush with the mask layer, and after forming the isolation walls 170, the mask layer is removed (for example, in the process of forming the isolation structure 101, the mask layer is removed), so that the top of the isolation walls 170 is higher than the top of the stacked structure 120.

In other embodiments, the top of the isolation wall may also be flush with the top of the stacked structure, and therefore, the top of the isolation wall is higher than the top of the topmost first channel layer, thereby improving the isolation effect of the isolation wall.

As an example, the bottom of the isolation wall 170 extends into the fin 110, so as to further improve the isolation effect of the isolation wall 170.

With continuing reference to fig. 5 and 6, the method of forming further includes: a dummy gate structure 200 is formed on the substrate to cross the stack structure 120 and the partition wall 170 in the first direction (as shown in the Y direction in fig. 5).

The dummy gate structure 200 covers the top and the sidewalls of the stack structure 120 of the channel region (not shown), and the dummy gate structure 200 is used to occupy a space for a subsequently formed gate structure.

In this embodiment, the dummy gate structure 200 spans the stacked structure 120 and the isolation wall 170, that is, the dummy gate structure 200 covers a part of the top of the stacked structure 120 and the isolation wall 170, a part of the sidewall of the isolation wall 170, and a part of the sidewall of the stacked structure 120 facing away from the isolation wall 170.

In this embodiment, the dummy gate structure 200 includes a dummy gate layer. The material of the dummy gate layer comprises polycrystalline silicon, amorphous silicon or amorphous carbon.

In this embodiment, the forming method further includes: and forming a gate sidewall 210 on the sidewall of the dummy gate structure 200.

The gate sidewall 210 is used to protect the sidewall of the dummy gate structure 200 and the sidewall of a subsequently formed gate structure, and is also used to define the formation position of a source-drain doping layer.

The gate sidewall 210 may have a single-layer structure or a stacked-layer structure, and the material of the gate sidewall 210 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the gate sidewall 210 has a single-layer structure, and the gate sidewall 210 is made of silicon nitride.

With continuing reference to fig. 5 and 6, the method of forming further includes: source-drain doping layers 150 are formed in the stacked structure 120 on both sides of the dummy gate structure 200, and the source-drain doping layers 150 adjacent to the sub-device region 100a are isolated by the isolation wall 170.

Specifically, after the gate sidewall spacers 210 are formed, source-drain doping layers 150 are formed in the stacked structures 120 on both sides of the dummy gate structure 200.

The source-drain doping layer 150 is used as a source region or a drain region of the transistor.

Specifically, the doping type of the source-drain doping layer 150 is the same as the channel conductivity type of the corresponding transistor. When the transistor is a PMOS transistor, the material of the source-drain doping layer 150 includes silicon germanium doped with P-type ions or silicon doped with P-type ions, and the P-type ions include B, ga or In. When the transistor is an NMOS transistor, the material of the source-drain doping layer 150 includes silicon doped with N-type ions or silicon carbide doped with N-type ions, and the N-type ions include P, as or Sb.

In this embodiment, in the first direction (as shown in the Y direction in fig. 5), the source and drain doping layers 150 adjacent to the sub-device region 100a are isolated by the isolation wall 170, so that the probability of bridging between the source and drain doping layers 150 adjacent to the sub-device region 100a is reduced.

In this embodiment, before forming the source-drain doping layer 150 in the stacked structure 120 at two sides of the dummy gate structure 200, the method further includes: in the sub-device region 100a, source-drain grooves (not shown) are formed in the stacked structures 120 on both sides of the dummy gate structure 200.

The source-drain grooves are used for providing space positions for forming the source-drain doping layer 150 and also used for providing a process foundation for forming inner grooves in the follow-up process.

In this embodiment, the fin 110 is exposed at the bottom of the source-drain groove.

As an example, in the sub-device region 100a, an anisotropic etching process (e.g., a dry etching process) is used to etch the stacked structures 120 on both sides of the dummy gate structure 200, so as to form the source-drain grooves.

In this embodiment, after the source and drain grooves are formed, the first sacrificial layer 132 exposed by the source and drain grooves is laterally etched along the second direction (as shown in an X direction in fig. 5) to form inner grooves (not shown), where the inner grooves are located between adjacent first channel layers 131 or between the first channel layers 131 and the substrate.

The inner grooves are used for providing space positions for forming the inner side wall subsequently.

In this embodiment, an isotropic etching process (e.g., a wet etching process) is used to perform a lateral etching process on the first sacrificial layer 132 exposed from the source-drain groove. Wherein, the transverse direction means: perpendicular to the direction of the sidewalls of the dummy gate structure 200.

In this embodiment, in the step of performing the lateral etching process on the first sacrificial layer 132 exposed from the source-drain groove, the second sacrificial layer 140 exposed from the source-drain groove is also subjected to the lateral etching process, so that the inner groove is also formed between the gate sidewall 210 and the first channel layer 132.

Correspondingly, after the inner groove is formed, an inner side wall 160 is formed in the inner groove; after forming the inner sidewall 160 in the inner trench, a source-drain doping layer 150 is formed in the source-drain trench.

The inner sidewall 160 plays a role in isolating the gate structure from the source-drain doping layer 150, and increases the distance between the gate structure and the source-drain doping layer 150, thereby facilitating reduction of parasitic capacitance between the gate structure and the source-drain doping layer 150.

The material of the inner sidewall spacers 160 may include one or more of silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material, and ultra-low-k dielectric material. In this embodiment, the inner sidewall spacer 160 is made of silicon nitride.

It should be noted that, in this embodiment, the sub-device region 100a includes a first sub-device region 100n for forming a first type transistor and a second sub-device region 100p for forming a second type transistor, and therefore, after a corresponding source/drain doping layer 150 is formed in any one sub-device region 100a of the first sub-device region 100n and the second sub-device region 100p, a source/drain groove, an inner sidewall 160, and a corresponding source/drain doping layer 150 are sequentially formed in another sub-device region 100a.

After the corresponding source-drain doping layer 150 is formed in any one of the first sub-device region 100n and the second sub-device region 100p in the sub-device region 100a, the sub-device region 100a where the source-drain doping layer 150 is formed is shielded and protected by using a mask layer, so that each process is selectively performed on the other sub-device region 100a.

With continuing reference to fig. 5 and 6 in combination with fig. 7 and 8, fig. 7 is a top view, fig. 8 (a) is a cross-sectional view of fig. 7 along the direction AA1, fig. 8 (b) is a cross-sectional view of fig. 7 along the direction BB1, a dielectric layer 102 covering a part of the stacked structure 120 is formed on the substrate, a gate opening 205 penetrating through the dielectric layer 102 and extending along the first direction is formed in the dielectric layer 102, and the gate opening 205 crosses over the stacked structure 120 and the isolation wall 170 of the device cell area 100A and exposes a part of the top and a part of the sidewall of the stacked structure 120.

The gate opening 205 is used to provide a spatial location for the subsequent formation of a second channel layer. Specifically, the gate opening 205 exposes the stacked structure 120 of the channel region, and the dielectric layer 102 covers the stacked structure of the remaining region, so that a second channel layer is formed only on the surface of the first channel layer exposed by the gate opening 205, and the second channel layer is prevented from being formed at the position of the remaining region.

In this embodiment, the dielectric layer 102 is an interlayer dielectric layer 102, and is used to implement electrical isolation between adjacent devices.

Accordingly, the gate opening 205 is also used to provide a spatial location for the subsequent formation of a gate structure.

For this reason, in this embodiment, the step of forming the dielectric layer 102 on the substrate to cover a portion of the stacked structure 120 includes: after the source-drain doping 150 is formed, a dielectric layer 102 covering the side wall of the dummy gate structure 200 is formed on the substrate, and the dielectric layer 102 exposes the top of the dummy gate structure 200.

The dielectric layer 102 exposes the top of the dummy gate structure 200, and provides for subsequent removal of the dummy gate structure 200.

Specifically, the step of forming the dielectric layer 102 includes: forming a dielectric material layer (not shown) on the substrate at the side of the dummy gate structure 200, wherein the dielectric material layer also covers the top of the dummy gate structure 200; and removing the dielectric material layer higher than the top of the dummy gate structure 200 to form the dielectric layer 102.

The dielectric layer 102 is made of an insulating material. As an example, the material of the dielectric layer 102 is silicon oxide.

Accordingly, referring to fig. 7 and 8, the step of forming the gate opening 205 includes: the dummy gate structure 200 is removed.

Specifically, the process of removing the dummy gate structure 200 includes one or both of dry etching and wet etching.

Referring to fig. 9 and 10, fig. 9 is a top view, fig. 10 (a) is a cross-sectional view of fig. 9 along direction AA1, and fig. 10 (b) is a cross-sectional view of fig. 9 along direction BB1, wherein the first sacrificial layer 131 is removed through the gate opening 205 to form a through trench 206 communicating with the gate opening 205.

The through-trench 206 is in communication with the gate opening 205, and the through-trench 206 is also used to provide a spatial location for the subsequent formation of the gate structure.

Also, the first channel layer 132 of the channel region is exposed through the gate opening 205 and the through-groove 206, so that a subsequent second channel layer can cover respective surfaces of the first channel layer 132 exposed at the gate opening 205 and the through-groove 206.

Specifically, the through-trench 206 is surrounded by the adjacent first channel layer 132 and the sidewall of the isolation wall 170, or the fin 110, the sidewall of the isolation wall 170, and the first channel layer 132 adjacent to the fin 110.

In the present embodiment, in the first direction (as shown in the Y direction in fig. 9), the through trenches 206 of adjacent sub-device regions 100a are isolated by the isolation walls 170.

In this embodiment, the first sacrificial layer 131 is removed by a wet etching process.

Specifically, the material of the first channel layer 132 is silicon, and the material of the first sacrificial layer 131 is silicon germanium, so that the HCl vapor is used to remove the first sacrificial layer 131 exposed from the gate opening 40, and the etching rate of the wet etching process on the first sacrificial layer 131 is much greater than the etching rate on the first channel layer 132 and the fin portion 110.

It should be noted that, after the source-drain doping layer 150 is formed, the first sacrificial layer 131 is removed, and after the first sacrificial layer 131 is removed, along the extending direction of the first channel layer 132, two ends of the first channel layer 132 are connected to the source-drain doping layer 150 and suspended in the gate opening 205, so as to provide a process foundation for the subsequent gate structure to wrap the channel layer in the channel region.

After the first sacrificial layer 131 is removed, the first channel layer 132 exposed by the gate opening 205 is spaced apart in the longitudinal direction, so as to provide a process base for a subsequent second channel layer to be formed on the top surface and the bottom surface of the first channel layer 132. Wherein longitudinal refers to a direction perpendicular to the substrate surface.

It is to be understood that, when the first sacrificial layer material of the first sub-device region and the second sub-device region is different, the sacrificial layer of the first sub-device region and the first sacrificial layer of the second sub-device region may be removed in different steps, respectively.

In this embodiment, since the second sacrificial layer 140 is further formed on the top surface of the topmost first channel layer 132, the second sacrificial layer 140 exposed by the gate opening 205 is further removed in the step of removing the first sacrificial layer 131 through the gate opening 205.

Accordingly, in the present embodiment, after the first sacrificial layer 131 is removed, the top surface of the isolation wall 170 is higher than the top surface of the topmost first channel layer 132.

Referring to fig. 11 and 12, fig. 11 is a top view, fig. 12 (a) is a cross-sectional view of fig. 11 along the direction AA1, fig. 12 (b) is a cross-sectional view of fig. 11 along the direction BB1, after the through trench 206 is formed, a second channel layer 133 is formed on the top surface, the bottom surface and the side surface of the first channel layer 132 exposed by the gate opening 205 and the through trench 206, an included angle α between the end surface of the second channel layer 133 and the side wall of the first channel layer 170 exposed by the first channel layer 132 is an acute angle at the boundary between the top surface of the first channel layer 132 and the side wall of the partition wall 170, and the second channel layer 133 and the first channel layer 132 are used to form the channel layer 135.

The first channel layer 132 and the second channel layer 133 on the surface of the first channel layer 132 constitute a channel layer 135, thereby collectively providing a conductive channel of a transistor. That is, each of the channel layers 135 includes one first channel layer 132, and a second channel layer 133 covering a top surface, a bottom surface, and side surfaces of the first channel layer 132.

The second channel layer 133 is formed on the top surface, the bottom surface and the side surface of the first channel layer 132 exposed by the isolation wall 170, and an included angle α between the end surface of the second channel layer 133 and the side wall of the isolation wall 170 exposed by the first channel layer 132 is an acute angle at the boundary between the top surface of the first channel layer 132 and the side wall of the isolation wall 170 and at the boundary between the bottom surface of the first channel layer 132 and the side wall of the isolation wall 170, compared with a scheme without a second channel layer, in this embodiment, the channel layer 135 is recessed inward at the boundary between the top surface of the channel layer 135 and the side wall of the isolation wall 170 and at the boundary between the bottom surface of the channel layer 135 and the side wall of the isolation wall 170, which is beneficial to reduce the channel width at the position close to the isolation wall 170 on the one hand, and enables a subsequently formed gate structure to cover the end surface of the second channel layer 133 facing the isolation wall 170 on the other hand, thereby improving the cladding capability of the gate structure to the channel layer 135, and improving the performance of the semiconductor structure accordingly.

In addition, in the embodiment, after the dummy gate structure 200 and the first sacrificial layer 131 are removed, the second channel layer 133 is formed before the gate structure is formed, which has little change to the current process and high process compatibility.

In addition, by forming the second channel layer 333 on the surface of the first channel layer 332, the channel layer 335 may be recessed inward, which is beneficial to reduce the process risk (e.g., avoid the introduction of an etching process).

In this embodiment, the second channel layer 133 is formed by an epitaxial growth process.

Wherein, the growth rate of the epitaxial growth process is greater at the <111> crystal plane than at other crystal planes (for example, the <100> crystal plane), and therefore, at the corners of the end surfaces and the top surface of the first channel layer 132, the corners of the end surfaces and the bottom surface of the first channel layer 132, the junctions of the top surface of the first channel layer 132 and the sidewalls of the isolation wall 170, and the junctions of the bottom surface of the first channel layer 132 and the sidewalls of the isolation wall 170, the surface of the second channel layer 333 is closer to the <111> crystal plane, that is, the second channel layer 333 has a slope, so that the included angle α between the end surface of the second channel layer 133 and the exposed sidewalls of the isolation wall 170 of the first channel layer 132 is an acute angle at the junctions of the top surface of the first channel layer 132 and the sidewalls of the isolation wall 170, and the junctions of the bottom surface of the first channel layer 132 and the sidewalls of the isolation wall 170.

An included angle α between the end surface of the second channel layer 133 and the sidewall of the isolation wall 170 exposed by the first channel layer 132 is not too small or too large. If the included angle α is too small, the filling capability of the subsequent gate structure between the end surface of the second channel layer 133 and the sidewall of the isolation wall 170 is easily deteriorated, so that the cladding capability of the gate structure on the channel layer 135 at the position close to the isolation wall 170 is poor; if the included angle α is too large, it is easy to cause that the end surface of the second channel layer 133 is difficult to obtain a significant slope at a position close to the isolation wall 170, so that the inward retracting effect of the channel layer 135 is not good, and the control capability of the gate structure on the channel at a position close to the sidewall of the isolation wall 170 is not good. For this reason, in this embodiment, at the boundary between the top surface of the first channel layer 132 and the sidewall of the isolation wall 170 and the boundary between the bottom surface of the first channel layer 132 and the sidewall of the isolation wall 170, an included angle α between the end surface of the second channel layer 133 and the sidewall of the isolation wall 170 exposed by the first channel layer 132 is 35 degrees to 75 degrees. For example, the included angle α is 45 degrees or 55 degrees.

It should be noted that, in an actual process, appropriate epitaxial process parameters may be adjusted according to the material characteristics of the first channel layer 132, so as to obtain the included angle α meeting the requirement.

It should be noted that the process temperature of the epitaxial growth process is not too low and not too high. If the process temperature of the epitaxial growth process is too low, poor epitaxial quality is easily caused, and the second channel layer 133 cannot be formed on the surface of the first channel layer 132; if the process temperature of the epitaxial growth process is too high, the crystal lattice of the first channel layer 132 is easily damaged, thereby adversely affecting the performance of the first channel layer 132. For this reason, in this embodiment, the process temperature of the epitaxial growth process is 200 ℃ to 500 ℃. For example, the process temperature of the epitaxial growth process is 250 ℃, 300 ℃, 350 ℃ or 400 ℃.

The second channel layer 133 and the first channel layer 132 together constitute a channel layer 135, and thus, the material of the second channel layer 133 includes silicon, silicon germanium, or a iii-v semiconductor material.

Specifically, the material of the second channel layer 133 depends on the type of transistor and performance requirements. For example, if the first sub-device region 100n is used to form an NMOS transistor and the second sub-device region 100p is used to form a PMOS transistor, the second channel layer 133 formed in the first sub-device region 100n is made of silicon, and the second channel layer 133 formed in the second sub-device region 100p is made of silicon germanium.

In other embodiments, the material of the second channel layer formed in each sub-device region may also be the same according to the process requirements.

It is understood that when the materials of the second channel layers of the first sub-device region and the second sub-device region are different, corresponding second channel layers are formed in the first sub-device region and the second sub-device region, respectively, in different steps.

It should be noted that, since the second channel layer 133 is located on the surface of the first channel layer 132 exposed by the isolation wall 170, the thickness of the channel layer 135 is equal to the sum of the thickness of the first channel layer 132 and twice the thickness of the second channel layer 133 along the direction perpendicular to the substrate surface, and the width of the channel layer 135 is equal to the width of the first channel layer 132 and the thickness of the second channel layer 133 along the direction perpendicular to the sidewall of the isolation wall 170.

The thickness of the second channel layer 133 is not necessarily too small, nor too large.

If the thickness of the second channel layer 133 is too small, it is easy to cause that a sufficiently obvious slope is difficult to obtain at the end surface of the second channel layer 133, so that the effect of covering the end surface of the second channel layer 133 facing the partition wall 170 by the gate structure is not good, and therefore it is not good for improving the controllability of the gate structure on the channel at the position close to the sidewall of the partition wall 170, and the smaller the thickness of the second channel layer 133 is, the smaller the forming process window of the second channel layer 133 is, and accordingly it is easy to cause the poor forming quality of the second channel layer 133, and both of the above two aspects are easy to cause the poor performance of the semiconductor structure.

If the thickness of the second channel layer 133 is too large, the distance between adjacent channel layers 135 is too small easily in the direction perpendicular to the substrate surface, so that the window of the formation process of the subsequent gate structure is easily reduced, or, when the thickness of the channel layer 135 meets the process requirement, the formation thickness of the first channel layer 132 is too small correspondingly, which not only easily reduces the mechanical performance of the first channel layer 132 and increases the probability of deformation of the first channel layer 132, but also affects the height of the source-drain doping layer 150, thereby affecting the volume of the source-drain doping layer 150 and correspondingly affecting the performance of the source-drain doping layer 150.

For this reason, in the present embodiment, the second channel layer 133 has a thickness of

To

For example, the second channel layer 133 has a thickness of

Or

It is understood that, according to actual process requirements, the thickness of the first channel layer 132 may be appropriately reduced compared to a scheme in which a second channel layer is not formed, so that the thickness and the width of the channel layer 135 meet the process requirements.

Referring to fig. 13 and 14, fig. 13 is a top view, fig. 14 (a) is a cross-sectional view of fig. 13 along direction AA1, fig. 14 (b) is a cross-sectional view of fig. 13 along direction BB1, and a gate structure 220 is formed in the gate opening 205 and the through trench 206, wherein the gate structure 220 includes a gate dielectric layer 230 surrounding and covering the second channel layer 133, and a gate electrode layer 240 covering the gate dielectric layer 230.

The gate structure 220 is used to control the conduction channel of the corresponding transistor to be turned on or off.

The gate dielectric layer 230 is used to isolate the gate electrode layer 240 from the conductive channel.

The material of the gate dielectric layer 230 comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La ₂ O ₃ One or more of (a).

In this embodiment, the gate structure 220 is a metal gate structure. Accordingly, the gate dielectric layer 230 comprises a high-k gate dielectric layer.

It should be noted that the gate dielectric layer 230 may further include a gate oxide layer between the high-k gate dielectric layer and the second channel layer 133. As an example, the material of the gate oxide layer may be silicon oxide.

The gate electrode layer 240 is used to electrically conduct the gate structure 220.

The material of the gate electrode layer 240 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC.

In this embodiment, the gate electrode layer 240 includes a work function layer 241 and an electrode layer 242 covering the work function layer 241. The work function layer 241 is used for adjusting the threshold voltage of the corresponding transistor.

In other embodiments, the gate electrode layer may only include a work function layer

As an example, the first sub-device region 100n is used to form an NMOS transistor, and the second sub-device region 100p is used to form a PMOS transistor, so that the work function layer 241 in the first sub-device region 100n is made of a different material than the work function layer 241 in the second sub-device region 100 p.

It should be noted that the partition wall 170 is disposed on the substrate between the adjacent sub-device regions 100a, which is beneficial to reduce the probability of the mutual influence between the work function layers 241 of the adjacent sub-device regions 100a (for example, reduce the probability of the mutual diffusion of ions in the work function layers 241), thereby being beneficial to further improving the performance of the semiconductor structure.

It should be further noted that the top of the isolation wall 170 is higher than the top of the topmost first channel layer 132, and therefore, the gate structure 220 also covers the sidewall of the isolation wall 170 higher than the top surface of the topmost channel layer 135.

As an example, the top of the gate structures 220 and the top of the isolation wall 170 are flush, so that the gate structures 220 of the adjacent sub-device regions 100a are isolated from each other by the isolation wall 170, thereby further reducing the probability of mutual influence between the gate structures 220 of the adjacent sub-device regions 100a.

The parts of this embodiment that are the same as the parts of the previous embodiment will not be described herein again. The present embodiment differs from the preceding embodiments in that: as shown in fig. 15, in the step of providing the substrate, an isolation layer 804 is formed between the stacked structure 820 and the substrate, that is, an isolation layer 804 is further formed between the lowest channel stack (not labeled) and the substrate.

Accordingly, before forming the stacked structure 820 on the substrate, further comprising: a third sacrificial layer (not shown) is formed on the substrate.

The third sacrificial layer is used to occupy a spatial location for the isolation layer 804 to be subsequently formed.

Specifically, the third sacrificial layer is formed on top of the fin 810.

In this embodiment, the stacked structure 820 is correspondingly formed on the third sacrificial layer.

It should be noted that the third sacrificial layer and the stacked structure 820 are patterned in the same etching process, that is, after the material layer corresponding to the third sacrificial layer and the material layer corresponding to the stacked structure 820 are sequentially formed, the third sacrificial layer and the stacked structure 820 are sequentially etched from top to bottom to form the stacked structure 820 and the third sacrificial layer located at the bottom of the stacked structure 820.

In this embodiment, the third sacrificial layer is made of a material having an etching selectivity ratio with respect to the stacked structure 820, so that damage to the stacked structure 820 is reduced when the third sacrificial layer is subsequently removed.

As an example, in the stacked-layer structure 820, the material of the first channel layer (not labeled) is silicon, the material of the first sacrificial layer (not labeled) is silicon germanium, and thus, the material of the third sacrificial layer is also silicon germanium, and the concentration of germanium in the third sacrificial layer is greater than the concentration of germanium in the first sacrificial layer.

In the silicon germanium material, the higher the germanium concentration, the higher the etched rate of the silicon germanium material is, and therefore, the third sacrificial layer is made of silicon germanium with higher germanium concentration, so that the third sacrificial layer is easy to remove, and the damage to the stacked structure 820 is small.

Moreover, the material of the third sacrificial layer is also a semiconductor material, so that epitaxial growth is performed on the third sacrificial layer, which correspondingly reduces the influence on the stacked structure 820, and the process compatibility is high.

Accordingly, in this embodiment, the isolation wall 870 also penetrates through the third sacrificial layer.

In this embodiment, after the isolation wall 870 is formed, the third sacrificial layer is removed, and a trench (not shown) is formed between the stacked structure 820 and the substrate.

The trench is surrounded by the bottom of the stacked structure 820, the top of the substrate, and the sidewalls of the isolation walls 870.

The trench is used for providing a space position for the formation of a subsequent isolation layer.

In this embodiment, the third sacrificial layer is removed by an isotropic etching process, so as to completely remove the third sacrificial layer at the bottom of the stacked structure 820.

It should be noted that the isolation wall 870 is located on the substrate between adjacent sub-device regions (not labeled), specifically, the isolation wall 870 is located between the stacked structures 820, and the isolation wall 870 covers the sidewalls of the stacked structures 120 on two sides, so that the end of the stacked structure 120 is in contact with the sidewall of the isolation wall 870, and the stacked structure 120 can be suspended on the substrate after the third sacrificial layer is removed under the supporting action of the isolation wall 870.

Referring to fig. 15, an isolation layer 804 is formed in the trench.

The isolation layer 804 is used for isolating a subsequently formed gate structure from a substrate, so that the probability of leakage current generated between the gate structure and the substrate is reduced, and the formation of a parasitic device is favorably inhibited.

Specifically, the step of forming the isolation layer 804 in the trench includes: forming an isolation film covering the top and sidewalls of the stacked structure 120, the top and sidewalls of the isolation wall 870, the top of the substrate, and the sidewalls of the fin 810, the isolation film further filling the trench; the top and sidewalls of the stacked structure 120, the top and sidewalls of the isolation wall 870, the top of the substrate, and the sidewalls of the fin 810 are etched away, and the remaining isolation film in the trench is retained as the isolation layer 804.

The trench is surrounded by the bottom of the stacked structure 820, the top of the substrate, and the sidewall of the isolation wall 870, so that the isolation film in the trench can be retained under the shielding effect of the stacked structure 820 during the etching of the isolation film.

As an example, an atomic layer deposition process is used to form the isolation film to improve the filling effect of the isolation film in the trench.

The material of the isolation layer 804 includes a dielectric material. In particular, the dielectric material comprises one or more of silicon oxide, silicon oxynitride and silicon nitride. As an example, the material of the isolation layer 804 is silicon oxide.

In this embodiment, the isolation layer 804 is a film structure, and compared with a scheme in which an isolation layer is formed by performing ion implantation on a substrate (that is, a scheme in which an isolation layer is an ion doped layer), this embodiment can avoid a problem that parasitic capacitance is increased due to the ion implantation on the substrate.

In this embodiment, after the isolation layer 804 is formed, an isolation structure 801 is formed on the substrate on the side of the fin 810, and the isolation structure 801 covers the sidewalls of the fin 810 and the sidewalls of the isolation layer 804 and exposes the stacked structure 820.

Specifically, the top of the isolation structure 801 is flush with the top of the isolation layer 804.

Referring to fig. 16 in combination, a schematic structural view after forming a gate structure is shown, fig. 16 (a) is a cross-sectional view taken along a direction perpendicular to a sidewall of a partition wall, and fig. 16 (b) is a cross-sectional view taken along an extending direction of the partition wall at a side of the partition wall. Accordingly, the second channel layer (not shown) is epitaxially grown on the surface of the first channel layer exposed by the isolation wall (not shown), and since the isolation layer 804 covers the substrate below the first channel layer, the second channel layer is not formed on the surface of the isolation layer 804 in the process of epitaxially growing the second channel layer, so that the bottom of the gate structure (not shown) is in contact with the isolation layer 804.

As an example, in the process of forming a source-drain doping layer (not labeled), the bottom of the source-drain groove exposes the isolation layer 804, so that the bottom of the source-drain doping layer contacts the isolation layer 804, the source-drain doping layer is effectively isolated by the isolation layer 804, and the probability of punch-through between the source-drain doping layers is reduced.

In other embodiments, the bottom of the source-drain groove is also etched to expose the top of the fin portion 810, and accordingly, the source-drain doping layer is in contact with the substrate, so that the growth rate of the source-drain doping layer is increased, the growth quality of the source-drain doping layer is improved, and defects generated in the growth process are reduced.

It should be noted that the process after forming the isolation layer 804 is the same as the foregoing embodiment, and the description of this embodiment is omitted here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A semiconductor structure, comprising:

a substrate including a discrete device cell region including a plurality of sub-device regions adjacent in a first direction;

the channel structure layers extend along a second direction, are respectively positioned on the substrate of the sub-device region and are arranged at intervals with the substrate, the second direction is vertical to the first direction, and the channel structure layers comprise one or more first channel layers arranged at intervals;

the isolation wall is positioned on the substrate between the adjacent sub-device regions and extends along the second direction, the isolation wall covers the side walls of the channel structure layer on two sides, and the top of the isolation wall is higher than that of the channel structure layer;

the second channel layer is positioned on the top surface, the bottom surface and the side surfaces of the first channel layer exposed by the isolation wall, the junction between the top surface of the first channel layer and the side wall of the isolation wall and the junction between the bottom surface of the first channel layer and the side wall of the isolation wall form an acute angle, and the second channel layer and the first channel layer are used for forming a channel layer;

the gate structure is positioned on the substrate of the sub-device region and transversely crosses the channel structure layer along the first direction, the gate structure covers the top and the side wall of the channel structure layer of the sub-device region, and the gate structure comprises a gate dielectric layer which surrounds a second channel layer covering the device region and a gate electrode layer which covers the gate dielectric layer;

and the source-drain doped layers are positioned on the substrate at two sides of the gate structure of the sub-device region and cover the end surface of the channel structure layer below the gate structure, and the source-drain doped layers of the adjacent sub-device regions are isolated by the isolation wall.

2. The semiconductor structure of claim 1, wherein an angle between an end surface of the second channel layer and an exposed sidewall of the isolation wall of the first channel layer is 35 degrees to 75 degrees.

3. The semiconductor structure of claim 1, further comprising: and the isolation layer is positioned below the channel structure layer and between the bottom of the grid structure and the top of the substrate.

4. The semiconductor structure of claim 1, wherein in the device cell region, the sub-device regions include a first sub-device region for forming a transistor of a first type and a second sub-device region for forming a transistor of a second type, the transistors of the first and second types having different channel conductivity types;

the isolation wall is located on the substrate between the first sub-device region and the second sub-device region.

5. The semiconductor structure of claim 1, wherein the base comprises a substrate and a fin protruding above the substrate of the device cell region;

the channel structure layer is respectively positioned on the fin parts of the sub-device regions and is arranged at intervals with the fin parts;

the bottom of the partition wall extends into the fin.

6. The semiconductor structure of claim 1, wherein portions of the gate structure between adjacent ones of the channel layers and between a channel layer and a substrate are first portions;

the semiconductor structure further includes: and the inner side wall is positioned between the source-drain doped layer and the first part.

7. The semiconductor structure of claim 6, wherein a remaining portion of the gate structure serves as a second portion;

the top surface of the source-drain doped layer is higher than the top surface of the channel structure layer;

the inner side wall is also positioned between the source-drain doped layer and the second part.

8. The semiconductor structure of claim 1, wherein the material of the first channel layer comprises silicon, silicon germanium, or a group iii-v semiconductor material, and the material of the second channel layer comprises silicon, silicon germanium, or a group iii-v semiconductor material.

9. The semiconductor structure of claim 1, wherein the second channel layer has a thickness of

To

10. The semiconductor structure of claim 1, wherein the material of the isolation wall comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride, and silicon carbonitride.

11. The semiconductor structure of claim 2, wherein the material of the isolation layer comprises a dielectric material comprising one or more of silicon oxide, silicon oxynitride, and silicon nitride.

12. The semiconductor structure of claim 1, wherein the material of the gate dielectric layer comprises HfO ₂ 、ZrO ₂ 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al ₂ O ₃ 、SiO ₂ And La ₂ O ₃ The gate electrode layer is made of one or more materials including one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAl C.

13. A method of forming a semiconductor structure, comprising:

providing a substrate comprising discrete device unit regions, wherein the device unit regions comprise a plurality of sub-device regions adjacent to each other in a first direction, laminated structures extending along a second direction are respectively formed on the substrate of the plurality of sub-device regions, the second direction is perpendicular to the first direction, the laminated structures comprise one or more stacked channel laminated layers, each channel laminated layer comprises a first sacrificial layer and a first channel layer located on the first sacrificial layer, and isolation walls extending along the second direction are formed on the substrate between the adjacent sub-device regions and cover the side walls of the laminated structures on two sides;

forming a dielectric layer covering part of the laminated structure on the substrate, wherein a gate opening penetrating through the dielectric layer and extending along the first direction is formed in the dielectric layer, and the gate opening crosses the laminated structure and the isolation wall of the device unit region and exposes part of the top and part of the side wall of the laminated structure;

removing the first sacrificial layer through the gate opening to form a through groove communicated with the gate opening;

after the through groove is formed, forming a second channel layer on the top surface, the bottom surface and the side surface of the first channel layer exposed by the gate opening and the through groove, wherein an included angle between the end surface of the second channel layer and the side wall of the isolation wall exposed by the first channel layer is an acute angle at the junction of the top surface of the first channel layer and the side wall of the isolation wall and at the junction of the bottom surface of the first channel layer and the side wall of the isolation wall, and the second channel layer and the first channel layer are used for forming the channel layer;

and forming a gate structure in the gate opening and the through groove, wherein the gate structure comprises a gate dielectric layer surrounding and covering the second channel layer and a gate electrode layer covering the gate dielectric layer.

14. The method of forming a semiconductor structure of claim 13, wherein the second channel layer is formed using an epitaxial growth process.

15. The method of forming a semiconductor structure of claim 14, wherein the process temperature of the epitaxial growth process is 200 ℃ to 500 ℃.

16. The method of forming a semiconductor structure of claim 13, wherein prior to forming a dielectric layer overlying a portion of the stacked structure on the substrate, the method further comprises: forming a pseudo gate structure on the substrate, wherein the pseudo gate structure transversely spans the laminated structure and the partition wall along the first direction; forming source and drain doping layers in the laminated structures on the two sides of the pseudo gate structure, wherein the source and drain doping layers of the adjacent sub-device regions are isolated by the isolation wall;

the step of forming a dielectric layer on the substrate to cover a part of the laminated structure comprises: after the source-drain doping is formed, forming a dielectric layer covering the side wall of the pseudo gate structure on the substrate, wherein the dielectric layer is exposed out of the top of the pseudo gate structure;

the step of forming the gate opening includes: and removing the pseudo gate structure.

17. The method of forming a semiconductor structure according to claim 13, wherein in the step of providing a substrate, the stack structure further includes a second sacrificial layer on top of the topmost channel stack, the second sacrificial layer and the first sacrificial layer being made of the same material;

and in the step of removing the first sacrificial layer through the gate opening, the second sacrificial layer exposed by the gate opening is also removed.

18. The method of forming a semiconductor structure of claim 13, wherein in the step of providing a substrate, an isolation layer is further formed between the lowest layer of the channel stack and the substrate.

19. The method of forming a semiconductor structure of claim 13, wherein in the step of providing a substrate, in the device cell region, the sub-device regions include a first sub-device region for forming a transistor of a first type and a second sub-device region for forming a transistor of a second type, channel conductivity types of the transistor of the first type and the transistor of the second type being different;

the isolation wall is formed on the substrate between the first sub-device region and the second sub-device region.

20. The method of claim 13, wherein in the step of providing a base, the base comprises a substrate and a fin protruding from the substrate in the device cell region; the laminated structure is separated from the top of the fin part, and the bottom of the isolation wall extends into the fin part.