CN117810259A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN117810259A CN117810259A CN202211206999.6A CN202211206999A CN117810259A CN 117810259 A CN117810259 A CN 117810259A CN 202211206999 A CN202211206999 A CN 202211206999A CN 117810259 A CN117810259 A CN 117810259A
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- 238000000034 method Methods 0.000 title claims abstract description 124
- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 239000010410 layer Substances 0.000 claims abstract description 475
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 238000005530 etching Methods 0.000 claims abstract description 79
- 239000011241 protective layer Substances 0.000 claims abstract description 68
- 239000000463 material Substances 0.000 claims description 94
- 230000008569 process Effects 0.000 claims description 94
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- 238000001312 dry etching Methods 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- 229910018072 Al 2 O 3 Inorganic materials 0.000 claims description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims description 3
- 229910004129 HfSiO Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 229910010041 TiAlC Inorganic materials 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052731 fluorine Inorganic materials 0.000 claims description 3
- 239000011737 fluorine Substances 0.000 claims description 3
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 3
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- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 6
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- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
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- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 4
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 4
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Abstract
A semiconductor structure and a method of forming the same, comprising: providing a substrate, wherein a channel laminated structure is formed on the top of the substrate, the channel laminated structure comprises one or more stacked channel laminated layers, each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, a grid structure crossing the channel laminated structure is formed on the top of the substrate, and the grid structure covers part of the top and part of the side wall of the channel laminated structure; forming a side wall layer on the side wall of the grid structure; forming a protective layer on the side wall of the side wall layer, wherein an etching selection ratio is arranged between the sacrificial layer and the protective layer; forming grooves in the channel laminated structures at two sides of the grid structure, wherein the side walls of the grooves expose the channel laminated structures; forming an inner groove by transversely etching part of the sacrificial layer exposed out of the side wall of the groove along the direction parallel to the substrate and perpendicular to the extending direction of the grid structure; forming an inner wall side wall layer in the inner groove; and forming a source-drain doped layer in the groove. The protective layer reduces the probability of damage to the sidewall layer.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor transistors are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor transistors, and therefore, as the element density and integration level of the semiconductor transistors are increased, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
To better accommodate the demands of transistor scaling, semiconductor processes are gradually beginning to transition from planar transistors to three-dimensional transistors with higher power, such as fin field effect transistors (finfets), gate-all-around (GAA) transistors, and the like. Wherein the fully-enclosed gate transistors include vertical fully-enclosed gate transistors and horizontal fully-enclosed gate transistors. In the fully-enclosed gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.
As device dimensions shrink further, it becomes increasingly difficult and challenging to improve the performance of fully surrounding gate structure devices.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to further improving the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; the channel structure layer is suspended on the top of the substrate and comprises one or more channel layers which are arranged at intervals in the longitudinal direction; a device gate structure on the substrate and crossing the channel structure layer, the device gate structure covering a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer, the sidewall of the device gate structure directly under the channel layer being recessed relative to the sidewall of the channel layer in a direction parallel to the substrate and perpendicular to an extension direction of the device gate structure; the source-drain doped layers are positioned in the channel structure layers at two sides of the grid structure of the device; the side wall layer is positioned on the side wall of the device grid structure; the protective layer is positioned on the side wall of the side wall layer; the inner wall side wall layer is positioned between the side wall of the device grid structure right below the channel layer and the source-drain doping layer.
Correspondingly, the embodiment of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein a channel laminated structure is formed on the top of the substrate, the channel laminated structure comprises one or more stacked channel laminated layers, each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, a grid structure crossing the channel laminated structure is formed on the top of the substrate, and the grid structure covers part of the top and part of the side wall of the channel laminated structure; forming a side wall layer on the side wall of the grid structure; forming a protective layer on the side wall of the side wall layer, wherein an etching selection ratio is arranged between the sacrificial layer and the protective layer; after forming the protective layer, forming grooves in the channel laminated structures at two sides of the grid structure, wherein the side walls of the grooves expose the channel laminated layers; forming an inner groove by transversely etching part of the sacrificial layer exposed out of the side wall of the groove along the direction parallel to the substrate and perpendicular to the extending direction of the grid structure, wherein the inner groove is surrounded by the adjacent channel layer and the rest of the sacrificial layer, or the inner groove is surrounded by the substrate, the channel layer adjacent to the substrate and the rest of the sacrificial layer; forming an inner wall side wall layer in the inner groove; and after forming the inner wall side wall layer, forming a source-drain doping layer in the groove.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a side wall layer on the side wall of a grid structure, forming a protective layer on the side wall of the side wall layer, wherein an etching selection ratio is arranged between a sacrificial layer and the protective layer, and correspondingly, in the process of subsequently transversely etching part of the sacrificial layer exposed out of the side wall of a groove, the etching selection ratio is arranged between the sacrificial layer and the protective layer, so that the protective layer is not easy to remove in the etching process for removing the sacrificial layer, namely, the protective layer protects the side wall of the side wall layer, the probability of damage to the side wall layer is reduced, and correspondingly, the risk of exposing the grid structure is reduced, thereby improving the performance of the semiconductor structure.
Drawings
Fig. 1 to 3 are schematic structural views corresponding to steps of a method for forming a semiconductor structure;
FIG. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 5 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The performance of current semiconductor structures is to be improved. The reasons for the improvement in performance are now analyzed in connection with a semiconductor structure.
Fig. 1 to 3 are schematic structural views corresponding to steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 10 is provided, a channel stack structure 19 is formed on top of the substrate 10, the channel stack structure 19 includes one or more stacked channel stacks 12, each channel stack 12 includes a sacrificial layer 11 and a channel layer 13 on the sacrificial layer 11, a gate structure 15 is formed on top of the substrate 10 across the channel stack structure 19, the gate structure 15 covers a portion of the top and a portion of the sidewalls of the channel stack structure 19, and a sidewall of the gate structure 15 is formed with a sidewall layer 14.
Referring to fig. 2, a recess 20 is formed in the channel stack structure 19 on both sides of the gate structure 15, and the sidewalls of the recess 20 expose the channel stack 12.
Referring to fig. 3, the portion of the sacrificial layer 11 exposed from the sidewall of the recess 20 is laterally etched in a direction parallel to the substrate 10 and perpendicular to the extending direction of the gate structure 15.
According to research, in the process of transversely etching the exposed part of the sacrificial layer 11 on the side wall of the groove 20 by adopting the etching process, the etching process also easily causes the consumed part of the side wall layer 14 on the side wall of the gate structure 15, and accordingly, the probability of damaging the side wall layer 14 is greatly improved, so that the risk of exposing the gate structure 15 is increased, and the performance of the semiconductor structure is improved.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein a channel laminated structure is formed on the top of the substrate, the channel laminated structure comprises one or more stacked channel laminated layers, each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, a grid structure crossing the channel laminated structure is formed on the top of the substrate, and the grid structure covers part of the top and part of the side wall of the channel laminated structure; forming a side wall layer on the side wall of the grid structure; forming a protective layer on the side wall of the side wall layer, wherein an etching selection ratio is arranged between the sacrificial layer and the protective layer; after forming the protective layer, forming grooves in the channel laminated structures at two sides of the grid structure, wherein the side walls of the grooves expose the channel laminated layers; forming an inner groove by transversely etching part of the sacrificial layer exposed out of the side wall of the groove along the direction parallel to the substrate and perpendicular to the extending direction of the grid structure, wherein the inner groove is surrounded by the adjacent channel layer and the rest of the sacrificial layer, or the inner groove is surrounded by the substrate, the channel layer adjacent to the substrate and the rest of the sacrificial layer; forming an inner wall side wall layer in the inner groove; and after forming the inner wall side wall layer, forming a source-drain doping layer in the groove.
The embodiment of the invention provides a method for forming a semiconductor structure, which comprises the steps of forming a side wall layer on the side wall of a grid structure, forming a protective layer on the side wall of the side wall layer, wherein an etching selection ratio is arranged between a sacrificial layer and the protective layer, and correspondingly, in the process of subsequently transversely etching part of the sacrificial layer exposed out of the side wall of a groove, the etching selection ratio is arranged between the sacrificial layer and the protective layer, so that the protective layer is not easy to remove in the etching process for removing the sacrificial layer, namely, the protective layer protects the side wall of the side wall layer, the probability of damage to the side wall layer is reduced, and correspondingly, the risk of exposing the grid structure is reduced, thereby improving the performance of the semiconductor structure.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: a substrate (not labeled); a channel structure layer 202 suspended on top of the substrate, the channel structure layer 202 including one or more channel layers 2022 disposed at intervals in a longitudinal direction; a device gate structure 270 on the substrate and crossing the channel structure layer 202, the device gate structure 270 covering a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 2022, the sidewall of the device gate structure 270 directly under the channel layer 2022 being recessed relative to the sidewall of the channel layer 2022 in a direction parallel to the substrate and perpendicular to the extension direction of the device gate structure 270; source-drain doped layer 296 located in channel structure layer 202 on both sides of device gate structure 270; a sidewall layer 203 located on the sidewall of the device gate structure 270; a protective layer 280 located on the sidewall of the sidewall layer 203; the inner wall sidewall layer 295 is located between the sidewalls of the device gate structure 270 and the source drain doped layer 296 directly below the channel layer 2022.
It should be noted that, by disposing the protective layer 280 on the sidewall of the sidewall layer 203, in the process of forming the device gate structure 270, the protective layer 280 protects the sidewall of the sidewall layer 203, thereby reducing the probability of damage to the sidewall layer 203, and correspondingly reducing the risk of exposing the gate structure, so as to improve the performance of the semiconductor structure.
The substrate is used to provide a process platform for providing a Gate-all-around (GAA) transistor.
In this embodiment, the base is a three-dimensional base, and the base includes a substrate 200 and a protruding portion 201 protruding from the substrate 200.
In this embodiment, the substrate 200 is a silicon substrate 200. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
In this embodiment, the material of the bump 201 is the same as that of the substrate 200, and the material of the bump 201 is silicon. In other embodiments, the material of the protruding portion may be a semiconductor material suitable for forming the fin portion, such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the protruding portion may be different from the material of the substrate.
The channel structure layer 202 is used to provide a conductive channel for the transistor.
In this embodiment, each channel structure layer 202 includes one or more channel layers 2022 disposed at intervals.
In this embodiment, the channel structure layer 202 includes a plurality of channel layers 2022 disposed at intervals, and the stacking direction of the plurality of stacked channel layers 2022 is perpendicular to the surface of the substrate 200.
In this embodiment, the material of the channel structure layer 202 is the same as that of the bump 201, and the material of the channel structure layer 202 is Si.
The device gate structure 270 is used to control the opening and closing of the conduction channel when the device is in operation.
Specifically, the device gate structure 270 is a metal gate structure.
In this embodiment, the device gate structure 270 includes a gate dielectric layer (not shown) covering a portion of the top, a portion of the sidewall, and a portion of the bottom of the channel layer 2022, and a gate electrode layer (not shown) covering the gate dielectric layer.
In this embodiment, the gate dielectric layer comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following.
Specifically, the gate dielectric layer includes a gate oxide layer conformally covering a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 2022, and a high-k gate dielectric layer conformally covering the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, and the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
The gate electrode layer is used for being electrically connected with an external structure. The material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.
The source drain doped layer 296 serves as a source or drain region of the transistor.
When the fully-surrounding gate transistor is a P-type MOS transistor, the stress layer is made of Si or SiGe, and the doped ions in the source/drain doped layer 296 are P-type ions; when the fully-surrounding gate transistor is an N-type MOS transistor, the stress layer is made of Si or SiC, and the dopant ions in the source/drain dopant layer 296 are N-type ions.
The sidewall layer 203 is used to protect the sidewall of the gate structure.
In this embodiment, the sidewall 203 has a single-layer structure.
In this embodiment, the material of the sidewall layer 203 includes one or more of silicon nitride, fluorine doped silicon oxide and silicon oxynitride. As an example, the material of the sidewall layer 203 is silicon nitride.
It should be noted that, taking the direction parallel to the substrate and perpendicular to the extending direction of the device gate structure 270 as the lateral direction, the lateral dimension of the protection layer 280 should not be too large or too small. If the lateral dimension of the protection layer 280 is too large, the conductive channel is easy to be too long, on one hand, parasitic capacitance generated by the source-drain doped layer 296 is increased, and on the other hand, the area of the device gate structure 270, which covers the channel layer 2022, is reduced, so that the control capability of the device gate structure 270 on the conductive channel is weakened; if the lateral dimension of the protection layer 280 is too small, during the formation process of the device gate structure 270 (e.g., the lateral etching of a portion of the sacrificial layer), the protection effect of the protection layer 280 on the sidewall of the sidewall layer 203 is easily reduced, and the probability of damage to the sidewall layer 203 is increased, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the lateral dimension of the protection layer 280 is 3 nm to 5 nm, with the direction parallel to the substrate and perpendicular to the extending direction of the device gate structure 270 as the lateral direction.
In this embodiment, the material of the protective layer 280 includes one or both of silicon oxide and silicon oxycarbide.
Specifically, the hardness of the silicon oxide and silicon oxycarbide materials is relatively high, so that the silicon oxide and silicon oxycarbide materials can have a relatively good protection effect on the sidewall layer 203 during the formation process of the device gate structure 270, and the risk of exposing the sidewall of the device gate structure 270 is reduced, thereby improving the performance of the semiconductor structure.
The inner wall sidewall layer 295 can isolate the source/drain doped layer 296 from the device gate structure 270, which is beneficial to increasing the distance between the source/drain doped layer 296 and the device gate structure 270, and further to reducing the parasitic capacitance between the source/drain doped layer 296 and the device gate structure 270.
In this embodiment, the material of the inner wall sidewall layer 295 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.
In this embodiment, the semiconductor structure further includes: an interlayer dielectric layer 298 is located on top of the source drain doped layer 296 and covers the sidewalls of the gate structure.
Interlayer dielectric layer 298 is used to achieve electrical isolation between adjacent devices.
In this embodiment, the material of the interlayer dielectric layer 298 is silicon oxide.
Fig. 5 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5-6, a substrate is provided, a channel stack structure 190 is formed on top of the substrate, the channel stack structure 190 includes one or more stacked channel stacks 102, each channel stack 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021, a gate structure 104 is formed on top of the substrate across the channel stack structure 190, and the gate structure 104 covers a portion of the top and a portion of the sidewalls of the channel stack structure 190.
The substrate is used to provide a process platform for forming a Gate-all-around (GAA) transistor.
In this embodiment, the base is a three-dimensional base, and the base includes a substrate 100 and a protruding portion 101 protruding from the substrate 100.
In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.
The raised portion 101 exposes a portion of the substrate 100, thereby providing a process basis for the subsequent formation of an isolation layer.
In this embodiment, the material of the bump 101 is the same as that of the substrate 100, and the material of the bump 101 is silicon. In other embodiments, the material of the bump may be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, or other semiconductor materials suitable for forming a fin, and the material of the bump 101 may be different from the material of the substrate.
In this embodiment, the channel stack 102 is located on top of the protruding portion 101, and the extending direction of the channel stack 102 is the same as the extending direction of the protruding portion 101.
In this embodiment, the number of channel stacks 102 is plural, and the stacking direction of the plural stacked channel stacks 102 is perpendicular to the surface of the substrate 100.
Each channel stack 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021. The channel stack 102 provides a process basis for the subsequent formation of the channel layer 1022 that is spaced apart in a floating manner. Specifically, the sacrificial layer 1021 supports the channel layer 1022, thereby providing a process basis for the subsequent implementation of the spaced-apart suspended arrangement of the channel layer 1022, and also occupying a spatial position for the subsequent formation of the device gate structure, the channel layer 1022 being configured to provide a conductive channel for the fully-enclosed gate transistor.
Accordingly, when the number of the channel stacks 102 is plural, the number of the channel layers 1022 is plural, and the plural channel layers 1022 are disposed at intervals.
In this embodiment, the material of the channel layer 1022 is Si, and the material of the sacrificial layer 1021 is SiGe. In the subsequent process of laterally etching part of the sacrificial layer 1021, the etching selection of SiGe and Si is relatively high, so that the influence of the removal process of the sacrificial layer 1021 on the channel layer 1022 can be effectively reduced by setting the material of the sacrificial layer 1021 as SiGe and the material of the channel layer 1022 as Si, thereby improving the quality of the channel layer 1022 and further being beneficial to improving the device performance.
In this embodiment, an isolation layer (not shown) is further formed on the substrate 100 at the side of the protruding portion 101, and the isolation layer exposes the channel stack 102.
The spacer layer serves to provide a spacer function between adjacent bosses 101.
In this embodiment, the material of the isolation layer is silicon oxide.
In this embodiment, the gate structure 104 is a dummy gate structure, and the gate structure 104 occupies a space for subsequently forming a device gate structure. In this embodiment, the gate structure 104 includes a dummy gate layer. The material of the dummy gate layer includes polysilicon.
In this embodiment, the step of forming the gate structure 104 includes: forming a layer of gate material (not shown) over channel stack 102; forming a gate mask layer (not shown) on the gate material layer; the gate mask layer is used as a mask to remove the exposed gate material layer, and the remaining gate material layer on the channel stack 102 is used as the gate structure 104.
The gate mask layer is used as an etching mask when forming the gate structure 104, and can also protect the top of the gate structure 104 in a subsequent process.
In this embodiment, the material of the gate mask layer is silicon nitride.
Referring to fig. 7, a sidewall layer 103 is formed on the sidewall of the gate structure 104.
The sidewall layer 103 is used to protect the sidewall of the gate structure 104.
In this embodiment, the step of forming the sidewall layer 103 includes: forming a sidewall material layer (not shown) on top of and sidewalls of the gate structure 104 and on top of the channel stack structure 190 where the gate structure 104 is exposed; the sidewall material layer on top of the gate structure 104 and the sidewall material layer on top of the channel stack structure 190 are removed, and the remaining sidewall material layer on the sidewall of the gate structure 104 is used as the sidewall layer 103.
In this embodiment, the process of forming the sidewall material layer includes an atomic layer deposition process.
In this embodiment, the process of removing the sidewall material layer on top of the gate structure 104 and the sidewall material layer on top of the channel stack structure 190 includes a dry etching process.
Specifically, the dry etching process includes an anisotropic dry etching process.
Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, the longitudinal etching rate is larger than the transverse etching rate, the profile controllability of the anisotropic dry etching process is good, the profile appearance quality of the side wall layer 103 is improved, in addition, the selected anisotropic dry etching process is beneficial to realizing higher etching selection ratio, and the probability of misetching other film layers is further reduced.
In this embodiment, the sidewall 103 has a single-layer structure.
In this embodiment, the material of the sidewall layer 103 includes one or more of silicon nitride, fluorine doped silicon oxide and silicon oxynitride. As an example, the material of the sidewall layer 103 is silicon nitride.
Referring to fig. 8, a protective layer 180 is formed on a sidewall of the sidewall layer 103, and an etching selectivity is provided between the sacrificial layer 1021 and the protective layer 180.
In the subsequent process of laterally etching the part of the sacrificial layer 1021 exposed from the side wall of the groove, an etching selection ratio is formed between the sacrificial layer 1021 and the protective layer 180, so that the protective layer 180 is not easy to remove in the etching process for removing the sacrificial layer 1021, namely, the protective layer 180 plays a role in protecting the side wall of the side wall layer 103, the probability of damage to the side wall layer 103 is reduced, and accordingly, the risk of exposure of the gate structure 104 is reduced, and the performance of the semiconductor structure is improved.
In this embodiment, the step of forming the protective layer 180 includes: forming a protective material layer (not shown) on top of the gate structure 104, sidewalls of the sidewall layer 103, and top of the channel stack structure 190 where the gate structure 104 is exposed; the protective material layer on top of the gate structure 104 and the protective material layer on top of the channel stack structure 190 are removed, and the remaining protective material layer on the sidewalls of the sidewall layer 103 serves as a protective layer 180.
In this embodiment, the process of forming the protective material layer includes an atomic layer deposition process.
Specifically, the atomic layer deposition process has good step coverage, so that the probability of generating a gap between the interface of the protective layer 180 and the gate structure 104 is reduced, and meanwhile, the atomic layer deposition process comprises multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the protective material layer, so that the thickness of the protective layer 180 on the side wall of the side wall layer 103 can meet the process size requirement, and the protective effect of the protective layer 180 on the side wall of the side wall layer 103 is ensured.
In this embodiment, the process of removing the protective material layer on top of the gate structure 104 and the protective material layer on top of the channel stack structure 190 includes a plasma dry etching process.
Specifically, the plasma dry etching process has the characteristics of high etching controllability and the like, and the protective material layer at the top of the gate structure 104 and the protective material layer at the top of the channel laminated structure 190 are removed by adopting the plasma dry etching process, so that plasma and the protective material layer at the top of the gate structure 104 and the protective material layer at the top of the channel laminated structure 190 are subjected to chemical reaction, the purpose of removing the protective material layer at the top of the gate structure 104 and the protective material layer at the top of the channel laminated structure 190 is achieved, and the protective material layer at the side wall of the side wall layer 103 is kept to serve as the protective layer 180.
It should be noted that, as an example, after the sidewall of the gate structure 104 forms the sidewall layer 103, a protective material layer is formed, and then the protective material layer on top of the gate structure 104 and the protective material layer on top of the channel stack structure 190 are removed separately, so that the formed protective layer 180 can fully cover the sidewall of the sidewall layer 103, and correspondingly, in the subsequent process of laterally etching part of the sacrificial layer 1021, the protective layer 180 can fully protect the sidewall of the sidewall layer 103, thereby reducing the probability that the sidewall layer 103 is damaged, and further improving the performance of the semiconductor structure.
It should be noted that, in the lateral direction parallel to the substrate and perpendicular to the extending direction of the gate structure, the lateral dimension of the protection layer 180 is not too large or too small. If the lateral dimension of the protection layer 180 is too large, the conducting channel is easy to be too long, on one hand, parasitic capacitance generated by a subsequently formed source-drain doped layer is increased, and on the other hand, the area of a subsequently formed device gate structure cladding channel layer 1022 is reduced, so that the control capability of the device gate structure on the conducting channel is weakened; if the lateral dimension of the protection layer 180 is too small, the protection effect of the protection layer 180 on the sidewall of the sidewall layer 103 is easily reduced in the subsequent process of laterally etching a part of the sacrificial layer 1021, so that the probability of damage to the sidewall layer 103 is increased, and the performance of the semiconductor structure is affected. For this reason, in the present embodiment, the lateral dimension of the protection layer 180 is 3 nm to 5 nm with the lateral direction being the direction parallel to the substrate and perpendicular to the extending direction of the gate structure of the device.
In this embodiment, the material of the protective layer 180 includes one or both of silicon oxide and silicon oxycarbide.
Specifically, the etching selectivity between the sacrificial layer 1021 and the silicon oxide and silicon oxycarbide of the materials selected for the protective layer 180 is greater than the etching selectivity between the sacrificial layer 1021 and the side wall layer 103, so that the protective layer 180 is not easy to remove in the etching process of removing the sacrificial layer 1021 in the subsequent process of removing the sacrificial layer 1021, and the protective effect of the protective layer 180 on the side wall layer 103 is improved.
Referring to fig. 9, after forming the protective layer 180, the method for forming the semiconductor structure further includes, before subsequently forming the recess: the compensation layer 191 is formed on the sidewall of the protection layer 180.
It should be noted that, by forming the compensation layer 191, in the subsequent process of forming the groove, the size of the groove can be controlled, so that the distance between the source-drain doped layer formed in the groove and the device gate structure formed subsequently can meet the process size requirement, and thus the parasitic capacitance between the source-drain doped layer and the device gate structure can be reduced.
In this embodiment, the step of forming the compensation layer 191 includes: forming a compensation material layer (not shown) on sidewalls of the protection layer 180, on top of the gate structure 104, and on top of the channel stack structure 190 where the gate structure 104 is exposed; the compensation material layer on top of the gate structure 104 and on top of the channel stack structure 190 is removed and the remaining compensation material layer on the sidewalls of the gate structure 104 serves as a compensation layer 191.
In this embodiment, the process of forming the compensation material layer includes an atomic layer deposition process.
In this embodiment, the process of removing the compensation material layer on top of the gate structure 104 and on top of the channel stack structure 190 includes an anisotropic dry etching process.
In this embodiment, the material of the compensation layer 191 includes one or more of silicon nitride, silicon oxide, and silicon oxycarbide.
Specifically, the hardness of the silicon nitride, silicon oxide and silicon oxycarbide materials is relatively high, and the channel stack structure 190 exposed at both sides of the gate structure 104 can be removed by using the etching selectivity between the compensation layer 191 and the channel stack structure 190 in the subsequent recess forming process. As an example, the material of the compensation layer 191 is silicon nitride.
It should be noted that, taking the direction parallel to the substrate and perpendicular to the extending direction of the gate structure 104 as the lateral direction, the lateral dimension of the compensation layer 191 should not be too large or too small. If the lateral dimension of the compensation layer 191 is too large, the lateral dimension of the groove is too small, so that the depth-to-width ratio of the groove is increased, the filling difficulty of the source-drain doped layer formed later is increased, and meanwhile, the probability of forming a cavity in the source-drain doped layer is increased, so that the performance of the semiconductor structure is influenced; if the lateral dimension of the compensation layer 191 is too small, the lateral dimension of the recess is easily increased, so that the distance between the source-drain doped layer formed in the recess and the device gate structure formed in the recess is reduced, thereby increasing the parasitic capacitance between the source-drain doped layer and the device gate structure and further improving the performance of the semiconductor structure. For this reason, in the present embodiment, the lateral dimension of the compensation layer 191 is 3 nm to 7 nm with the direction parallel to the substrate and perpendicular to the extending direction of the gate structure 104 as the lateral direction.
Referring to fig. 10, after the protective layer 180 is formed, a recess 192 is formed in the channel stack structure 190 on both sides of the gate structure 104, and the sidewalls of the recess 192 expose the channel stack 102.
Specifically, the grooves 192 provide space for the subsequent formation of source and drain doped layers, and also provide process windows for the subsequent lateral etching of portions of the sacrificial layer 1021.
In this embodiment, the process of forming the recess 192 includes a dry etching process.
Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has better profile control, is beneficial to improving the profile shape quality of the groove 192, and is beneficial to realizing higher etching selection ratio by the selected anisotropic dry etching process, thereby reducing the probability of misetching other film layers.
Referring to fig. 11, the inner trench 193 is formed by laterally etching a portion of the sacrificial layer 1021 exposed from the sidewall of the recess 192 in a direction parallel to the substrate and perpendicular to the extending direction of the gate structure 104, wherein the inner trench 193 is surrounded by the adjacent channel layer 1022 and the remaining sacrificial layer 1021, or the inner trench 193 is surrounded by the substrate, the channel layer 1022 adjacent to the substrate, and the remaining sacrificial layer 1021.
Specifically, the inner trench 193 provides a space position for forming an inner wall side wall layer subsequently, so that after the source-drain doping layer is formed subsequently and the device gate structure is formed at the position of the sacrificial layer 1021, the inner wall side wall layer is located between the source-drain doping layer and the device gate structure, and can play a role in isolating between the source-drain doping layer and the device gate structure, thereby being beneficial to increasing the distance between the source-drain doping layer and the device gate structure and further being beneficial to reducing parasitic capacitance between the source-drain doping layer and the device gate structure.
In this embodiment, the process of laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the recess 192 includes an isotropic dry etching process.
It should be noted that, the isotropic dry etching process has the characteristic of an isotropic etching process, and can etch the sacrificial layer 1021 along a direction parallel to the substrate and perpendicular to the extending direction of the gate structure 104, and the isotropic dry etching process is easy to realize a larger etching selection ratio, which is beneficial to reducing the difficulty of etching the sacrificial layer 1021 and reducing the probability of damaging other film structures, and meanwhile, the isotropic dry etching process can enable the side wall portion of the sacrificial layer 1021 to be uniformly etched and removed, thereby reducing the probability of foot effect defects (Footing defects) of the residual sacrificial layer 1021 appearing on the surface of the channel layer 1022 exposed by the inner trench 193, and further improving the performance of the semiconductor structure.
In this embodiment, the etching gas of the isotropic dry etching process includes CF 4 、NF 3 And O 2 One or more of the following.
It should be noted that CF 4 、NF 3 And O 2 Is the etching gas commonly used in the etching process, has the characteristics of low process cost and the like, and adopts CF at the same time 4 、NF 3 And O 2 The etching gas can realize the high etching selection ratio of the sacrificial layer 1021 to the channel layer 1022 and the sacrificial layer 1021 to the protective layer 180, so that the protective layer 180 and the channel layer 1022 are not easy to remove in the process of removing the sacrificial layer 1021, meanwhile, the protective layer 180 plays a role in protecting the side wall of the side wall layer 103, the damage probability of the side wall layer 103 is reduced, the risk that the subsequently formed device grid structure is exposed is correspondingly reduced, and the performance of the semiconductor structure is improved.
In this embodiment, in the process of laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the recess 192, the etching selectivity of the sacrificial layer 1021 to the protective layer 180 is greater than that of the sacrificial layer 1021 to the sidewall layer 103.
Specifically, the etching selectivity of the sacrificial layer 1021 to the protective layer 180 is greater than that of the sacrificial layer 1021 to the side wall layer 103, so that the protective layer 180 is not easy to be removed in the etching process of removing the sacrificial layer 1021, namely, the protective layer 180 plays a role in protecting the side wall of the side wall layer 103, the probability of damaging the side wall layer 103 is reduced, the risk of exposing the gate structure 104 is correspondingly reduced, and therefore, the performance of the semiconductor structure is improved, and meanwhile, after the gate structure 104 is subsequently removed to form a device gate structure, the protective layer 180 is also used as an insulating isolation layer of the device gate structure, namely, the protective layer 180 plays a role in electrically isolating the adjacent device gate structure, so that the performance of the semiconductor structure is improved.
It should be noted that, in the process of laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the recess 192, the etching selectivity between the sacrificial layer 1021 and the channel layer 1022 should not be too small. If the etching selectivity between the sacrificial layer 1021 and the channel layer 1022 is too small, the etching selectivity between the sacrificial layer 1021 and the channel layer 1022 is easy to approach, accordingly, in the subsequent process of laterally etching part of the sacrificial layer 1021, the probability of etching and removing the channel layer 1022 is increased, so that the conductive channel of the transistor is damaged, and the performance of the semiconductor structure is affected. For this reason, in the process of laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the recess 192 in this embodiment, the etching selectivity between the sacrificial layer 1021 and the channel layer 1022 is greater than 6:1.
it should be noted that, in the process of laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the recess 192, the etching selectivity between the sacrificial layer 1021 and the protection layer 180 should not be too small. If the etching selectivity between the sacrificial layer 1021 and the protective layer 180 is too small, the etching selectivity between the sacrificial layer 1021 and the protective layer 180 is easy to approach, accordingly, in the subsequent process of laterally etching part of the sacrificial layer 1021, the probability of etching and removing the protective layer 180 is increased, the protective effect of the protective layer 180 on the sidewall layer 103 is affected, and accordingly, the risk of exposing the subsequently formed device gate structure is increased, so that the performance of the semiconductor structure is affected. For this reason, in the process of laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the recess 192, the etching selectivity between the sacrificial layer 1021 and the protection layer 180 is greater than 20:1.
In this embodiment, during the process of laterally etching the part of the sacrificial layer 1021 exposed from the side wall of the groove 192, the compensation layer 191 is also removed, that is, part of the sacrificial layer 1021 and the compensation layer 191 are removed in the same step, so that the process steps are reduced, and the process cost is reduced. In other embodiments, the compensation layer 191 may be removed after laterally etching the exposed portion of the sacrificial layer 1021 on the sidewall of the recess 192.
Referring to fig. 12, an inner wall sidewall layer 195 is formed in the inner trench 193.
The inner wall side wall layer 195 can play an isolating role between the source/drain doped layer and the subsequently formed device gate structure, which is beneficial to increasing the distance between the source/drain doped layer and the device gate structure and further beneficial to reducing the parasitic capacitance between the source/drain doped layer and the device gate structure.
In this embodiment, the material of the inner wall sidewall layer 195 includes one or more of silicon nitride, silicon oxide and silicon oxynitride.
Referring to fig. 13, after forming the inner wall sidewall layer 195, a source drain doped layer 196 is formed in the recess 192.
The source-drain doped layer 196 serves as a source or drain region of the transistor.
In this embodiment, the process of forming the source/drain doped layer 196 in the recess 192 includes an epitaxial process.
When the fully-surrounding gate transistor is a P-type MOS transistor, the stress layer is made of Si or SiGe, and the doped ions in the source/drain doped layer 196 are P-type ions; when the fully-surrounding gate transistor is an N-type MOS transistor, the stress layer is made of Si or SiC, and the dopant ions in the source/drain dopant layer 196 are N-type ions.
Referring to fig. 14, an interlayer dielectric layer 198 is formed atop the source drain doped layer 196, the interlayer dielectric layer 198 covering sidewalls of the gate structure 104.
Interlayer dielectric layer 198 is used to achieve electrical isolation between adjacent devices.
In this embodiment, the material of the interlayer dielectric layer 198 is silicon oxide.
Referring to fig. 15-16, gate structure 104 is removed and a gate opening 199 is formed in interlayer dielectric layer 198; after forming the gate opening 199, removing the sacrificial layer 1021; device gate structure 170 is formed in gate opening 199, as well as in the region where sacrificial layer 1021 is removed.
Specifically, the gate opening 199 provides a process window for the subsequent formation of the removal sacrificial layer 1021, as well as providing a spatial location for the subsequent formation of the device gate structure 170.
In this embodiment, the process of removing the gate structure 104 includes a dry etching process.
Specifically, the removal of sacrificial layer 1021 provides a spatial location for the subsequent formation of device gate structure 170.
In this embodiment, a wet etching process is used to remove the sacrificial layer 1021.
The sacrificial layer 1021 is removed after the source-drain doped layer 196 is formed, so that after the sacrificial layer 1021 is removed, two ends of the channel layer 1022 are connected with the source-drain doped layer 196 along the extending direction of the protruding portion 101 and suspended in the gate opening 199, thereby providing a foundation for the device gate structure 170 to surround the channel layer 1022.
After the sacrificial layer 1021 is removed, the channel layers 1022 are disposed at intervals, and the remaining channel layers 1022 constitute a channel structure layer (not shown) that is disposed on the protruding portion 101 and is disposed at intervals from the protruding portion 101.
The device gate structure 170 is used to control the opening and closing of the conduction channel when the device is in operation.
Specifically, the device gate structure 170 is the metal gate structure 104.
In this embodiment, the device gate structure 170 includes a gate dielectric layer (not shown) overlying the conformal blanket channel layer 1022, and a gate electrode layer (not shown) overlying the gate dielectric layer.
In this embodiment, the gate dielectric layer comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following.
Specifically, the gate dielectric layer includes a gate oxide layer conformally covering a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 1022, and a high-k gate dielectric layer conformally covering the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, and the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
The gate electrode layer is used for subsequent electrical connection with an external structure. The material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC. Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may include only the work function layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (19)
1. A semiconductor structure, comprising:
a substrate;
a channel structure layer suspended on top of the substrate, the channel structure layer including one or more channel layers spaced apart in a longitudinal direction;
a device gate structure on the substrate and crossing the channel structure layer, wherein the device gate structure covers part of the top, part of the side wall and part of the bottom of the channel layer, and the side wall of the device gate structure right below the channel layer is retracted inwards relative to the side wall of the channel layer along the direction parallel to the substrate and perpendicular to the extending direction of the device gate structure;
the source-drain doped layers are positioned in the channel structure layers at two sides of the grid structure of the device;
the side wall layer is positioned on the side wall of the device grid structure;
the protective layer is positioned on the side wall of the side wall layer;
and the inner wall side wall layer is positioned between the side wall of the device grid structure right below the channel layer and the source-drain doped layer.
2. The semiconductor structure of claim 1, wherein the material of the protective layer comprises one or both of silicon oxide and silicon oxycarbide.
3. The semiconductor structure of claim 1, wherein the protective layer has a lateral dimension of 3 nm to 5 nm in a direction parallel to the substrate and perpendicular to an extension direction of the device gate structure.
4. The semiconductor structure of claim 1, wherein the material of the sidewall layer comprises one or more of silicon nitride, fluorine doped silicon oxide, and silicon oxynitride.
5. The semiconductor structure of claim 1, wherein the device gate structure comprises a gate dielectric layer conformally covering a portion of a top, a portion of a sidewall, and a portion of a bottom of the channel layer, and a gate electrode layer covering the gate dielectric layer;
the gate dielectric layer material comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La (La) 2 O 3 One or more of the following;
the material of the gate electrode layer includes one or more of TiN, taN, ta, ti, tiAl, W, al, tiSiN and TiAlC.
6. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein a channel laminated structure is formed on the top of the substrate, the channel laminated structure comprises one or more stacked channel laminated layers, each channel laminated layer comprises a sacrificial layer and a channel layer positioned on the sacrificial layer, a grid structure crossing the channel laminated structure is formed on the top of the substrate, and the grid structure covers part of the top and part of the side wall of the channel laminated structure;
Forming a side wall layer on the side wall of the grid structure;
forming a protective layer on the side wall of the side wall layer, wherein an etching selection ratio is arranged between the sacrificial layer and the protective layer;
after the protective layer is formed, forming grooves in the channel laminated structures at two sides of the grid structure, wherein the side walls of the grooves expose the channel laminated structures;
etching part of the sacrificial layer exposed out of the side wall of the groove transversely along the direction parallel to the substrate and perpendicular to the extending direction of the grid structure to form an inner groove, wherein the inner groove is surrounded by the adjacent channel layer and the rest of the sacrificial layer, or the inner groove is surrounded by the substrate, the channel layer adjacent to the substrate and the rest of the sacrificial layer;
forming an inner wall side wall layer in the inner groove;
and after the inner wall side wall layer is formed, forming a source-drain doping layer in the groove.
7. The method of claim 6, wherein the step of laterally etching the exposed portion of the sacrificial layer comprises an isotropic dry etching process.
8. The method of forming a semiconductor structure of claim 7, wherein the etching gas of the isotropic dry etching process comprises CF 4 、NF 3 And O 2 One or more of the following.
9. The method of claim 6, wherein an etch selectivity of the sacrificial layer to the protective layer is greater than an etch selectivity of the sacrificial layer to the sidewall layer during the lateral etching of the exposed portion of the recess sidewall.
10. The method of claim 6, wherein during the step of laterally etching the exposed portion of the sacrificial layer on the sidewall of the recess, an etching selectivity between the sacrificial layer and the channel layer is greater than 6:1, a step of;
the etching selectivity ratio of the sacrificial layer to the protective layer is greater than 20:1.
11. the method of forming a semiconductor structure of claim 6, wherein forming said sidewall layer comprises: forming a side wall material layer on the top and the side wall of the grid structure and the top of the channel laminated structure exposed by the grid structure; and removing the side wall material layer at the top of the grid structure and the side wall material layer at the top of the channel laminated structure, and taking the remaining side wall material layer positioned on the side wall of the grid structure as the side wall layer.
12. The method of forming a semiconductor structure of claim 6, wherein the step of forming the protective layer comprises: forming a protective material layer on the top of the gate structure, the side wall of the side wall layer and the top of the channel laminated structure exposed by the gate structure; and removing the protective material layer at the top of the grid electrode structure and the protective material layer at the top of the channel laminated structure, and taking the remaining protective material layer positioned on the side wall of the side wall layer as the protective layer.
13. The method of forming a semiconductor structure of claim 12, wherein the process of forming the protective material layer comprises an atomic layer deposition process.
14. The method of forming a semiconductor structure of claim 12, wherein the process of removing the protective material layer on top of the gate structure and the protective material layer on top of the channel stack structure comprises a plasma dry etch process.
15. The method of forming a semiconductor structure of claim 6, wherein after forming the protective layer and before forming the recess, the method of forming a semiconductor structure further comprises: forming a compensation layer on the side wall of the protection layer;
and removing the compensation layer in the process of transversely etching the part of the sacrificial layer exposed out of the side wall of the groove.
16. The method of forming a semiconductor structure of claim 15, wherein the step of forming the compensation layer comprises: forming a compensation material layer on the side wall of the protection layer, the top of the gate structure and the top of the channel laminated structure exposed by the gate structure; and removing the compensation material layers at the top of the gate structure and the top of the channel laminated structure, and taking the rest compensation material layers positioned on the side walls of the gate structure as the compensation layers.
17. The method of forming a semiconductor structure of claim 15, wherein the material of the compensation layer comprises one or more of silicon nitride, silicon oxide, and silicon oxycarbide.
18. The method of claim 15, wherein the lateral dimension of the compensation layer is 3 nm to 7 nm in a direction parallel to the substrate and perpendicular to the extending direction of the gate structure.
19. The method of claim 6, wherein the protective layer has a lateral dimension of 3 nm to 5 nm in a direction parallel to the substrate and perpendicular to the extending direction of the gate structure.
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