CN115394719A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN115394719A
CN115394719A CN202110569594.8A CN202110569594A CN115394719A CN 115394719 A CN115394719 A CN 115394719A CN 202110569594 A CN202110569594 A CN 202110569594A CN 115394719 A CN115394719 A CN 115394719A
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China
Prior art keywords
region
layer
substrate
channel
dielectric wall
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CN202110569594.8A
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Chinese (zh)
Inventor
张海洋
柯星
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202110569594.8A priority Critical patent/CN115394719A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A structure of a semiconductor and a forming method thereof are provided, the method comprises the following steps: forming bottom side wall material layers conformally covering the channel lamination and the substrate, wherein the bottom side wall material layers positioned on the opposite side walls of the isolation groove are in contact; removing the side wall material layers positioned at the top of the substrate and the top of the channel lamination and the side wall material layer with partial thickness in the isolation groove, and forming a bottom dielectric wall in partial space of the isolation groove, wherein the top surface of the bottom dielectric wall is higher than the top surface of the channel lamination; after the bottom dielectric wall is formed, a top dielectric wall is formed in the remaining space of the isolation trench to cover a top of the bottom dielectric wall, the top of the top dielectric wall being flush with a top of the channel stack, the top dielectric wall and the bottom dielectric wall forming the dielectric wall. The dielectric wall reduces the probability of electric leakage generated between devices which are formed in the first area and the second area subsequently, and is beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, and the trend of semiconductor transistors toward higher element density and higher integration, the trend of semiconductor process nodes following moore's law is decreasing. Transistors are currently being widely used as the most basic semiconductor transistors, and therefore, as the element density and integration of semiconductor transistors increase, the channel length of the transistors has to be shortened in order to accommodate the reduction of process nodes.
In order to better meet the requirement of scaling down the transistor size, semiconductor processes are gradually starting to transition from planar transistors to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets), gate-all-around (GAA) transistors, and the like. Wherein the fully-wrapped-around gate transistor comprises a vertical fully-wrapped-around gate transistor and a horizontal fully-wrapped-around gate transistor. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel and can better inhibit a short-channel effect.
With the further reduction of the device size, how to achieve a better electrical isolation effect between the NMOS device having the fully-wrapped-around gate structure and the PMOS device having the fully-wrapped-around gate structure has higher difficulty and challenge.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which are beneficial to further improving the performance of the semiconductor structure.
To solve the above problems, the present invention provides a semiconductor structure, comprising: the semiconductor device comprises a substrate, a first isolation region, a second isolation region and a plurality of fins, wherein the substrate comprises discrete device regions and the isolation regions positioned between the device regions, the device regions comprise a first region and a second region which are spaced, and the substrate comprises a substrate and the fins which are respectively raised on the substrate of the first region and the substrate of the second region; the channel structure layer is suspended on the top of the fin part of the device region and comprises one or more channel layers arranged at intervals along the normal direction of the surface of the substrate; the isolation layer is positioned on the substrate of the isolation region and exposes the side wall of the channel structure layer; the dielectric walls are positioned on the substrate at the junction of the first area and the second area and cover the side walls of the channel structure layer, and each dielectric wall comprises a bottom dielectric wall and a top dielectric wall positioned at the top of the bottom dielectric wall; the gate dielectric layer covers part of the top, part of the side wall and part of the bottom of the channel structure layer; and the gate electrode layer is positioned on the substrate and stretches across the channel structure layer and the dielectric wall, and the gate electrode layer surrounds and covers the gate dielectric layer.
Correspondingly, the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate comprises a discrete device region, the device region comprises a first region and a second region which are adjacent to each other, the substrate comprises a substrate and a fin portion which is respectively raised on the substrate of the first region and the second region, a channel laminated structure is formed on the fin portion, the channel laminated structure comprises one or more channel laminated layers which are longitudinally stacked, each channel laminated layer comprises a sacrificial layer and a channel layer which is positioned on the sacrificial layer, and in the device region, the substrate at the junction of the first region and the second region, the channel laminated layers, the fin portion and the first region and the second region which are adjacent to each other, enclose an isolation groove; forming a bottom side wall material layer conformally covering the channel laminated structure and the substrate, wherein the bottom side wall material layers positioned on the opposite side walls of the isolation groove are in contact; removing the side wall material layers positioned at the top of the substrate and the top of the channel laminated structure and the side wall material layer with partial thickness in the isolation groove, and forming a bottom dielectric wall in partial space of the isolation groove, wherein the top surface of the bottom dielectric wall is higher than the top surface of the channel laminated structure; after the bottom dielectric wall is formed, a top dielectric wall covering the top of the bottom dielectric wall is formed in the residual space of the isolation groove, the top of the top dielectric wall is flush with the top of the channel laminated structure, and the top dielectric wall and the bottom dielectric wall form the dielectric wall.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a semiconductor structure, wherein a dielectric wall is positioned on a substrate at the junction of a first area and a second area and covers the side wall of a channel structure layer, and the dielectric wall comprises a bottom dielectric wall and a top dielectric wall positioned at the top of the bottom dielectric wall; the gate dielectric layer conformally covers part of the top, part of the side wall and part of the bottom of the channel structure layer; the gate electrode layer is located on the substrate and stretches across the channel structure layer and the dielectric wall, and the gate electrode layer covers the gate dielectric layer in a surrounding mode. Compared with the scheme that the dielectric wall of the integrated structure is formed at the junction of the first region and the second region of the device region at present, the dielectric wall of the embodiment of the invention comprises the bottom dielectric wall and the top dielectric wall positioned at the top of the bottom dielectric wall, so that the top dielectric wall can fill a gap formed by the bottom dielectric wall and the channel structure layer, the flatness of the top surface of the dielectric wall is high, the dielectric wall can completely cover the side wall of the channel structure layer, the dielectric wall can better isolate the adjacent channel structure layers of the first region and the second region in the device region, the probability of electric leakage generated between devices of the first region and the second region formed subsequently is reduced, and the performance of the semiconductor structure is improved.
The embodiment of the invention provides a method for forming a semiconductor structure, wherein a bottom dielectric wall is formed in a part of space of an isolation groove, and the top surface of the bottom dielectric wall is lower than that of a channel laminated structure; after the bottom dielectric wall is formed, a top dielectric wall covering the top of the bottom dielectric wall is formed in the residual space of the isolation groove, the top dielectric wall and the bottom dielectric wall form a dielectric wall, and the top of the top dielectric wall is flush with the top of the channel laminated structure. Compared with the existing scheme of forming the dielectric wall with the integrated structure in the isolation groove, the embodiment of the invention firstly removes a part of thickness of the side wall material layer in the isolation groove, forms the bottom dielectric wall in a part of space of the isolation groove to reserve a residual space of the isolation groove, and forms the top dielectric wall in the residual space of the isolation groove, wherein the bottom dielectric wall and the top dielectric wall form the dielectric wall, the top of the top dielectric wall is flush with the top of the channel laminated structure, and the top dielectric wall fills a gap formed by the side wall of the channel laminated structure and the bottom dielectric wall, so that the flatness of the top surfaces of the dielectric wall and the channel laminated structure is high, the dielectric wall can be ensured to completely cover the side wall of the channel laminated structure, the dielectric wall can better isolate the adjacent channel laminated structure of the first region and the second region in the device region, the probability of electric leakage generated between devices subsequently formed in the first region and the second region is reduced, and the performance of the semiconductor structure is improved.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
FIG. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 5 to fig. 16 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The performance of semiconductor structures currently needs to be improved. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure.
Fig. 1 to fig. 3 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate includes discrete device regions 10A and isolation regions 10B located between the device regions 10A, the device regions 10A include adjacent first regions a and second regions B, the substrate includes a substrate 10 and fins 11 protruding from the substrate 10 in the first regions a and the second regions B, one or more longitudinally stacked channel stacks 14 are formed on the fins 11, each channel stack 14 includes a sacrificial layer 12 and a channel layer 13 located on the sacrificial layer 12, an isolation layer 17 is formed on the substrate 10 exposed by the channel stack 14, and in the device regions 10A, sidewalls of adjacent channel stacks 14 and tops of the isolation layers 17 enclose isolation grooves 15.
Referring to fig. 2, a dielectric material layer 18 is formed conformally covering the channel stack and the isolation layer, the dielectric material layer 18 also filling the isolation trenches 15 of the device region 10A.
Referring to fig. 3, the dielectric material layer 18 on top of the isolation layer 17 of the isolation region 10B and on top of the channel stack 14 is removed, and a dielectric wall 18 is formed in the isolation trench 15 at the intersection of the first region a and the second region B.
A first region a of the device region 10A is used to form NMOS transistors and a second region B of the device region 10A is used to form PMOS transistors.
It is found through research that, in the process of forming the dielectric wall 18, in order to completely remove the dielectric material layer 18 on the top of the isolation layer 17 and the top of the channel stack 14 of the isolation region 10B, the dielectric material layer 18 in the isolation groove 15 is prone to over-etching (as shown by a dashed circle in fig. 3), which tends to result in poor flatness between the top of the dielectric wall 18 and the top of the channel stack 14, that is, the dielectric wall 18 exposes a part of the sidewall of the channel stack 14, thereby reducing the isolation effect of the dielectric wall 18 on the adjacent channel stacks 14 in the device region 10A, and accordingly, increasing the probability of electric leakage between devices subsequently formed in the first region a and the second region B, and further affecting the performance of the semiconductor structure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a discrete device region, the device region comprises a first region and a second region which are adjacent, the substrate comprises a substrate and a fin part which is respectively raised on the substrate of the first region and the second region, a channel laminated structure is formed on the fin part, the channel laminated structure comprises one or more channel laminated layers which are longitudinally stacked, each channel laminated layer comprises a sacrificial layer and a channel layer which is positioned on the sacrificial layer, and in the device region, the adjacent channel laminated layers of the first region and the second region, the fin part and the substrate at the junction of the first region and the second region enclose an isolation groove; forming bottom sidewall material layers conformally covering the channel laminated structure and the substrate, wherein the bottom sidewall material layers positioned on the opposite side walls of the isolation groove are contacted; removing the side wall material layers positioned at the top of the substrate and the top of the channel laminated structure and the side wall material layer with partial thickness in the isolation groove, and forming a bottom dielectric wall in partial space of the isolation groove, wherein the top surface of the bottom dielectric wall is lower than that of the channel laminated structure; after the bottom dielectric wall is formed, a top dielectric wall is formed in the remaining space of the isolation trench to cover the top of the bottom dielectric wall, the top of the top dielectric wall is flush with the top of the channel stack structure, and the top dielectric wall and the bottom dielectric wall constitute the dielectric wall.
The dielectric wall comprises a bottom dielectric wall and a top dielectric wall positioned at the top of the bottom dielectric wall, so that the top dielectric wall can fill a gap formed by the bottom dielectric wall and a channel structure layer, the flatness of the top surface of the dielectric wall is high, the dielectric wall can be ensured to completely cover the side wall of the channel structure layer, the dielectric wall can better isolate adjacent channel structure layers of a first area and a second area in a device area, the probability of electric leakage generated between devices of the first area and the second area formed subsequently is reduced, and the performance of a semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
FIG. 4 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: the substrate comprises a discrete device region 200A and an isolation region 200B positioned between the device regions 200A, wherein the device region 200A comprises a first region c and a second region d which are spaced, the substrate comprises a substrate 200 and a fin portion 201 which is raised on the substrate 200 of the first region c and the second region d respectively; the channel structure layer 290 is suspended on the top of the fin portion 201 of the device region 200A, and the channel structure layer 290 comprises one or more channel layers 203 arranged at intervals along the surface normal direction of the substrate 200; an isolation layer 217 on the substrate 200 of the isolation region 200B and exposing sidewalls of the channel structure layer 290; a dielectric wall 216 located on the substrate 200 at the boundary of the first region c and the second region d and covering the sidewall of the channel structure layer 290, the dielectric wall 216 including a bottom dielectric wall 212 and a top dielectric wall 215 located on top of the bottom dielectric wall 212; a gate dielectric layer 222, wherein the gate dielectric layer 222 covers a part of the top, a part of the sidewall and a part of the bottom of the channel structure layer 290; and a gate electrode layer 223 on the substrate and crossing the channel structure layer 290 and the dielectric wall 216, wherein the gate electrode layer 223 surrounds the gate dielectric layer 222.
The dielectric wall 216 of the present embodiment includes the bottom dielectric wall 212 and the top dielectric wall 215 located at the top of the bottom dielectric wall 212, and therefore, the top dielectric wall 215 can fill a gap defined by the sidewalls of the bottom dielectric wall 212 and the channel structure layer 290, so that the flatness of the top surface of the dielectric wall 216 is high, which is beneficial to ensuring that the dielectric wall 216 can completely cover the sidewall of the channel structure layer 290, and thus the dielectric wall 216 can better isolate the adjacent channel structure layer 290 of the first region c and the second region d in the device region 200A, thereby reducing the probability of leakage generated between devices subsequently formed in the first region c and the second region d, and being beneficial to improving the performance of the semiconductor structure.
In this embodiment, the first region c of the device region 200A is used to form a first type transistor, the second region d of the device region 200A is used to form a second type transistor, and the channel conductivity types of the first type transistor and the second type transistor are different. Specifically, the first type transistor is an NMOS transistor, and the second type transistor is a PMOS transistor; in other embodiments, the first type transistor is a PMOS transistor and the second type transistor is an NMOS transistor.
In this embodiment, the substrate further includes isolation regions 200B located between the device regions 200A.
The isolation region 200B serves to electrically isolate adjacent device regions 200A.
In this embodiment, the base is a three-dimensional structure, and includes a substrate 200 and a fin 201 protruding from the substrate 200 in the first region c and the second region d. In other embodiments, the base may be a planar substrate. In this embodiment, the substrate 200 is a silicon substrate, the fin portion 201 and the substrate 200 are made of the same material, and the fin portion 201 is made of silicon.
In this embodiment, the top of the substrate 200 at the boundary between the first region c and the second region d is lower than the top of the substrate 200 of the isolation region 200B.
In order to improve the electrical isolation effect of the dielectric wall 216 between the well region in the base of the first region c and the well region in the base of the second region d, and to satisfy the electrical isolation effect between the first region c and the second region d, the top of the substrate 200 at the boundary between the first region c and the second region d is lower than the top of the substrate 200 of the isolation region 200B.
It should be noted that the distance h1 from the top of the substrate 200 at the boundary between the first region c and the second region d to the top of the substrate 200 of the isolation region 200B should not be too large, nor too small. If the distance h1 from the top of the substrate 200 at the junction of the first region c and the second region d to the top of the substrate 200 of the isolation region 200B is too large, the filling performance of the bottom dielectric wall 212 on the substrate 200 at the junction of the first region c and the second region d is poor under the condition that the isolation layer 217 in the isolation region 200B satisfies the isolation effect, which easily causes the reduction of the isolation effect of the bottom dielectric wall, thereby affecting the performance of the semiconductor structure; if the distance h1 from the top of the substrate 200 at the junction of the first region c and the second region d to the top of the substrate 200 of the isolation region 200B is too small, the electrical isolation effect between the dielectric wall on the substrate 200 at the junction of the first region c and the second region d to the well region in the base of the first region c and the well region in the base of the second region d is deteriorated under the condition that the isolation layer 217 in the isolation region 200B satisfies the isolation effect, thereby affecting the performance of the semiconductor structure; for this reason, in the present embodiment, a distance h1 from the top of the substrate 200 at the boundary between the first region c and the second region d to the top of the substrate 200 of the isolation region 200B is 50 to 300 angstroms.
In this embodiment, the channel structure layer 290 is suspended on the top of the fin 201 of the device region 200A, and the channel structure layer 290 includes one or more channel layers 203 arranged at intervals along the surface normal direction of the substrate 200. In this embodiment, the channel layer 203 is used to provide a conduction channel for the first type transistor and the second type transistor.
In this embodiment, the material of the channel layer 203 includes one or more of silicon, silicon germanium, and a group iii-v semiconductor material. Wherein the material of the channel layer 203 of the first region c is determined according to the performance of the first type transistor, and the material of the channel layer 203 of the second region c is determined according to the performance of the second type transistor.
In the present embodiment, the number of channel layers 203 is three. In other embodiments, the number of channel layers may also be other numbers.
In this embodiment, the semiconductor structure further includes: an isolation layer 217 is formed on the substrate 200 of the isolation region 200B and exposes sidewalls of the channel structure layer 290. The isolation layer 217 serves to isolate the adjacent device region 200A. To this end, the material of the isolation layer 217 is a dielectric material, and the material of the isolation layer 217 may include silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation layer 217 is made of silicon oxide.
The dielectric wall 216 is used to isolate the first region c and the second region d in the same device region 200A. In order to improve the isolation effect of the dielectric wall 216 on the channel structure layer 290 in the first region c and the second region d, the top of the dielectric wall 216 is higher than the top of the channel structure layer 290.
In this embodiment, the dielectric walls 216 include bottom dielectric walls 212 and top dielectric walls 215 located on top of the bottom dielectric walls 212.
In this embodiment, the top of the bottom dielectric wall 212 is higher than the top of the channel structure layer 290. The top of the bottom dielectric wall 212 is higher than the top of the channel structure layer 290, so that the insulation between the channel structure layers 290 is uniform.
In this embodiment, the bottom dielectric wall 212 is made of a dielectric material, for example, including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride and silicon carbonitride, so as to ensure that the bottom dielectric wall 212 can perform the isolation function. In this embodiment, the bottom dielectric wall 212 is made of silicon nitride.
It should be noted that the distance from the top of the bottom dielectric wall 212 to the top of the channel structure layer 290 should not be too large or too small. If the distance from the top of the bottom dielectric wall 212 to the top of the channel structure layer 290 is too large, the spatial position of the bottom dielectric wall 215 is too small, and the filling effect of the bottom dielectric wall 215 and the isolation effect of the dielectric wall 216 are affected during the formation process of the bottom dielectric wall 215, so that the probability of generating a leakage between the devices in the first region c and the second region d is increased; if the distance from the top of the bottom dielectric wall 212 to the top of the channel structure layer 290 is too small, the insulation between the bottom dielectric wall 212 and the channel structure layer 290 is not uniform, which affects the performance of the semiconductor structure. For this reason, in the present embodiment, the distance h2 from the top of the bottom dielectric wall 212 to the top of the channel structure layer 290 is 5 nm to 20 nm.
It should be noted that, in order to reduce the process steps and save the cost, the isolation layer 217 is formed in the isolation region 200B during the process of forming the top dielectric wall 215, and therefore, the material of the top dielectric wall 215 is the same as that of the isolation layer 217. Therefore, in the present embodiment, the material of the top dielectric wall 215 is silicon oxide.
In this embodiment, the gate dielectric layer 222 conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel layer 203. In this embodiment, the gate dielectric layer 222 is made of HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a).
In particular, the gate dielectric layer 222 includes a gate oxide layer conformally covering a portion of the top, a portion of the sidewalls, and a portion of the bottom of the channel structure layer 290, and a high-k gate dielectric layer conformally covering the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, and the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
It should be noted that the gate dielectric layer 222 also conformally covers a portion of the top of the isolation layer 217 and a portion of the sidewalls and a portion of the top of the exposed dielectric wall 216 of the channel layer 203.
In this embodiment, the gate electrode layer 223 is disposed on the substrate and crosses the channel structure layer 290 and the dielectric wall 216, and the gate electrode layer 223 surrounds and covers the gate dielectric layer 222. The gate electrode layer 223 is used for subsequent electrical connection to external structures. The material of the gate electrode layer 223 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC. Specifically, the gate electrode layer 223 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 223 may include only the work function layer.
In this embodiment, the semiconductor structure further includes: and the side walls 220 are positioned on the side walls of the gate electrode layer 223. The sidewall spacers are used to protect sidewalls of the gate electrode layer 223. The sidewall spacers 220 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall spacers 220 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacer 220 has a single-layer structure, and the material of the sidewall spacer 220 is silicon nitride.
In this embodiment, the semiconductor structure further includes: and the interlayer dielectric layer 219 is positioned on the gate electrode layer 223 and the top of the isolation layer 217 exposed by the sidewall spacers 220, and the interlayer dielectric layer 219 covers the sidewalls of the sidewall spacers 220. The interlevel dielectric layer 219 serves to isolate adjacent devices. The material of the interlayer dielectric layer 219 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 219 is made of silicon oxide.
Fig. 5 to 16 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 5 to 6, a substrate is provided, the substrate includes a discrete device region 100A, the device region 100A includes a first region a and a second region b which are adjacent to each other, the substrate includes a substrate 100 and a fin 101 protruding from the substrate 100 of the first region a and the second region b, the fin 101 has a channel stack structure 301 formed thereon, the channel stack structure 301 includes one or more channel stacks 104 which are stacked longitudinally, each channel stack 104 includes a sacrificial layer 102 and a channel layer 103 on the sacrificial layer 102, and in the device region 100A, the adjacent channel stack 104 of the first region a and the second region b, the fin 101, and the substrate 100 at a boundary of the first region a and the second region b enclose an isolation trench 109.
The substrate is used to provide a process platform for subsequent process.
In this embodiment, the first region a of the device region 100A is used to form a first type transistor, the second region b of the device region 100A is used to form a second type transistor, and the channel conductivity types of the first type transistor and the second type transistor are different. Specifically, the first type transistor is an NMOS transistor, and the second type transistor is a PMOS transistor; in other embodiments, the first type transistors are PMOS transistors and the second type transistors are NMOS transistors.
In this embodiment, the substrate further includes an isolation region 100B located between the device regions 100A. The isolation region 100B serves to electrically isolate adjacent device regions 100A.
In the present embodiment, the adjacent channel stack 104 closest to the isolation region 100B and the fin 101 and the remaining base of the isolation region 100B enclose an isolation opening 110, and the bottom of the isolation trench 109 is lower than the bottom of the isolation opening 110.
The isolation trench 109 provides a spatial location for the subsequent formation of dielectric walls.
In order to improve the electrical isolation effect between the dielectric wall and the well region in the first region a substrate and the well region in the second region b substrate, and satisfy the electrical isolation effect between the first region a and the second region b, the bottom of the isolation trench 109 is lower than the bottom of the isolation opening 110.
In this embodiment, the step of forming the substrate and channel stack 104 includes: as shown in fig. 5, providing an initial substrate 190, the initial substrate 190 including a discrete device region 100A, the device region 100A including a first region a and a second region b adjacent to each other, the initial substrate 190 having one or more longitudinally stacked channel material stacks 180 formed thereon, each channel material stack 180 including a sacrificial material layer 179 and a channel material layer 178 on the sacrificial material layer 179; as shown in fig. 6, an initial substrate 190 and a channel material stack 180 on the initial substrate 190 are patterned, the initial substrate 190 is patterned into a substrate including a substrate 100 and a fin 101 protruding from the substrate 100 in a first region a and a second region b, respectively, and the channel material stack 180 is patterned into a channel stack 104 on the fin 101.
In this embodiment, the channel stack layer 104 and the isolation trench 109 are formed in the same step, which reduces the number of process steps and the process cost.
In this embodiment, the base is a three-dimensional structure, and includes a substrate 100 and a fin 101 protruding from the substrate 100 in the first region a and the second region b. In other embodiments, the base may be a planar substrate.
In this embodiment, the substrate 100 is a silicon substrate, the fin portion 101 and the substrate 100 are made of the same material, and the fin portion 101 is made of silicon.
Accordingly, in this embodiment, the channel stack structure 301 is formed on the fin 101, and the channel stack structure 301 includes one or more channel stacks 104 stacked longitudinally.
In this embodiment, the material of the sacrificial layer 102 includes silicon germanium; the material of the channel layer 103 includes silicon, silicon germanium, or a iii-v semiconductor material, and there is an etch selectivity between the sacrificial layer 102 and the channel layer 103.
The channel stack 104 extends in the same direction as the fin 101. The stacking direction of the plurality of channel stacks 104 is perpendicular to the surface of the substrate 100.
The channel stack 104 provides a process foundation for the subsequent formation of spaced apart channel layers.
As an example, the number of channel stacks 104 is three. In other embodiments, the number of channel stacks may be other numbers.
In this embodiment, the channel layer 103 in the first region a is used to provide a conductive channel of a first-type transistor, the sacrificial layer 102 is used to support the channel layer 103, after the sacrificial layer 102 in the first region a is subsequently removed, the channel layer 103 can be arranged in a suspended manner at intervals, and the sacrificial layer 102 in the first region a occupies a space for forming a gate dielectric layer and a gate electrode layer subsequently.
In this embodiment, the channel layer 103 in the second region b is used to provide a conductive channel of the second type transistor, the sacrificial layer 102 is used to support the channel layer 103, after the sacrificial layer 102 in the second region b is subsequently removed, the channel layer 103 can be spaced and suspended, and the sacrificial layer 102 in the second region b occupies a space for subsequently forming a gate dielectric layer and a gate electrode layer.
In the present embodiment, in the step of providing the substrate, the number of the sacrificial layers 102 and the channel layers 103 is the same.
With continued reference to fig. 5-6, the step of patterning the initial substrate 190 and the channel material stack 180 on the initial substrate 190 includes: forming a core layer 106 on top of the channel material stack 180, the core layer 106 having a mask opening 108 formed therein at a boundary of the first region a and the second region b; forming a discrete second mask layer 107 on top of the core layer 106 in the first region a and the second region B, wherein the second mask layer 107 exposes the top of the core layer 106 in the isolation region 100B; the core layer 106, the channel material stack 180 and a partial thickness of the initial substrate 190 are etched using the second mask layer 107 as a mask.
It should be noted that the core layer 106 is formed with the mask opening 108 at the boundary between the first region a and the second region b, so that the channel material stack 180 at the boundary between the first region a and the second region b is etched in advance compared with the rest of the regions, and accordingly, the etching depth of the initial substrate 190 at the boundary between the first region a and the second region b is greater at the same etching time, thereby facilitating to make the bottom of the isolation trench 109 lower than the bottom of the isolation opening 110 during the process of forming the isolation trench 109 and the isolation opening 110.
In this embodiment, the sacrificial layer 102 in the channel stack layer 104 is used as the first sacrificial layer 102, and the channel stack layer structure 301 further includes a second sacrificial layer 300 located on top of the topmost channel stack layer 104.
The second sacrificial layer 300 is used to occupy a spatial position for a subsequent increase in the height of the gate electrode layer to be formed.
Therefore, as shown in fig. 5, with the sacrificial material layer 179 in the channel material stack 180 as the first sacrificial material layer 179, before patterning the initial substrate 190 and the channel material stack 180 on the initial substrate 190, further includes: a second sacrificial material layer 500 is formed on top of the topmost channel material stack 180.
Accordingly, in forming the substrate and channel stack 104, the second sacrificial material layer 500, the channel material stack 180, and the initial substrate 190 are patterned in sequence, and the second sacrificial material layer 500 is patterned into the second sacrificial layer 300. The second sacrificial layer 300 and the channel stack 104 constitute a channel stack structure 301.
In this embodiment, the material of the first sacrificial layer 102 is the same as the material of the second sacrificial layer 300, so that the material can be removed in the same step.
In this embodiment, the forming method further includes: a hard mask layer 105 is formed on top of the channel material stack 180 and a core layer 107 is correspondingly formed on the hard mask layer 105. Specifically, the hard mask layer 105 is formed on top of the second sacrificial material layer 500.
The patterned hard mask layer 105 is used as a mask for etching the second sacrificial material layer 500 and the channel material stack 180. In which, by transferring the pattern into the hard mask layer 105 first, it is advantageous to improve the accuracy of pattern transfer.
In this embodiment, the material of the hard mask layer 105 includes one or more of silicon nitride, silicon carbide, and silicon carbide nitride.
Referring to fig. 7, a conformal channel-covering stack 301 is formed in contact with the bottom sidewall material layer 111 of the substrate on the opposite sidewalls of the isolation trench 109.
The bottom sidewall material layer 111 provides a process foundation for the subsequent formation of the bottom dielectric wall.
In this embodiment, the process of forming the bottom sidewall material layer 111 includes an atomic layer deposition process.
The atomic layer deposition process comprises multiple atomic layer deposition cycles, has good step coverage characteristics, is beneficial to improving the thickness uniformity of the bottom side wall material layer 111, and enables the bottom side wall material layer 111 to conformally cover the channel lamination layer 104 and the substrate.
It should be noted that, the subsequently formed bottom dielectric wall is obtained by patterning the bottom side wall material layer 111, and in order to ensure the electrical isolation effect between the adjacent first region a and the second region b, the material of the bottom side wall material layer 111 is a dielectric material, for example, including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride and silicon carbonitride, so as to ensure that the subsequently formed bottom dielectric wall can play a role in isolation. In this embodiment, the bottom sidewall material layer 111 is made of silicon nitride.
Referring to fig. 8, the sidewall material layer 111 on the top of the substrate and on the top of the channel stack structure 301 and a part of the thickness of the sidewall material layer 111 in the isolation trench 109 are removed, and a bottom dielectric wall 112 is formed in a part of the space of the isolation trench 109, wherein a top surface of the bottom dielectric wall 112 is lower than a top surface of the channel stack 104.
In order to form the gate electrode layer crossing the channel structure layer and the dielectric wall in the following step, the sidewall material layer 111 on the top of the substrate and on the top of the channel stack structure 301 needs to be removed completely, i.e., a space is provided for forming the gate electrode layer in the following step.
The spacer material layer 111 is removed to a partial thickness in the isolation trench 109 to provide a space for forming a top dielectric wall on top of the bottom dielectric wall 112.
In this embodiment, the process of removing the sidewall material layer 111 located at the top of the substrate and the top of the channel stacked structure 301 and the sidewall material layer 111 with a partial thickness in the isolation trench 109 includes a dry etching process.
The dry etching process includes an anisotropic dry etching process having anisotropic etching characteristics. Namely, the longitudinal etching rate is greater than the transverse etching rate, so that the morphology quality of the side wall of the channel lamination layer 104 can be ensured while removing the side wall material layer 111 positioned at the top of the substrate and the top of the channel lamination layer 104 and the side wall material layer 111 with a part of thickness in the isolation groove 109, and a good process basis is provided for the subsequent process.
In this embodiment, the bottom dielectric wall 112 can isolate the channel stacks 104 of the first region a and the second region b, and meanwhile, the bottom dielectric wall 112 is also located between the fins 101 of the first region a and the second region b, and is also used for isolating the fins 101 of the first region a and the second region b, and can ensure that the channel stacks 104 of the first region a and the second region b can be completely isolated, so that the isolation effect of the bottom dielectric wall 112 on the adjacent channel stacks 104 of the first region a and the second region b is improved.
For this purpose, the material of the bottom dielectric wall 112 is a dielectric material, for example, including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride and silicon carbonitride, so as to ensure that the bottom dielectric wall 112 can perform the isolation function. In this embodiment, the bottom dielectric wall 112 is made of silicon nitride.
In this embodiment, after the bottom dielectric wall 112 is formed, the top of the bottom dielectric wall 112 is higher than the top of the channel stack 104. That is, the bottom dielectric wall 112 can penetrate through the channel stack, so that after the channel structure layer is formed subsequently, the insulation between the channel structure layers is uniform.
The distance from the top of the bottom dielectric wall 112 to the top of the channel stack 104 should not be too small, nor too large. If the distance from the top of the bottom dielectric wall 112 to the top of the channel stack 104 is too large, the space position of the subsequently formed top dielectric wall is easily occupied too much, the filling effect of the top dielectric wall is affected, the isolation effect of the subsequently formed dielectric wall is further affected, and the probability of electric leakage generated between devices in the first region and the second region is increased; if the distance from the top of the bottom dielectric wall 112 to the top of the channel stack 104 is too small, it is easy to cause non-uniform insulation between subsequently formed channel structure layers, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the distance from the top of the bottom dielectric wall 112 to the top of the channel stack 104 is 5 nm to 20 nm.
Referring to fig. 9 to 13, after the bottom dielectric wall 112 is formed, a top dielectric wall 115 covering the top of the bottom dielectric wall 112 is formed in the remaining space of the isolation trench 109, the top of the top dielectric wall 115 is flush with the top of the channel stack 301, and the top dielectric wall 115 and the bottom dielectric wall 112 constitute a dielectric wall 116.
In this embodiment, the sidewall material layer 111 with a partial thickness in the isolation trench 109 is removed first, the bottom dielectric wall 112 is formed in a partial space of the isolation trench 109 to reserve a remaining space of the isolation trench 109, and then the top dielectric wall 115 is formed in the remaining space of the isolation trench 109, the bottom dielectric wall 112 and the top dielectric wall 115 form the dielectric wall 116, and the top of the top dielectric wall 115 is flush with the top of the channel stacked structure 301, and the top dielectric wall 115 fills a gap surrounded by the sidewall of the channel stacked structure 301 and the bottom dielectric wall 112, so that the flatness of the top surfaces of the dielectric wall 116 and the channel stacked structure 301 is high, which is beneficial to ensuring that the dielectric wall 116 can completely cover the sidewall of the channel stacked structure 301, and thus the dielectric wall 116 can better isolate the adjacent channel stacked structure 301 of the first region a and the second region b in the device region 100A, thereby reducing the probability of leakage generated between devices subsequently formed in the first region a and the second region b, and being beneficial to improving the performance of the semiconductor structure.
In this embodiment, the step of forming the top dielectric wall 115 includes: as shown in fig. 9, a top sidewall material layer 113 covering the substrate and the channel stacked structure 301 is formed, and the top sidewall material layer 113 is further filled in the remaining space of the isolation trench 109; referring to fig. 10 to 13, the top sidewall material layer 113 is etched back, the top sidewall material layer 113 in the device region 100A above the top of the channel stack 301 is removed, a top dielectric wall 115 covering the top of the bottom dielectric wall 112 is formed in the remaining space of the isolation trench 109, the top of the top dielectric wall 115 is flush with the top of the channel stack 301, and the top dielectric wall 115 and the bottom dielectric wall 112 form a dielectric wall 116.
In this embodiment, the top dielectric wall 115 can isolate the channel stack structures 301 of the first region a and the second region b, and can ensure that the channel stack structures 301 of the first region a and the second region b can be completely isolated, so as to improve the isolation effect of the top dielectric wall 115 on the adjacent channel stack structures 301 of the first region a and the second region b.
For this purpose, the material of the top dielectric wall 115 is a dielectric material, for example, including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride and silicon carbonitride, so as to ensure that the top dielectric wall 115 can perform an isolation function. In this embodiment, the top dielectric wall 115 is made of silicon oxide.
In this embodiment, the process of forming the top sidewall material layer 113 covering the substrate and the channel stack structure 301 includes a chemical vapor deposition process.
The chemical vapor deposition process has the characteristics of high controllability, high utilization rate, good uniformity and the like.
In this embodiment, in the step of forming the top dielectric wall 115, the process of etching back the top sidewall material layer 113 includes a dry etching process.
The dry etching process includes an anisotropic dry etching process having anisotropic etching characteristics. Namely, the longitudinal etching rate is greater than the transverse etching rate, so that the morphology quality of the side wall of the channel lamination layer 104 can be ensured while the top side wall material layer 113 is etched back, and a good process basis is provided for the subsequent process.
Referring to fig. 10 to fig. 12, in the present embodiment, the step of etching back the top spacer material layer 113 includes: performing a first etch-back process on the top sidewall material layer 113 of the isolation region 100B, and removing the top sidewall material layer 113 with a preset thickness H in the isolation region 100B.
In this embodiment, the step of performing the first etching back process on the top sidewall material layer 113 of the isolation region 100B includes: as shown in fig. 10, a patterned first mask layer 114 is formed on the top of the top sidewall material layer 113, and the first mask layer 114 is located on the top of the top sidewall material layer 113 in the device region 100A; as shown in fig. 11, the top spacer material layer 113 with a predetermined thickness H in the isolation region 100B is etched by using the first mask layer 114 as a mask.
Performing a first etch-back process to reduce the effective height of the top sidewall material layer 113 in the isolation region 100B, which is beneficial to forming an isolation layer in the isolation region 100B while forming the top dielectric wall 115 in the remaining space of the isolation trench 109 in the subsequent step of performing a second etch-back process; moreover, the subsequent step of performing the second etching back process can use the top of the channel stack structure 301 as an etching stop position, so as to reduce the probability that the top sidewall material layer 113 located in the isolation trench 109 is over-etched in the second etching back process, thereby facilitating the improvement of the top surface flatness of the top dielectric wall 115.
It should be noted that the predetermined thickness H for removing the top sidewall material layer 113 in the isolation region 100B should not be too large, nor too small. If the preset thickness H for removing the top side wall material layer 113 in the isolation region 100B is too large, the remaining top side wall material layer 113 in the isolation region 100B is easily removed completely in the subsequent second etching process, or the thickness of the remaining top side wall material layer 113 in the isolation region 100B is too small, so that the isolation effect between adjacent device regions 100A is difficult to satisfy, and the performance of the semiconductor structure is further affected; if the preset thickness H for removing the top sidewall material layer 113 in the isolation region 100B is too small, in the subsequent second etching process, the isolation layer in the isolation region 100B may not completely expose the sidewall of the channel stack 104 under the condition that the top dielectric wall 115 formed in the remaining space of the isolation trench 109 meets the process requirement, thereby affecting the performance of the semiconductor structure. Therefore, in the present embodiment, in the step of performing the first etching back process, the predetermined thickness H of the top sidewall material layer 113 in the isolation region 100B is removed to be 50 to 300 angstroms.
In this embodiment, in the step of performing the first etching back process, the process of etching the top sidewall material layer 113 of the isolation region 100B by using the first mask layer 114 as a mask includes a dry etching process.
The dry etching process comprises an anisotropic dry etching process, and the anisotropic dry etching process has anisotropic etching characteristics. Namely, the longitudinal etching rate is greater than the lateral etching rate, so that the profile quality of the side wall of the channel stack layer 104 can be ensured while the top side wall material layer 113 of the isolation region 100B is etched back, and a good process basis is provided for the subsequent process.
It should be further noted that, after the first etching back process is performed, the method further includes: the first mask layer 114 is removed.
Referring to fig. 12 to 13, after the first etch back process, a second etch back process is performed on the remaining top spacer material layer 113 in the isolation region 100B and the device region 100A with the top of the channel stack 104 as an etch stop position, so as to form a top dielectric wall 115 in the isolation trench 109 and an isolation layer 117 on the substrate 100 of the isolation region 100B.
The top dielectric walls 115 occupy the remaining space of the isolation trench 109, i.e. the top of the top dielectric walls 115 is flush with the top of the channel stack 104, so that the flatness of the top surfaces of the dielectric walls 116 and the channel stack 104 is high, which is beneficial to ensure that the dielectric walls 116 can completely cover the sidewalls of the channel stack 104, thereby enabling the dielectric walls 116 to better isolate the adjacent channel stacks 104 of the first region a and the second region b in the device region 100A.
Isolation layer 117 located on isolation region 100B substrate 100 isolates adjacent device region 100A.
Referring to fig. 14, the forming method further includes: a dummy gate 118 is formed across the channel stack 104 and the dielectric walls 116, the dummy gate 118 covering a portion of the top and a portion of the sidewalls of the channel stack 104.
The dummy gate 118 occupies a spatial location for subsequently formed gate structures.
In the present embodiment, the dummy gate 118 crosses over the channel stack 104 and the dielectric wall 116, that is, the dummy gate 118 covers a portion of the top of the channel stack 104 and the dielectric wall 116, and a portion of the sidewall of the channel stack 104 opposite to the dielectric wall 116.
In this embodiment, the material of the dummy gate 118 includes polysilicon.
In this embodiment, after forming the dummy gate 118, the forming method further includes: and forming a side wall 120 on the side wall of the dummy gate 118.
The sidewall spacers 120 are used for protecting sidewalls of a subsequently formed gate structure. The sidewall 120 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 120 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 120 has a single-layer structure, and the material of the sidewall 120 is silicon nitride.
In this embodiment, after the forming of the sidewall spacers 120, the forming method further includes: source and drain doped layers (not shown) are formed in the channel stack 104 on either side of the dummy gate 118. The conductivity type of the doped ions in the source and drain doped layers is the same as the conductivity type of the channel of the transistor in the region, and detailed description of the source and drain doped layers is omitted here for the sake of brevity.
In this embodiment, the forming method further includes: an interlayer dielectric layer 119 is formed on the dummy gate 118 and the top of the isolation layer 117 exposed by the sidewall spacers 120, and the interlayer dielectric layer 119 covers the sidewalls of the sidewall spacers 120 and exposes the top of the dummy gate 118.
The interlevel dielectric layer 119 is used to isolate adjacent devices. The material of the interlayer dielectric layer 119 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 119 is made of silicon oxide.
Referring to fig. 15, the dummy gate 118 is removed, and a gate opening 121 is formed.
The gate opening 121 is used to provide a spatial location for a subsequently formed gate structure. Furthermore, after removing dummy gate 118, gate opening 121 exposes channel stack 104 for subsequent removal of sacrificial layer 102 through gate opening 121.
Specifically, the process of removing the dummy gate 118 includes one or both of a dry etching process and a wet etching process.
Referring to fig. 16, the first sacrificial layer 102 and the second sacrificial layer 300 exposed by the gate opening 121 are removed; after removing the sacrificial layer 102 exposed by the gate opening 121, forming a gate dielectric layer 122 in the gate opening 121, wherein the gate dielectric layer 122 conformally covers part of the top, part of the sidewall and part of the bottom of the channel layer 103, and the gate dielectric layer 122 also conformally covers the dielectric wall 116 exposed by the gate opening 121; after forming the gate dielectric layer 122, a gate electrode layer 123 is formed in the gate opening 121 across the channel layer 103 and the dielectric walls 116, the gate electrode layer 123 surrounding the gate dielectric layer 122, the gate dielectric layer 122 and the gate electrode layer 123 forming the gate structure 180.
Specifically, the gate structure 180 is used to control the conduction channels of the first-type and second-type transistors in the device region 100A to be turned on or off during device operation.
In this embodiment, the gate dielectric layer 122 includes HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a).
In particular, gate dielectric layer 122 includes a gate oxide layer conformally covering a portion of the top, a portion of the sidewalls, and a portion of the bottom of channel layer 103, and a high-k gate dielectric layer conformally covering the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, and the high-k dielectric material is a dielectric material with a relative dielectric constant larger than that of silicon oxide.
It should be noted that the gate dielectric layer 122 also conformally covers a portion of the top of the isolation layer 117 and a portion of the top and sidewalls of the dielectric wall 116 exposed by the channel layer 103.
The gate electrode layer 123 is used for subsequent electrical connection to external structures. The material of the gate electrode layer 123 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC. Specifically, the gate electrode layer 123 may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer 123 may include only the work function layer.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A semiconductor structure, comprising:
the substrate comprises discrete device regions and an isolation region positioned between the device regions, the device regions comprise a first region and a second region which are spaced, and the substrate comprises a substrate and a fin portion which is respectively raised on the substrate of the first region and the substrate of the second region;
the channel structure layer is suspended on the top of the fin part of the device region and comprises one or more channel layers arranged at intervals along the normal direction of the surface of the substrate;
the isolation layer is positioned on the substrate of the isolation region and exposes the side wall of the channel structure layer;
the dielectric wall is positioned on the substrate at the junction of the first area and the second area and covers the side wall of the channel structure layer, and the dielectric wall comprises a bottom dielectric wall and a top dielectric wall positioned at the top of the bottom dielectric wall;
the gate dielectric layer covers part of the top, part of the side wall and part of the bottom of the channel structure layer;
and the gate electrode layer is positioned on the substrate and stretches across the channel structure layer and the dielectric wall, and the gate electrode layer covers the gate dielectric layer in a surrounding manner.
2. The semiconductor structure of claim 1, wherein a top of the bottom dielectric wall is higher than a top of the channel structure layer.
3. The semiconductor structure of claim 1, wherein a distance from a top of the bottom dielectric wall to a top of the channel structure layer is 5 nm to 20 nm.
4. The semiconductor structure of claim 1, wherein a material of the top dielectric wall is the same as a material of the isolation layer.
5. The semiconductor structure of claim 1, wherein a top of the substrate at an interface of the first region and the second region is lower than a top of the substrate of the isolation region.
6. The semiconductor structure of claim 5, wherein a distance from a top of the substrate at an interface of the first region and the second region to a top of the substrate of the isolation region is 50 to 300 angstroms.
7. The semiconductor structure of claim 5, wherein a material of the top dielectric wall comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride.
8. The semiconductor structure of claim 1, wherein the material of the bottom dielectric wall comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride, and silicon carbonitride.
9. The semiconductor structure of claim 1, wherein the material of the channel layer comprises one or more of silicon, silicon germanium, and a group iii-v semiconductor material.
10. The semiconductor structure of claim 1, wherein the material of the gate dielectric layer comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of;
the material of the gate electrode layer comprises one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAl C.
11. The semiconductor structure of claim 1, wherein a first region of the device region is used to form a first type transistor and a second region of the device region is used to form a second type transistor, the first and second type transistors having different channel conductivity types.
12. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a discrete device region, the device region comprises a first region and a second region which are adjacent to each other, the substrate comprises a substrate and a fin portion which is respectively protruded from the substrate of the first region and the substrate of the second region, a channel laminated structure is formed on the fin portion, the channel laminated structure comprises one or more longitudinally stacked channel laminated layers, each channel laminated layer comprises a sacrificial layer and a channel layer which is positioned on the sacrificial layer, and in the device region, the substrate of the first region and the substrate of the second region which are adjacent to each other, the fin portion and the boundary of the first region and the second region enclose an isolation groove;
forming bottom side wall material layers which conformally cover the channel laminated structure and the substrate, wherein the bottom side wall material layers positioned on the opposite side walls of the isolation groove are in contact;
removing the side wall material layers positioned at the top of the substrate and the top of the channel laminated structure and the side wall material layer with partial thickness in the isolation groove, and forming a bottom dielectric wall in partial space of the isolation groove, wherein the top surface of the bottom dielectric wall is higher than the top surface of the channel laminated structure;
after the bottom dielectric wall is formed, a top dielectric wall covering the top of the bottom dielectric wall is formed in the residual space of the isolation groove, the top of the top dielectric wall is flush with the top of the channel laminated structure, and the top dielectric wall and the bottom dielectric wall form the dielectric wall.
13. The method of forming a semiconductor structure of claim 12, wherein forming the top dielectric wall comprises: forming a top side wall material layer covering the substrate and the channel laminated structure, wherein the top side wall material layer is also filled in the residual space of the isolation groove;
and etching back the top side wall material layer, removing the top side wall material layer which is higher than the top of the channel laminated structure in the device region, forming a top dielectric wall covering the top of the bottom dielectric wall in the residual space of the isolation groove, wherein the top of the top dielectric wall is flush with the top of the channel laminated structure, and the top dielectric wall and the bottom dielectric wall form the dielectric wall.
14. The method of forming a semiconductor structure of claim 13, wherein in the step of providing the substrate, the substrate further comprises isolation regions between the device regions;
the step of back etching the top side wall material layer comprises the following steps: performing first etching-back treatment on the top side wall material layer of the isolation region, and removing the top side wall material layer with preset thickness in the isolation region;
and after the first etching back treatment, performing second etching back treatment on the residual top side wall material layers in the isolation region and the device region by taking the top of the channel laminated structure as an etching stop position to form a top dielectric wall in the isolation groove and an isolation layer on the isolation region substrate.
15. The method for forming a semiconductor structure according to claim 14, wherein the step of performing a first etch-back process on the top spacer material layer of the isolation region comprises: forming a first patterned mask layer on the top of the top side wall material layer of the device region; and etching and removing the top side wall material layer with the preset thickness in the isolation region by taking the first mask layer as a mask.
16. The method of forming a semiconductor structure of claim 12, wherein the step of forming the substrate and channel stack comprises:
providing an initial substrate, wherein the initial substrate comprises a discrete device area, the device area comprises a first area and a second area which are adjacent, one or more longitudinally stacked channel material lamination layers are formed on the initial substrate, and each channel material lamination layer comprises a sacrificial material layer and a channel material layer positioned on the sacrificial material layer;
and patterning the initial substrate and a channel material lamination layer positioned on the initial substrate, and patterning the initial substrate into the substrate, wherein the substrate comprises a substrate and fin parts protruding from the substrate of the first region and the second region respectively, and the channel material lamination layer is patterned into a channel lamination layer positioned on the fin parts.
17. The method of forming a semiconductor structure according to claim 12 or 16, wherein in the step of forming the substrate, the substrate further comprises an isolation region between the device regions;
in the step of forming the substrate, an isolation opening is surrounded by the adjacent channel lamination layer closest to the isolation region, the fin portion and the remaining substrate of the isolation region, and the bottom of the isolation groove is lower than the bottom of the isolation opening.
18. The method of forming a semiconductor structure of claim 16, wherein patterning the initial substrate and the stack of channel materials on the initial substrate comprises: forming a core layer on top of the channel material stack, the core layer having a mask opening formed therein at a boundary of the first and second regions;
forming a discrete second mask layer on the top of the core layer of the first area and the second area, wherein the second mask layer exposes the top of the core layer of the isolation area;
and etching the core layer, the channel material lamination and the initial substrate with partial thickness by taking the second mask layer as a mask.
19. The method for forming a semiconductor structure according to claim 14, wherein the step of performing the first etch-back process removes the top spacer material layer in the isolation region to a predetermined thickness of 500 to 1500 angstroms.
20. The semiconductor structure of claim 12, wherein a first region of the device region is used to form a first type transistor and a second region of the device region is used to form a second type transistor, the first and second type transistors having different channel conductivity types.
CN202110569594.8A 2021-05-25 2021-05-25 Semiconductor structure and forming method thereof Pending CN115394719A (en)

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