CN115224027A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN115224027A
CN115224027A CN202110420045.4A CN202110420045A CN115224027A CN 115224027 A CN115224027 A CN 115224027A CN 202110420045 A CN202110420045 A CN 202110420045A CN 115224027 A CN115224027 A CN 115224027A
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layer
channel
forming
gate
device region
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

A structure of a semiconductor and a forming method thereof are provided, the method comprises the following steps: after the dielectric wall is formed, forming a first protective layer covering the top and the side wall of the channel lamination in the second device area, wherein the first protective layer exposes the channel lamination in the first device area; removing the first channel layer exposed from the gate opening in the first device region by using the first protective layer as a mask to form a first through groove communicated with the gate opening; after the first through groove is formed, forming a second protective layer covering the grid opening and the second channel layer exposed from the first through groove in the first device area; and removing the first protective layer and the second channel layer exposed from the gate opening in the second device region by using the second protective layer as a mask to form a second through groove communicated with the gate opening. The first channel layer and the second channel layer can respectively meet the requirements of the second type transistor and the first type transistor on the carrier mobility, so that the performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor transistors are moving toward higher element density and higher integration, and the trend of semiconductor process nodes following moore's law is decreasing. Transistors are now widely used as the most basic semiconductor transistors, and therefore, as the element density and integration of semiconductor transistors increase, the channel length of the transistors has to be shortened in order to accommodate the reduction in process nodes.
In order to better meet the requirement of scaling down the transistor size, the semiconductor process gradually starts to transition from planar transistors to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets), gate-all-around (GAA) transistors, etc. Wherein the fully-wrapped-around gate transistor comprises a vertical fully-wrapped-around gate transistor and a horizontal fully-wrapped-around gate transistor. In the all-around gate transistor, the gate surrounds the region where the channel is located from the periphery, and compared with a planar transistor, the all-around gate transistor has stronger control capability on the channel by the gate, and can better inhibit a short-channel effect.
With the further reduction of the device size, it is increasingly difficult and challenging to improve the carrier mobility of the conductive channel of both the NMOS device having the fully-wrapped-gate structure and the PMOS device having the fully-wrapped-gate structure.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which are beneficial to further improving the performance of the semiconductor structure.
To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate including a first device region for forming a first type transistor and a second device region for forming a second type transistor, the first and second device regions being adjacent in a first direction; a first channel structure layer extending along a second direction and located on the substrate of the second device region, wherein the first channel structure layer longitudinally comprises one or more first channel layers arranged at intervals, the first channel layer at the bottommost part is in contact with the substrate, and the second direction is perpendicular to the first direction; the second channel structure layer is positioned on the substrate of the first device area and is arranged at intervals with the substrate, the second channel structure layer comprises one or more second channel layers arranged at intervals in the longitudinal direction, and the second channel layers and the first channel layers are arranged in a staggered mode in the longitudinal direction; the dielectric wall extends along the second direction, is positioned on the substrate at the junction of the first device area and the second device area, and covers the side walls of the first channel structure layer and the second channel structure layer; the first gate dielectric layer is positioned in the first device region and covers part of the top, part of the side wall and part of the bottom of the second channel layer; the second gate dielectric layer is positioned in the second device area and covers part of the top, part of the side wall and part of the bottom of the first channel layer; and the grid structure is positioned on the top of the substrate and stretches across the first channel structure layer, the second channel structure layer and the dielectric wall, covers partial tops of the first channel structure layer, the dielectric wall and the second channel structure layer and surrounds the first grid dielectric layer and the second grid dielectric layer.
Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate including a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, the first and second device regions being adjacent in a first direction, the substrate having one or more longitudinally stacked channel stacks formed thereon, each channel stack including a first channel layer for providing a channel of the first-type transistor and a second channel layer on the first channel layer, the first channel layer for providing a channel of the second-type transistor, and channel materials of the first-type and second-type transistors being different; forming a dielectric wall penetrating through the channel stack and extending along a second direction in the channel stack at the intersection of the first device region and the second device region, wherein the dielectric wall separates the channel stack in the first device region and the second device region in the first direction, and the first direction is perpendicular to the second direction; forming a dummy gate spanning the channel stack and the dielectric wall, the dummy gate covering a portion of the top and a portion of the sidewalls of the channel stack; removing the pseudo gate to form a gate opening; after the dielectric walls are formed, forming a first protection layer covering the top and the side wall of the channel lamination layer in the second device area, wherein the first protection layer exposes the channel lamination layer in the first device area; removing the first channel layer exposed from the gate opening in the first device region by using the first protective layer as a mask to form a first through groove communicated with the gate opening; after the first through groove is formed, forming a second protective layer covering the gate opening and the second channel layer exposed by the first through groove in the first device area; removing the first protective layer and the second channel layer exposed from the gate opening in the second device region by using the second protective layer as a mask to form a second through groove communicated with the gate opening; forming a gate structure in the gate opening, the first through trench and the second through trench, the gate structure surrounding a first channel layer in the first device region exposed by the dielectric wall and a second channel layer in the second device region exposed by the dielectric wall.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a semiconductor structure, wherein a first channel structure layer is positioned on a substrate of a second device area, the first channel structure layer comprises one or more first channel layers arranged at intervals in the longitudinal direction, and the first channel layer at the bottommost part is in contact with the substrate; the second channel structure layer is located on the substrate of the first device area and is arranged at intervals with the substrate, the second channel structure layer comprises one or more second channel layers arranged at intervals in the longitudinal direction, and the second channel layers and the first channel layers are arranged in a staggered mode in the longitudinal direction. Compared with the existing scheme that the first channel structure layer and the second channel structure layer are symmetrical to each other in the horizontal direction, the second channel layer and the first channel layer are arranged in a staggered mode in the longitudinal direction, and the first channel layer and the second channel layer can meet the requirements of a second type transistor and a first type transistor on the carrier mobility respectively so as to meet the performance requirements of the second type transistor and the first type transistor respectively, and therefore the performance of the semiconductor structure is improved; meanwhile, the second channel layers and the first channel layers are arranged in a staggered mode in the longitudinal direction, so that the same channel lamination can be formed on the substrate of the first device region and the substrate of the second device region in the forming process of the semiconductor structure, each channel lamination comprises the first channel layer and the second channel layer positioned on the first channel layer, and only the first channel layer in the first device region and the second channel layer in the second device region are required to be removed respectively, so that the process difficulty of forming the first channel layer and the second channel layer is reduced, and the process manufacturing efficiency is improved.
Accordingly, an embodiment of the present invention provides a method for forming a semiconductor structure, in which after a dielectric wall is formed, a first protection layer covering a top and a sidewall of a channel stack is formed in a second device region, and the first protection layer exposes the channel stack in the first device region; removing the first channel layer exposed from the gate opening in the first device region by using the first protective layer as a mask to form a first through groove communicated with the gate opening; after the first through groove is formed, forming a second protective layer covering the gate opening and the second channel layer exposed by the first through groove in the first device area; and removing the first protective layer and the second channel layer exposed from the gate opening in the second device region by using the second protective layer as a mask to form a second through groove communicated with the gate opening. Compared with the prior art that the first channel layer of the first device region and the first channel layer of the second device region are removed simultaneously after the gate opening is formed, in the embodiment of the invention, the first protective layer is formed in the second device region to cover the top and the sidewall of the channel stack, that is, in the step of removing the first channel layer of the first device region, the first protective layer can play a role of protecting and isolating the channel stack of the second device region, and then in the first device region, the second protective layer is formed to conformally cover the second channel layer, that is, in the step of removing the second channel layer of the second device region, the second protective layer can play a role of an etching mask, and accordingly, the first channel layer in the first device region and the second channel layer in the second device region can be removed respectively, so that the first channel layer and the second channel layer can meet the requirements of the second type transistor and the first type transistor on the carrier mobility respectively, so as to meet the respective performance requirements of the second type transistor and the first type transistor respectively, thereby improving the performance of the semiconductor structure.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIG. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention;
fig. 7 to 23 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Detailed Description
The performance of semiconductor structures currently needs to be improved. The reason why the performance of a semiconductor structure needs to be improved is analyzed in combination with a method for forming the semiconductor structure.
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate including a first device region 10a for forming a first type transistor and a second device region 10b for forming a second type transistor, the first device region 10a and the second device region 10b being adjacent in a first direction (as indicated by X direction in fig. 1), one or more longitudinally stacked channel stacks 13 formed on the substrate, each channel stack 13 including a sacrificial layer 11 and a channel layer 12 on the sacrificial layer 11, an isolation layer 18 formed on the substrate exposed by the channel stack 13, a dielectric wall 17 formed in the channel stack 13 at an interface of the first device region 10a and the second device region 10b and extending in a second direction (as indicated by Y direction in fig. 1) and penetrating the channel stack 13, the dielectric wall 17 separating the channel stack 13 in the first device region 10a and the second device region 10b in the first direction, and the first direction being perpendicular to the second direction.
The second direction refers to a direction parallel to the horizontal direction and perpendicular to the first direction.
Referring to fig. 2, a dummy gate 16 crossing the channel stack 13 and the dielectric wall 17 is formed, the dummy gate 16 covers a part of the top and a part of the side wall of the channel stack 13, a side wall 15 is formed on the side wall of the dummy gate 16, an interlayer dielectric layer 14 is formed on the isolation layer exposed by the dummy gate 16 and the side wall 15, and the interlayer dielectric layer covers the side wall of the side wall 15.
Referring to fig. 3, the dummy gate 16 is removed to form a gate opening 18.
Referring to fig. 4, the sacrificial layer 11 is removed along the gate opening 18, and the channel layers 12 remaining in the first and second device regions 10a and 10b are disposed symmetrically with each other in a horizontal direction.
Referring to fig. 5, a gate structure 19 is formed in the gate opening 18, the gate structure 19 surrounding the channel layer 12 in the first device region 10a exposed by the dielectric walls 17 and the channel layer 12 in the second device region 10b exposed by the dielectric walls 17.
The first device region 10a is used to form an NMOS transistor, and the second device region 10b is used to form a PMOS transistor.
As shown in fig. 4, the gate opening 18 simultaneously exposes the sacrificial layer 11 in the first device region 10a and the second device region 10b, and thus, the first device region 10a and the second device region 10b can only retain the same channel layer 12. That is, in the forming method, the first-type transistor and the second-type transistor can only use the same channel layer material. When the first-type transistor and the second-type transistor need to use different channel layers (for example, channel layers of different materials are needed to meet the requirement for carrier mobility), the forming method cannot meet the requirement that the respective required channel layers remain in the first device region 10a and the second device region 10b, so that it is difficult to meet the respective performance requirements of the second-type transistor and the first-type transistor, respectively.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate including a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, the first and second device regions being adjacent in a first direction, the substrate having one or more longitudinally stacked channel stacks formed thereon, each channel stack including a first channel layer for providing a channel of the first-type transistor and a second channel layer on the first channel layer, the first channel layer for providing a channel of the second-type transistor, and channel materials of the first-type and second-type transistors being different; forming a dielectric wall penetrating through the channel stack and extending along a second direction in the channel stack at an intersection of the first device region and the second device region, wherein the dielectric wall separates the channel stack in the first device region and the second device region in the first direction, and the first direction is perpendicular to the second direction; forming a dummy gate spanning the channel stack and the dielectric wall, the dummy gate covering a portion of the top and a portion of the sidewalls of the channel stack; removing the pseudo gate to form a gate opening; after the dielectric walls are formed, forming a first protection layer covering the top and the side wall of the channel lamination layer in the second device area, wherein the first protection layer exposes the channel lamination layer in the first device area; removing the first channel layer exposed from the gate opening in the first device region by using the first protective layer as a mask to form a first through groove communicated with the gate opening; after the first through groove is formed, forming a second protective layer covering the gate opening and the second channel layer exposed by the first through groove in the first device area; removing the first protection layer and the second channel layer exposed by the gate opening in the second device region by using the second protection layer as a mask to form a second through groove communicated with the gate opening; forming a gate structure in the gate opening, the first through trench and the second through trench, the gate structure surrounding the first channel layer in the first device region exposed by the dielectric wall and the second channel layer in the second device region exposed by the dielectric wall.
In the embodiments of the present invention, a first protection layer is formed in the second device region to cover the top and the sidewall of the channel stack, that is, in the step of removing the first channel layer in the first device region, the first protection layer can protect and isolate the channel stack in the second device region, and then in the first device region, a second protection layer conformally covering the second channel layer is formed, that is, in the step of removing the second channel layer in the second device region, the second protection layer can function as an etching mask, and accordingly, the first channel layer and the second channel layer can respectively satisfy the requirements of the second type transistor and the first type transistor on the carrier mobility, so as to respectively satisfy the respective performance requirements of the second type transistor and the first type transistor, thereby improving the performance of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
FIG. 6 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: a substrate including a first device region 200a for forming a first type transistor and a second device region 200b for forming a second type transistor, the first and second device regions 200a and 200b being adjacent in a first direction (as shown in an X direction in fig. 6); a first channel structure layer 260 extending in a second direction (as shown in a Y direction in fig. 6) on the substrate of the second device region 200b, the first channel structure layer 260 including one or more first channel layers 201 spaced apart in the longitudinal direction, and a bottommost of the first channel layers 201 contacting the substrate, the second direction being perpendicular to the first direction; a second channel structure layer 270 extending in the second direction, the second channel structure layer 270 being located on the substrate of the first device region 200a and spaced apart from the substrate, the second channel structure layer 270 including one or more second channel layers 202 spaced apart in the longitudinal direction, and the second channel layers 202 being staggered with the first channel layers 201 in the longitudinal direction; a dielectric wall 207 extending along the second direction, located on the substrate at the interface of the first device region 200a and the second device region 200b, and covering sidewalls of the first channel structure layer 260 and the second channel structure layer 270; and a gate structure 225 located on top of the substrate and crossing the first channel structure layer 260, the second channel structure layer 270 and the dielectric wall 207, wherein the gate structure 225 covers partial tops of the first channel structure layer 260, the dielectric wall 207 and the second channel structure layer 270 and surrounds the first channel layer 201 and the second channel layer 202.
In this embodiment, the second channel layers 202 and the first channel layers 201 are arranged in a staggered manner in the longitudinal direction, and the first channel layers 201 and the second channel layers 202 can respectively meet the requirements of the second type transistor and the first type transistor on the carrier mobility so as to respectively meet the respective performance requirements of the second type transistor and the first type transistor, thereby improving the performance of the semiconductor structure; meanwhile, the second channel layers 202 are longitudinally staggered from the first channel layers 201, and therefore, in the formation of the semiconductor structure, the same channel stacks, each including the first channel layer 201 and the second channel layer 202 on the first channel layer 201, may be formed on the substrate of the first device region 200a and the second device region 200b, as long as the first channel layer 201 in the first device region 200a and the second channel layer 202 in the second device region 200b are removed, respectively, which reduces the difficulty of the process for forming the first channel layer 201 and the second channel layer 202 and improves the efficiency of the process manufacturing.
In this embodiment, the substrate includes a first device region 200a for forming a first type transistor and a second device region 200b for forming a second type transistor, the first device region 200a and the second device region 200b being adjacent in the first direction.
The first type transistor and the second type transistor have different channel conductivity types. Specifically, the first type is an N type, and the second type is a P type.
In this embodiment, the first type transistor is used to form an NMOS transistor, and the second type transistor is used to form a PMOS transistor; the material of the first channel layer 201 includes silicon germanium; the material of the second channel layer 202 includes silicon.
It should be noted that the material of the second channel layer 202 in the first device region 200a is silicon, and a Si channel technology is adopted for an NMOS transistor, which is beneficial to improving the performance of the NMOS transistor, that is, improving the carrier mobility of the NMOS transistor; the first channel layer 201 of the second device region 200b is made of silicon germanium, and a SiGe channel technology is adopted for the PMOS transistor, which is beneficial to improving the performance of the PMOS transistor, i.e., improving the carrier mobility of the PMOS transistor.
In other embodiments, the first type transistors are used to form PMOS transistors and the second type transistors are used to form NMOS transistors; the material of the first channel layer comprises silicon; the material of the second channel layer includes silicon germanium.
In this embodiment, the base is a three-dimensional structure, and includes a substrate 200 and a fin portion 280 separated from the first device region 200a and the second device region 200b on the substrate 200. In other embodiments, the base may be a planar substrate. In this embodiment, the substrate 200 is a silicon substrate, the fin 280 and the substrate 200 are made of the same material, and the fin 280 is made of silicon.
In this embodiment, the semiconductor structure further includes: an isolation layer 208 is located on the substrate 200 exposed at the side of the fin portion 280, and the isolation layer 208 exposes the first channel structure layer 260 and the second channel structure layer 270. The isolation layer is used to isolate the adjacent fins 280. The isolation layer 208 also serves to isolate the gate structure 225 from the substrate 200.
In this embodiment, the isolation layer 208 is made of silicon nitride.
In this embodiment, the semiconductor structure further includes: and the side wall 213 is positioned at the top of the substrate, and covers the side part of the gate structure 225.
The sidewall 213 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 213 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall spacers 213 have a single-layer structure, and the sidewall spacers 213 are made of silicon nitride.
In this embodiment, a first channel structure layer 260 extending along a second direction is located on the substrate of the second device region 200b, the first channel structure layer 260 includes one or more first channel layers 201 arranged at intervals in the longitudinal direction, and the bottommost first channel layer 201 is in contact with the substrate, and the second direction is perpendicular to the first direction.
The first channel layer 201 is used to provide a conductive channel of a first type transistor.
In this embodiment, the number of the first channel layers 201 is four. In other embodiments, the number of the first channel layers may also be other numbers.
In this embodiment, the second channel structure layer 270 extending along the second direction is located on the substrate of the first device region 200a and spaced apart from the substrate, the second channel structure layer 270 includes one or more second channel layers 202 spaced apart in the longitudinal direction, and the second channel layers 202 and the first channel layers 201 are staggered in the longitudinal direction.
The second channel layer 202 is used to provide a conductive channel for a transistor of the second type.
In this embodiment, the number of the second channel layers 202 is four. In other embodiments, the number of the second channel layers may also be other numbers.
In this embodiment, the fact that the second channel layers 202 and the first channel layers 201 are arranged in a staggered manner in the longitudinal direction means that, along the first direction, the second channel layers 202 correspond to gaps between adjacent first channel layers 201, or the first channel layers 201 correspond to gaps between adjacent second channel layers 202, or the first channel layers 201 correspond to gaps between the second channel layers 202 and the fin portion 280.
The second channel layers 202 are longitudinally staggered from the first channel layers 201, and therefore, in the formation of the semiconductor structure, the same channel stacks, each including the first channel layer 201 and the second channel layer 202 on the first channel layer 201, may be formed on the substrate of the first device region 200a and the second device region 200b, as long as the first channel layer 201 in the first device region 200a and the second channel layer 202 in the second device region 200b are removed, respectively, which reduces the difficulty of the process for forming the first channel layer 201 and the second channel layer 202 and improves the process efficiency.
In this embodiment, the first channel structure layer 260 and the second channel structure layer 270 are both located on the fin portion 280.
In this embodiment, the dielectric wall 207 extending along the second direction is located on the substrate at the boundary of the first device region 200a and the second device region 200b, and covers the sidewalls of the first channel structure layer 260 and the second channel structure layer 270.
Along the first direction, the dielectric wall 207 isolates the first channel structure layer 260 from the second channel structure layer 270 and the gate structure 225, and the dielectric wall 207 isolates the first type transistor from the second type transistor, which is beneficial to achieving smaller spacing between the first type transistor and the second type transistor.
In this embodiment, the dielectric wall 207 is further located between the fins 280 of the first device region 200a and the second device region 200b, and is used for isolating the fins 280 of the first device region 200a and the second device region 200 b.
For this purpose, the material of the dielectric wall 207 is a dielectric material, such as: one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride and silicon carbonitride so as to ensure that the dielectric wall 207 can play a role in isolation. In this embodiment, the dielectric wall 207 is made of silicon nitride.
As an example, the top surface of the dielectric wall 207 is higher than the top surface of the second channel structure layer 270.
In this embodiment, the first gate dielectric layer 290 is located in the first device region 200a, and the first gate dielectric layer 290 covers a part of the top, a part of the sidewall, and a part of the bottom of the second channel layer 202.
The first gate dielectric layer 290 is mainly used for electrically isolating the second channel structure layer 270 and the gate structure 225.
In this embodiment, the first gate dielectric layer 290 includes a first gate oxide layer 218 and a high-k gate dielectric layer 222 conformally covering the first gate oxide layer 218.
The material of the high-k gate dielectric layer 222 is a high-k dielectric material, wherein the high-k dielectric material is a dielectric material having a relative dielectric constant greater than that of silicon oxide. In particular, the material of the high-k gate dielectric layer 222 may be selected from HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of (a) and (b).
In this embodiment, the first gate dielectric layer 290 further covers the top of the isolation layer 208 of the first device region 200a and the sidewalls of the sidewall spacers 213.
In this embodiment, the first gate dielectric layer 290 includes a first gate oxide layer 218. As an example, the material of the first gate oxide layer 218 is silicon oxide.
In this embodiment, the thickness of the first gate oxide layer 218 is 5 to 15 angstroms.
It should be noted that the thickness of the first gate oxide layer 218 is not too large, nor too small. If the thickness of the first gate oxide layer 218 is too large, too many occupied space positions of the gap between the adjacent second channel layers 202 are likely to cause too large aspect ratio of the gap between the adjacent second channel layers 202 in the process of forming the gate structure 225, thereby increasing the difficulty in filling each film layer of the gate structure 225; if the thickness of the first gate oxide layer 218 is too small, the electrical isolation effect between the second channel structure layer 270 and the gate structure is reduced. For this reason, in this embodiment, the thickness of the first gate oxide layer 218 is 5 to 15 angstroms. The first gate oxide layer 218 has a thickness of, for example, 7, 10, or 12 angstroms.
In this embodiment, the second gate dielectric layer 291 is located in the second device region 200b, and the second gate dielectric layer 291 covers a portion of the top, a portion of the sidewall, and a portion of the bottom of the first channel layer 201.
The second gate dielectric layer 291 is mainly used for electrically isolating the first channel structure layer 260 from the gate structure 225.
In this embodiment, the second gate dielectric layer 291 includes a second gate oxide layer 250 and a high-k gate dielectric layer 222 conformally covering the second gate oxide layer 250.
The material of the high-k gate dielectric layer 222 is a high-k dielectric material, wherein the high-k dielectric material is a dielectric material having a relative dielectric constant greater than that of silicon oxide. In particular, the material of the high-k gate dielectric layer 222 may be selected from HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of (a) and (b).
In this embodiment, the second gate dielectric layer 291 includes a second gate oxide layer 250. As an example, the material of the second gate oxide layer 250 is silicon oxide.
In this embodiment, the second gate dielectric layer 291 further covers the top of the isolation layer 208 of the second device region 200b and the sidewall of the sidewall spacer 213.
It should be noted that, in other embodiments, the semiconductor structure further includes: and the channel transition layer is positioned in the second device area and is positioned between the second gate oxide layer and the first channel layer. In the forming process of the second gate oxide layer, the second gate oxide layer is formed by carrying out second oxidation treatment on the channel transition layer, so that when the channel transition layer with partial thickness is oxidized to form the second gate oxide layer, the channel transition layer with residual thickness can be remained correspondingly.
In this embodiment, the channel transition layer is completely consumed in the process of forming the second gate oxide layer 250, and therefore, the channel transition layer is not included in the semiconductor structure.
The channel transition layer can improve the interface state between the surface of the first channel structure layer and the second gate oxide layer, and can improve the reliability of the semiconductor structure.
The material of the channel transition layer comprises Si and Si (1-X) Ge x And SiC.
And a certain etching selection ratio is formed between the material of the channel transition layer and the material of the first channel structure layer. Wherein X represents a content of Ge in atomic percentage, the Ge concentration being in the range of 0.3 to 0.7.
In this embodiment, the gate structure 225 is located on the top of the substrate and crosses over the first channel structure layer 260, the second channel structure layer 270 and the dielectric wall 207, and the gate structure 225 covers part of the tops of the first channel structure layer 260, the dielectric wall 207 and the second channel structure layer 270 and surrounds the first gate dielectric layer 290 and the second gate dielectric layer 291.
The gate structure 225 is used to control the conduction channels of the first-type and second-type transistors to be turned on or off during device operation.
In this embodiment, the gate structure 225 is a metal gate structure.
In this embodiment, the gate structure includes a work function layer 223.
The work function layer 223 is used to adjust the threshold voltage of the first type transistor or the second type transistor. In this embodiment, the work function layer 223 includes one or more of TiAl, mo, moN, alN, tiN, taN, taSiN, taAlN, tiAlN, and TiAlC. Wherein the specific material and film structure of the work function layer 223 are determined according to the performance of the first type transistor or the second type transistor
Specifically, the first type transistor is an NMOS transistor, the work function layer 223 of the first device region 200a is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, mo, moN, alN, and TiAlC. The second type transistor is a PMOS transistor, the work function layer 223 of the second device region 200b is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, taN, taSiN, taAlN and TiAlN.
In this embodiment, the metal gate structure includes a gate electrode layer 224.
The gate electrode layer 224 is used for subsequent electrical connections to external structures. The material of the gate electrode layer 224 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC.
In this embodiment, the semiconductor structure further includes: and the interlayer dielectric layer 212 covers the side wall of the side wall 213.
The interlevel dielectric layer 212 is used to isolate adjacent devices. The material of the interlayer dielectric layer 212 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 212 is made of silicon oxide.
Fig. 7 to 23 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Referring to fig. 7, a substrate is provided, the substrate including a first device region 100a for forming a first-type transistor and a second device region 100b for forming a second-type transistor, the first device region 100a and the second device region 100b being adjacent in a first direction (as shown in an X direction in fig. 7), one or more longitudinally stacked channel stacks 103 formed on the substrate, each channel stack 103 including a first channel layer 101 and a second channel layer 102 on the first channel layer 101, the second channel layer 102 for providing a channel of the first-type transistor, the first channel layer 101 for providing a channel of the second-type transistor, and channel materials of the first-type transistor and the second-type transistor being different.
The substrate is used for providing a process platform for a manufacturing process.
In the step of providing the substrate, the first type transistor and the second type transistor have different channel conductivity types. Specifically, the first type is an N type, and the second type is a P type.
In this embodiment, the first type transistor is used to form an NMOS transistor, and the second type transistor is used to form a PMOS transistor; the material of the first channel layer 101 includes silicon germanium; the material of the second channel layer 102 includes silicon.
It should be noted that the second channel layer 102 of the first device region 100a is made of silicon, and a Si channel technology is adopted for an NMOS transistor, which is beneficial to improving the performance of the NMOS transistor, that is, improving the carrier mobility of the NMOS transistor; the first channel layer 101 of the second device region 100b is made of silicon germanium, and a SiGe channel technology is adopted for the PMOS transistor, which is beneficial to improving the performance of the PMOS transistor, that is, improving the carrier mobility of the PMOS transistor.
In other embodiments, the first type transistors are used to form PMOS transistors and the second type transistors are used to form NMOS transistors; the material of the first channel layer comprises silicon; the material of the second channel layer includes silicon germanium.
It should be noted that, in other embodiments, the first channel layer may also be made of other materials capable of meeting the performance requirement of the second type transistor, and similarly, the second channel layer may also be made of other materials capable of meeting the performance requirement of the first type transistor, and an etching selection ratio is provided between the materials of the first channel layer and the second channel layer.
In this embodiment, the base is a three-dimensional structure, and includes a substrate 100 and a fin portion 180 on the substrate 100 that is separated from the first device region 100a and the second device region 100 b. In other embodiments, the base may be a planar substrate. In this embodiment, the substrate 100 is a silicon substrate, the fin portion 180 is made of the same material as the substrate 100, and the fin portion 180 is made of silicon.
Accordingly, in the present embodiment, the channel stack 103 is formed on the fin 180, and the extending direction of the channel stack 103 is the same as that of the fin 180. The stacking direction of the plurality of channel stacks 103 is perpendicular to the surface of the substrate 100.
In this embodiment, the channel stack 103 is in a second direction (shown as the Y-direction in fig. 7). The second direction refers to a direction parallel to the horizontal direction and perpendicular to the first direction.
Channel stack 103 provides a process foundation for the subsequent formation of spaced apart channel layers.
As an example, the number of channel stacks 103 is four. In other embodiments, the number of channel stacks may be other numbers.
In this embodiment, the second channel layer 102 of the first device region 100a is used to provide a conductive channel of a first-type transistor, so that, for the first device region 100a, the first channel layer 101 is used as a first sacrificial layer, that is, the first channel layer 101 is used to support the second channel layer 102, and after the first channel layer 101 of the first device region 100a is subsequently removed, a spaced-apart arrangement of the second channel layer 102 can be achieved, and the first channel layer 101 of the first device region 100a also occupies a space for a subsequently formed gate structure.
In this embodiment, the first channel layer 101 of the second device region 100b is used to provide a conductive channel of a second type transistor, so that, for the second device region 100b, the second channel layer 102 is used as a second sacrificial layer, that is, the second channel layer 102 is used to support the first channel layer 101, after the second channel layer 102 of the second device region 100b is subsequently removed, the spaced-apart arrangement of the first channel layer 101 can be achieved, and the second channel layer 102 of the second device region 100b also occupies a space for a gate structure to be subsequently formed.
In the present embodiment, in the step of providing the substrate, the number of the first channel layers 101 and the second channel layers 102 is the same.
In this embodiment, in the step of providing a substrate, a hard mask layer 105 is further formed on the top of the channel stack 103. The hard mask layer 105 is used as a patterning mask in forming the channel stack 103 and the fin 180. In this embodiment, the hard mask layer 105 is made of silicon nitride.
In this embodiment, the forming method further includes: and forming a filling layer 104 on the top of the substrate exposed by the channel stack layer 103, wherein the filling layer 104 covers the channel stack layer 103 and the side wall of the hard mask layer 105. The filling layer 104 protects the top of the substrate during the subsequent formation of the dielectric wall.
In this embodiment, the material of the filling layer 104 is a dielectric material, so that the filling layer 104 can be utilized to form an isolation layer in the following process, thereby simplifying the process steps.
In this embodiment, the material of the filling layer 104 is silicon oxide.
Referring to fig. 8 to 9, at the boundary between the first device region 100a and the second device region 100b, a dielectric wall 107 extending through the channel stack 103 and along a second direction (indicated by Y direction in fig. 9) is formed in the channel stack 103, the dielectric wall 107 separates the channel stack 103 in the first device region 100a and the second device region 100b in the first direction (indicated by X direction in fig. 9), and the first direction is perpendicular to the second direction.
In the first direction, the dielectric wall 107 can serve as an isolation between the channel stack 103 of the first device region 100a and the channel stack 103 of the second device region 100b, and the dielectric wall 107 is used for isolating the first-type transistor and the second-type transistor, which is beneficial to achieving smaller spacing between the first-type transistor and the second-type transistor.
In this embodiment, the dielectric wall 107 is further located between the fins 180 of the first device region 100a and the second device region 100b, and is further configured to isolate the fins 180 of the first device region 100a and the second device region 100b, and ensure that the channel stacks 103 of the first device region 100a and the second device region 100b can be completely isolated, so as to improve an isolation effect of the dielectric wall 107 on adjacent channel stacks 103 of the first device region 100a and the second device region 100 b.
For this purpose, the material of the dielectric wall 107 is a dielectric material, for example, including one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbonitride, silicon carbonitride and silicon carbonitride, so as to ensure that the dielectric wall 107 can perform the isolation function. In this embodiment, the dielectric wall 107 is made of silicon carbonitride.
As an example, the top surface of the dielectric wall 107 is higher than the top surface of the channel stack 103, which is beneficial to improve the isolation effect of the dielectric wall 107 on the adjacent channel stack 103, and is also beneficial to improve the isolation effect of the dielectric wall 107 on the subsequent source/drain doping layer.
In this embodiment, the step of forming the dielectric wall 107 includes: as shown in fig. 8, the channel stack 103 at the boundary of the first device region 100a and the second device region 100b is removed, and a groove 106 penetrating through the channel stack 103 is formed; as shown in fig. 9, a dielectric material layer (not shown) is formed in the recess 106, the dielectric material layer also covers the top of the filling layer 104, the dielectric material layer higher than the top of the filling layer 104 is removed, and the remaining dielectric material layer in the recess 106 serves as the dielectric wall 107.
Specifically, the top of the hard mask layer 105 is used as a stop for the planarization process to remove the dielectric material layer above the top of the fill layer 104.
Referring to fig. 10, after forming the dielectric wall 107, the method further includes: and etching back the filling layer 104 with a part of thickness to form an isolation layer 108 covering the side wall of the fin portion 180, wherein the isolation layer 108 exposes the channel lamination layer 103.
The isolation layer 108 is used to isolate adjacent fins 180, and the isolation layer 108 is also used to isolate the substrate 100 from a subsequently formed gate structure. As an example, the material of the isolation layer 108 is silicon oxide.
It should be further noted that, after forming the isolation layer 108, the method further includes: the hard mask layer 105 is removed.
The hard mask layer 105 is removed to expose the top surface of the channel stack 103, facilitating the subsequent formation of a dummy gate across the channel stack 105 and the dielectric walls 107.
This embodiment exemplifies that the isolation layer 108 is formed after the dielectric wall 107 is formed. In other embodiments, the isolation layer can also be formed after forming the channel stack and before forming the dielectric wall. Correspondingly, in the step of forming the dielectric wall, the dielectric wall is also formed on the isolation structure between the fins of the first device region and the second device region.
Referring to fig. 11 to 12, after the dielectric walls 107 are formed, a first protection layer 110 covering the top and sidewalls of the channel stack 103 is formed in the second device region 100b, and the first protection layer 110 exposes the channel stack 103 of the first device region 100 a.
In the present embodiment, the first protection layer 110 is formed in the second device region 100b to cover the top and the sidewall of the channel stack 103, that is, in the subsequent step of removing the first channel layer 101 in the first device region 100a, the first protection layer 110 can perform a protection and isolation function on the channel stack 103 in the second device region 100b, so that the second channel layer 102 in the second device region 100b can be selectively removed in the subsequent step.
In this embodiment, after the dielectric walls 107 are formed and before the dummy gates are formed subsequently, the first protection layer 110 is formed on the top and sidewalls of the channel stack 103 and on the top of the substrate in the second device region 100 b.
It should be noted that, the first protection layer 110 is formed before the dummy gate is formed, so that the top and the sidewall of the channel stack 103 can be protected in the process of removing the dummy gate to form the gate opening.
In other embodiments, the first protection layer may also be formed after the gate opening is formed.
In this embodiment, the step of forming the first protection layer 110 includes: as shown in fig. 11, in the first device region 100a and the second device region 100b, a protective material layer 109 covering the top and sidewalls of the channel stack 103, and the top of the substrate is formed; as shown in fig. 12, the protective material layer 109 in the first device region 100a is removed, and the protective material layer 109 remaining in the second device region 100b serves as the first protective layer 110.
Specifically, a mask (mask) is used to selectively remove the protective material layer 109 of the first device region 100 a.
In the subsequent step of removing the first channel layer 101 in the first device region 100a, the first protection layer 110 can protect and isolate the channel stack 103 in the second device region 100b, that is, the material of the first protection layer 110 has characteristics of etching resistance, high hardness, and the like. To this end, the material of the first protective layer 110 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon oxycarbide. In this embodiment, the first protection layer 110 is made of silicon nitride.
In this embodiment, the thickness of the first protective layer 110 is 10 to 30 angstroms.
It should be noted that the thickness of the first protection layer 110 is not too large, nor too small. If the thickness of the first protection layer 110 is too large, the first protection layer easily occupies too much space of a subsequently formed dummy gate; if the thickness of the first protection layer 110 is too small, in the subsequent step of removing the first channel layer 101 in the first device region 100a, the protection effect of the first protection layer 110 on the channel stack of the second device region 100b is reduced, thereby affecting the electrical performance of the subsequently formed second type transistor. For this reason, in this embodiment, the thickness of the first protection layer 110 is 10 to 30 angstroms. For example, the first protective layer 110 has a thickness of 15 angstroms, 20 angstroms, or 25 angstroms.
In this embodiment, the process of forming the protective material layer 109 includes an atomic layer deposition process.
The atomic layer deposition process includes multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the first protection layer 110, and enables the first protection layer 110 to cover the top and the sidewall of the channel stack 103. In other embodiments, the first protection layer may also be formed by a Chemical Vapor Deposition (CVD) process.
In this embodiment, the process of removing the protective material layer 109 in the first device region 100a includes a dry etching process.
The dry etching process comprises an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, so that the longitudinal etching rate of the anisotropic dry etching process is far greater than the transverse etching rate, and the anisotropic dry etching process is favorable for ensuring the sidewall morphology quality of the channel lamination 103 of the first device region 100a and ensuring that the first protection layer 110 can completely cover the channel lamination 103 of the first device region 100a while obtaining quite accurate pattern transfer.
Referring to fig. 13, after forming the first protective layer 110, before forming the dummy gate subsequently, the method further includes: in the first device region 100a, a dummy gate oxide layer 111 is formed covering the top and sidewalls of the channel stack 103.
In the process of removing the dummy gate and forming the gate opening, the dummy gate oxide layer 111 protects the top and the side wall of the channel stack 103 in the first device region 100a, and reduces the probability of damage to the channel stack 103.
The material of the dummy gate oxide layer 111 includes one or more of silicon oxide, silicon oxynitride and silicon oxycarbide. In this embodiment, the material of the dummy gate oxide layer 111 is silicon oxide.
In order that the dummy gate oxide layer 111 can protect the top and the sidewalls of the channel stack 103 of the first device region 100a well, in this embodiment, the thickness of the dummy gate oxide layer 111 is 10 to 30 angstroms.
In this embodiment, the dummy gate oxide layer 111 is formed by an oxidation process. After the first protection layer 110 is formed, the dummy gate oxide layer 111 is formed, and the first protection layer 110 covers the channel lamination layer 103 of the second device area 100b, so that the dummy gate oxide layer 111 is only formed in the first device area 100a, a step of patterning the dummy gate oxide layer 111 is omitted, and the process steps are correspondingly simplified.
Referring to fig. 14, a dummy gate 115 is formed across the channel stack 103 and the dielectric wall 107, the dummy gate 115 covering a portion of the top and a portion of the sidewall of the channel stack 103.
The dummy gate 115 occupies a spatial location for subsequently formed gate structures.
In this embodiment, the dummy gate 115 crosses over the channel stack 103 and the dielectric wall 107, that is, the dummy gate 115 covers a portion of the top of the channel stack 103 and the dielectric wall 107, a portion of the sidewall of the dielectric wall 107, and a portion of the sidewall of the channel stack 103 opposite to the dielectric wall 107.
In this embodiment, the dummy gate 115 includes a dummy gate layer. The material of the dummy gate layer comprises polysilicon.
In this embodiment, the dummy gate 115 has a stripe structure, and the dummy gate 115 extends along a first direction (as shown by the X direction in fig. 14).
In this embodiment, after the dummy gate 115 is formed, the forming method further includes: and forming a side wall 113 on the side wall of the dummy gate 115.
The side walls 113 are used for protecting the side walls of the subsequently formed gate structure. The sidewall 113 may have a single-layer structure or a stacked-layer structure, and the material of the sidewall 113 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 113 has a single-layer structure, and the material of the sidewall 113 is silicon nitride.
In this embodiment, after forming the sidewall 113, the forming method further includes: source and drain doped layers (not shown) are formed in the channel stack 103 on both sides of the dummy gate 115. The conductivity type of the doped ions in the source and drain doped layers is the same as the conductivity type of the channel of the transistor in the region, and detailed description of the source and drain doped layers is omitted here for the sake of brevity.
In this embodiment, the forming method further includes: forming an interlayer dielectric layer 112 on the top of the isolation layer 108 exposed by the dummy gate 115 and the sidewall 113, wherein the interlayer dielectric layer 112 covers the sidewall of the sidewall 113.
The interlevel dielectric layer 112 is used to isolate adjacent devices. The material of the interlayer dielectric layer 112 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon oxycarbonitride. In this embodiment, the interlayer dielectric layer 112 is made of silicon oxide.
As an example, with continued reference to fig. 14, a gate mask layer 114 is further formed on top of the dummy gate 115.
The gate mask layer 114 is used as an etching mask when the dummy gate 115 is formed, and is also used for protecting the top of the dummy gate 115 in the process of forming the side wall 113 and the interlayer dielectric layer 112, so that the probability that the top of the dummy gate 115 is damaged is reduced. Correspondingly, the sidewall spacers 113 also cover the sidewalls of the gate mask layer 114.
Referring to fig. 15, the dummy gate 115 is removed to form a gate opening 116.
The gate opening 116 is used to provide a spatial location for the subsequent formation of a gate structure.
Moreover, after the dummy gate 115 is removed, the gate opening 116 exposes the dummy gate oxide 111 and the first protection layer 110, so that the dummy gate oxide 111 and the first protection layer 110 can be removed through the gate opening 116.
Specifically, the process of removing the dummy gate 115 includes one or both of a dry etching process and a wet etching process.
Referring to fig. 16 to 17, the first protection layer 110 is used as a mask, and the first channel layer 101 exposed by the gate opening 116 is removed in the first device region 100a to form a first through trench 117 communicating with the gate opening 116.
The first through trench 117 and the gate opening 116 of the first device region 100a provide a spatial location for subsequently forming a gate structure.
In the first device region 100a, the first channel layer 101 exposed by the gate opening 116 is removed, and the remaining second channel layer 102 is used to provide a conductive channel when the first-type transistor operates.
The first through-trench 117 is surrounded by the second channel layer 102 adjacent to the first through-trench or the substrate and the second channel layer 102.
In this embodiment, after the first through-trench 117 is formed, along the second direction (as shown in the Y direction in fig. 17), the second channel layer 102 is suspended in the gate opening 116, so as to provide a process foundation for a subsequently formed gate structure to surround the second channel layer 102 in the first device region 100 a.
In this embodiment, the process of removing the first channel layer 101 of the first device region 100a to form the first through trench 117 includes a wet etching process.
Note that the first channel layer 101 is removed by a wet etching process. The wet etching process is isotropic etching, has high etching rate, is simple to operate and has low process cost. The first channel layer 101 is made of SiGe, and an etching solution adopted by a corresponding wet etching process is a hydrogen chloride solution.
Referring to fig. 16, in the step of forming the first through trenches 117, before removing the first channel layer 101 in the channel stack 103 exposed by the first device region 100a, further including: and removing the pseudo gate oxide layer 111.
The dummy gate oxide layer 111 is removed to expose the top and sidewalls of the channel stack 103 of the first device region 100a, which facilitates the removal of the exposed first channel layer 101 during the formation of the first through trench 117.
Referring to fig. 18, after the first through trench 117 is formed, a second protective layer 118 covering the gate opening 116 and the second channel layer 102 exposed by the first through trench 117 is formed in the first device region 100 a.
The second protection layer 118 is used for protecting the surface of the second channel layer 102 exposed in the first device region 100a in a subsequent process of removing the second channel layer 102 in the second device region 100b, so that the probability that the surface of the second channel layer 102 exposed in the first device region 100a is damaged is reduced.
Therefore, in the present embodiment, the first protection layer 110 is formed in the second device region 100b to cover the top and the sidewall of the channel stack 103, that is, in the step of removing the first channel layer 101 in the first device region 100a, the first protection layer 110 can play a role of protecting and isolating the channel stack 103 in the second device region 100b, and then in the first device region 100a, the second protection layer 118 is formed to conformally cover the second channel layer 102, that is, in the step of removing the second channel layer 102 in the second device region 100b, the second protection layer 102 can play a role of etching mask, accordingly, the first channel layer 101 in the first device region 100a and the second channel layer 102 in the second device region 100b can be removed respectively, so that the first channel layer 101 and the second channel layer 102 can respectively meet the requirements of the second type transistor and the first type transistor on the carrier mobility to respectively meet the performance requirements of the second type transistor and the first type transistor, thereby improving the performance of the semiconductor structure.
In this embodiment, the step of forming the second protection layer 118 includes: in the first device region 100a, the second channel layer 102 exposed by the gate opening 116 and the first through trench 117 is subjected to a first oxidation process to form a first gate oxide layer covering each surface of the second channel layer 102, the first gate oxide layer serving as the second protection layer 118.
The first gate oxide layer is used as part of a gate dielectric layer of a subsequent first device region 100 a. By using the first gate oxide layer as the second protective layer 118, a step of additionally forming a second protective layer is omitted, and accordingly, the process steps are simplified.
Moreover, the first protective layer 110 is formed in the second device region 100b, and thus, the second protective layer 118 may be selectively formed on the exposed surface of the second channel layer 102, that is, the surface of the second channel layer 102 exposed by the gate opening 116 and the first through via 117, during the first oxidation process, and accordingly, the process complexity of forming the second protective layer 118 may be reduced.
In this embodiment, the thickness of the second protective layer 118 is 10 to 50 angstroms.
It should be noted that the thickness of the second protective layer 118 is not too large, nor too small. If the thickness of the second protection layer 118 is too large, the excessively occupied space position of the first through groove 117 easily causes an excessively large aspect ratio of the remaining space of the first through groove 117 in the subsequent process of forming the gate structure, thereby increasing the difficulty in filling each film layer of the gate structure, and when the second protection layer 118 is formed by performing the first oxidation treatment on the second channel layer 102, the thickness of the second protection layer 118 is too large, which correspondingly easily causes an excessively large consumption amount of the second channel layer 102, thereby affecting the size of the second channel layer 102 and further affecting the performance of the first transistor; if the thickness of the second protection layer 118 is too small, the effect of protecting the second channel layer 102 of the first device region 100a is reduced in the subsequent process of removing the second channel layer 102 of the second device region 100b, thereby affecting the performance of the semiconductor structure. For this reason, in the present embodiment, the thickness of the second protective layer 118 is 10 to 50 angstroms. For example, the second protective layer 118 has a thickness of 20 angstroms, 30 angstroms, or 40 angstroms.
The material of the second protective layer 118 includes one or more of silicon oxide, silicon oxynitride, and silicon oxycarbide. In this embodiment, the second passivation layer 118 is made of silicon oxide.
In other embodiments, the process of forming the second protection layer may also be an atomic layer deposition process.
Referring to fig. 19 to 20, the second protective layer 118 is used as a mask, and the first protective layer 110 and the second channel layer 102 exposed by the gate opening 116 are removed in the second device region 100b, so as to form a second through trench 119 communicating with the gate opening 116.
The second via 119 and the gate opening 116 of the second device region 100b provide a spatial location for a subsequently formed gate structure.
In the second device region 100b, the second channel layer 102 exposed by the gate opening 116 is removed, and the remaining first channel layer 101 is used to provide a conductive channel when the second type transistor operates.
The second through trench 119 is surrounded by the adjacent first channel layer 101 and the dielectric wall 107.
In this embodiment, after the second through trench 119 is formed, along the second direction (as shown in the Y direction in fig. 20), the second channel layer 119 is suspended in the gate opening 116, so as to provide a process foundation for a subsequently formed gate structure to surround the first channel layer 101 of the second device region 100 b.
In this embodiment, the process of removing the first protection layer 110 includes a dry etching process.
The dry etching process comprises an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, so that the longitudinal etching rate of the anisotropic dry etching process is far greater than the transverse etching rate, and the sidewall morphology quality of the channel lamination layer 103 of the second device region 100b can be ensured while quite accurate pattern transfer can be obtained.
In this embodiment, the process of removing the second channel layer 102 in the second device region 100b to form the second through trench includes a wet etching process.
Note that, the second channel layer 102 in the second device region 100b is removed by a wet etching process. The wet etching process is isotropic etching, has high etching rate, is simple to operate and has low process cost. The second channel layer 102 is made of Si, and an etching solution adopted in a corresponding wet etching process is a tetramethylammonium hydroxide (TMAH) solution.
Referring to fig. 21, after forming the second through trench 119, before forming a second gate oxide layer subsequently, the method further includes: in the second device region 100b, a channel transition layer 120 is formed conformally covering the respective surfaces of the first channel layer 101.
The channel transition layer 120 can improve an interface state between the surface of the first channel layer 101 and a subsequently formed second gate oxide layer, and can improve reliability of a semiconductor structure.
In this embodiment, the process of forming the channel transition layer 120 includes an atomic layer deposition process.
The atomic layer deposition process includes multiple atomic layer deposition cycles, has good step-like filling capability, is beneficial to improving the thickness uniformity of the channel transition layer 120, and enables the channel transition layer 120 to cover the top and the side wall of the first channel layer 101. In other embodiments, the channel transition layer may also be formed by a Chemical Vapor Deposition (CVD) process.
In this embodiment, in the step of forming the channel transition layer 120, the material of the channel transition layer 120 includes Si and Si (1-X) Ge x And SiC, wherein X represents an atomic percent content of Ge, the Ge concentration being in the range of 0.3 to 0.7. .
The material of the channel transition layer 120 is beneficial to forming a second gate oxide layer covering each surface of the first channel layer 101 in the process of performing a second oxidation process.
In this embodiment, in the step of forming the channel transition layer 120, the thickness of the channel transition layer 120 is 20 to 200 angstroms.
It should be noted that the thickness of the channel transition layer 120 is not too large or too small. If the thickness of the channel transition layer 120 is too large, the occupied space of the second through-groove 119 is too large, and the aspect ratio of the remaining space of the second through-groove 119 is easily too large in the subsequent process of forming the gate structure, thereby increasing the filling difficulty of each film layer of the gate structure; if the thickness of the channel transition layer 120 is too small, the thickness of the second gate oxide layer formed to cover each surface of the first channel layer 101 is also too small during the second oxidation process, thereby affecting the electrical isolation effect between the first channel layer 101 and the gate structure formed subsequently. For this reason, in the present embodiment, the thickness of the channel transition layer 120 is 20 to 200 angstroms. For example, the channel transition layer 120 has a thickness of 60, 100, or 150 angstroms.
In other embodiments, the channel transition layer may not be formed according to the process requirement.
Referring to fig. 22, after forming the second through trench 119, before forming a gate structure subsequently, the method further includes: the first channel layer 101 exposed by the gate opening 116 and the second through-groove 119 is subjected to a second oxidation process, and a second gate oxide layer 150 covering each surface of the first channel layer 101 is formed.
The second gate oxide layer 150 is used as a part of a gate dielectric layer of the second device region 100b, and the second gate oxide layer 150 is mainly used for electrically isolating the first channel layer 101 from a subsequently formed gate structure.
In this embodiment, since the channel transition layer 120 is formed on the surface of the first channel layer 101, in the step of performing the second oxidation process, the second oxidation process is performed on the channel transition layer 120 to convert the channel transition layer 120 into the second gate oxide layer 150.
In another embodiment, in the step of performing the second oxidation process, a part of the thickness of the channel transition layer may be oxidized to the second gate oxide layer. Accordingly, a partial thickness of channel transition layer oxygen may be retained between the second gate oxide layer and the first channel layer.
Referring to fig. 23, after forming the second gate oxide layer 150, the forming method further includes: in the gate opening 116, a high-k gate dielectric layer 122 is formed that conformally covers the first channel layer 101 and the second channel layer 102.
Specifically, the high-k gate dielectric layer 122 conformally covers the first gate oxide layer and the second gate oxide layer 150.
The first gate oxide layer and the high-k gate dielectric layer 122 form a first gate dielectric layer (not labeled) of the first device region 100a, and the second gate oxide layer 150 and the high-k gate dielectric layer 122 form a second gate dielectric layer (not labeled) of the second device region 100 b.
The high-k gate dielectric layer 122 is made of a high-k dielectric material, wherein the high-k dielectric material is a dielectric material having a relative dielectric constant greater than that of silicon oxide. In particular, the material of the high-k gate dielectric layer 122 may be selected from HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of (a) and (b).
With continued reference to fig. 23, after forming the high-k gate dielectric layer 122, a gate structure 125 is formed in the gate opening 116, the first through trench 117, and the second through trench 119, the gate structure 125 surrounding the first channel layer 101 in the first device region 100a exposed by the dielectric walls 107 and the second channel layer 102 in the second device region 100b exposed by the dielectric walls 107.
Specifically, the gate structure 125 surrounds the first gate dielectric layer and the second gate dielectric layer.
The gate structure 125 is used to control the conduction channels of the first-type and second-type transistors to be turned on or off during device operation.
In this embodiment, the gate structure 125 is a metal gate structure.
As an example, the step of forming the gate structure 125 includes: forming a work function layer 123 in the gate opening 116 to conformally cover the high-k gate dielectric layer 122; a gate electrode layer 124 conformally covering the work function layer 123 is formed in the remaining space of the gate opening 116, the gate electrode layer 124 crossing the first channel layer 101 and the second channel layer 102.
Note that the work function layer 123 in the first device region 100a and the second device region 100b may be formed in different steps.
The work function layer 123 is used to adjust the threshold voltage of the first type transistor or the second type transistor. In this embodiment, the work function layer 123 includes one or more of TiAl, mo, moN, alN, tiN, taN, taSiN, taAlN, tiAlN, and TiAlC. The specific material and film structure of the work function layer 123 depend on the performance of the first type transistor or the second type transistor.
Specifically, the first type transistor is an NMOS transistor, the work function layer 123 of the first device region 100a is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, mo, moN, alN, and TiAlC. The second type transistor is a PMOS transistor, the work function layer 123 of the second device region 100b is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, taN, taSiN, taAlN and TiAlN.
The gate electrode layer 124 is used for subsequent electrical connection to external structures. The material of the gate electrode layer 124 includes one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN, and TiAlC. In this embodiment, the material of the gate electrode layer 124 includes W.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (25)

1. A semiconductor structure, comprising:
a substrate including a first device region for forming a first type transistor and a second device region for forming a second type transistor, the first and second device regions being adjacent in a first direction;
a first channel structure layer extending along a second direction and located on the substrate of the second device region, wherein the first channel structure layer longitudinally comprises one or more first channel layers arranged at intervals, the first channel layer at the bottommost part is in contact with the substrate, and the second direction is perpendicular to the first direction;
the second channel structure layer is positioned on the substrate of the first device region and is arranged at intervals with the substrate, the second channel structure layer longitudinally comprises one or more second channel layers arranged at intervals, and the second channel layers and the first channel layers are arranged in a staggered manner longitudinally;
the dielectric wall extends along the second direction, is positioned on the substrate at the junction of the first device area and the second device area, and covers the side walls of the first channel structure layer and the second channel structure layer;
the first gate dielectric layer is positioned in the first device area and covers part of the top, part of the side wall and part of the bottom of the second channel layer;
the second gate dielectric layer is positioned in the second device region and covers part of the top, part of the side wall and part of the bottom of the first channel layer;
and the grid structure is positioned on the top of the substrate and stretches across the first channel structure layer, the second channel structure layer and the dielectric wall, covers partial tops of the first channel structure layer, the dielectric wall and the second channel structure layer and surrounds the first grid dielectric layer and the second grid dielectric layer.
2. The semiconductor structure of claim 1, wherein the first gate dielectric layer comprises a first gate oxide layer and a high-k gate dielectric layer conformally covering the first gate oxide layer;
the second gate dielectric layer comprises a second gate oxide layer and a high-k gate dielectric layer which conformally covers the second gate oxide layer.
3. The semiconductor structure of claim 2, further comprising: and the channel transition layer is positioned in the second device area and is positioned between the second gate oxide layer and the first channel layer.
4. The semiconductor structure of claim 3, in which a material of the channel transition layer comprises Si, si (1-X) Ge x And SiC;
wherein X represents a content of Ge in atomic percentage, the Ge concentration being in the range of 0.3 to 0.7.
5. The semiconductor structure of claim 1, wherein channel conductivity types of the first-type transistor and the second-type transistor are different.
6. The semiconductor structure of claim 1, wherein the first type transistor is an NMOS transistor and the second type transistor is a PMOS transistor; the material of the first channel layer comprises silicon germanium; the material of the second channel layer comprises silicon;
or the first device area is used for forming a PMOS transistor, and the second device area is used for forming an NMOS transistor; the material of the first channel layer comprises silicon; the material of the second channel layer includes silicon germanium.
7. The semiconductor structure of claim 2, wherein the material of the high-k gate dielectric layer comprises HfO 2 、ZrO 2 、HfSiO、HfSiON、HfTaO、HfTiO、HfZrO、Al 2 O 3 、SiO 2 And La 2 O 3 One or more of (a);
the material of the first gate oxide layer comprises SiO 2 ；
The material of the second gate oxide layer comprises SiO 2 。
8. The semiconductor structure of claim 2, wherein the first gate oxide layer has a thickness of 5 to 15 angstroms.
9. The semiconductor structure of claim 1, wherein the gate structure comprises a metal gate structure;
the metal gate structure comprises a gate electrode layer, and the material of the gate electrode layer comprises one or more of TiN, taN, ta, ti, tiAl, W, AL, tiSiN and TiAl C.
10. The semiconductor structure of claim 1, wherein the substrate comprises: the semiconductor device comprises a substrate, a fin part positioned on the substrate and an isolation layer positioned on the substrate exposed out of the fin part, wherein the isolation layer covers the side wall of the fin part;
the first channel structure layer and the second channel structure layer are both located on the fin portion.
11. The semiconductor structure of claim 10, further comprising:
the side wall is positioned at the top of the substrate and covers the side part of the grid structure;
the first gate dielectric layer also covers the top of the isolation layer of the first device region and the side wall of the side wall;
the second gate dielectric layer also covers the top of the isolation layer of the second device region and the side wall of the side wall.
12. A method of forming a semiconductor structure, comprising:
providing a substrate including a first device region for forming a first-type transistor and a second device region for forming a second-type transistor, the first and second device regions being adjacent in a first direction, the substrate having one or more longitudinally stacked channel stacks formed thereon, each channel stack including a first channel layer for providing a channel of the first-type transistor and a second channel layer on the first channel layer, the first channel layer for providing a channel of the second-type transistor, and channel materials of the first-type and second-type transistors being different;
forming a dielectric wall penetrating through the channel stack and extending along a second direction in the channel stack at the intersection of the first device region and the second device region, wherein the dielectric wall separates the channel stack in the first device region and the second device region in the first direction, and the first direction is perpendicular to the second direction;
forming a dummy gate spanning the channel stack and the dielectric wall, the dummy gate covering a portion of the top and a portion of the sidewalls of the channel stack;
removing the pseudo gate to form a gate opening;
after the dielectric wall is formed, forming a first protective layer covering the top and the side wall of the channel lamination layer in the second device area, wherein the first protective layer exposes the channel lamination layer of the first device area;
removing the first channel layer exposed from the gate opening in the first device region by using the first protective layer as a mask to form a first through groove communicated with the gate opening;
after the first through groove is formed, forming a second protective layer covering the gate opening and the second channel layer exposed from the first through groove in the first device area;
removing the first protection layer and the second channel layer exposed by the gate opening in the second device region by using the second protection layer as a mask to form a second through groove communicated with the gate opening;
forming a gate structure in the gate opening, the first through trench and the second through trench, the gate structure surrounding a first channel layer in the first device region exposed by the dielectric wall and a second channel layer in the second device region exposed by the dielectric wall.
13. The method of forming a semiconductor structure of claim 12, wherein in the step of providing a substrate, the first-type transistor and the second-type transistor have different channel conductivity types.
14. The method of forming a semiconductor structure of claim 12, wherein the first protective layer is formed on top and sidewalls of the channel stack and on top of the substrate in the second device region after forming the dielectric walls and before forming the dummy gate.
15. The method of forming a semiconductor structure of claim 12 or 14, wherein forming the first protective layer on top and sidewalls of the channel stack and on top of the base in the second device region comprises:
forming a layer of protective material in the first and second device regions covering the top and sidewalls of the channel stack and the top of the substrate;
and removing the protective material layer in the first device area, wherein the protective material layer remained in the second device area is used as the protective layer.
16. The method of forming a semiconductor structure of claim 14, wherein after forming the first protective layer and before forming the dummy gate, further comprising: forming a dummy gate oxide layer covering the top and the side wall of the channel lamination layer in the first device area;
in the step of forming the first through trench, before removing the first channel layer in the channel stack exposed by the first device region, the method further includes: and removing the pseudo gate oxide layer.
17. The method of forming a semiconductor structure of claim 12, wherein in the step of forming the first protective layer, the material of the first protective layer comprises one or more of silicon nitride, silicon oxynitride, silicon carbide, and silicon oxycarbide.
18. The method of forming a semiconductor structure of claim 12, wherein forming the second protective layer comprises: and in the first device area, carrying out first oxidation treatment on the second channel layer exposed from the gate opening and the first through groove to form a first gate oxide layer covering each surface of the second channel layer, wherein the gate oxide layer is used as the second protective layer.
19. The method of forming a semiconductor structure of claim 11, wherein after forming the second through trench and before forming the gate structure, further comprising: and carrying out second oxidation treatment on the first channel layer exposed from the gate opening and the second through groove to form a second gate oxide layer covering each surface of the first channel layer.
20. The method of forming a semiconductor structure of claim 19, wherein after forming said second trench, prior to forming said second gate oxide layer, further comprising: forming a channel transition layer conformally covering each surface of the first channel layer in the second device region;
and in the step of performing the second oxidation treatment, performing the second oxidation treatment on the channel transition layer, and oxidizing the channel transition layer or the channel transition layer with a part of thickness into the second gate oxide layer.
21. The method of forming a semiconductor structure of claim 20, wherein the process of forming the channel transition layer comprises an atomic layer deposition process.
22. The method of forming a semiconductor structure of claim 20, wherein in the step of forming the channel transition layer, the material of the channel transition layer comprises Si, si (1-X) Ge x And SiC; wherein X represents a content of Ge in atomic percentage, the Ge concentration being in the range of 0.3 to 0.7.
23. The method of forming a semiconductor structure of claim 20, wherein in the step of forming the channel transition layer, the channel transition layer has a thickness of 20 to 200 angstroms.
24. The method of forming a semiconductor structure of claim 12, wherein the first type transistor is used to form an NMOS transistor and the second type transistor is used to form a PMOS transistor;
the material of the first channel layer comprises silicon germanium; the material of the second channel layer includes silicon;
or the first type transistor is used for forming a PMOS transistor, and the second type transistor is used for forming an NMOS transistor; the material of the first channel layer comprises silicon; the material of the second channel layer includes silicon germanium.
25. The method for forming a semiconductor structure according to claim 12, wherein in the step of forming the first protective layer, the first protective layer has a thickness of 10 to 30 angstroms;
in the step of forming the second protective layer, a thickness of the second protective layer is 10 to 50 angstroms.
CN202110420045.4A 2021-04-19 2021-04-19 Semiconductor structure and forming method thereof Pending CN115224027A (en)

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