WO2013082774A1 - 一种阵列基板及液晶显示装置、阵列基板的制造方法 - Google Patents

一种阵列基板及液晶显示装置、阵列基板的制造方法 Download PDF

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WO2013082774A1
WO2013082774A1 PCT/CN2011/083655 CN2011083655W WO2013082774A1 WO 2013082774 A1 WO2013082774 A1 WO 2013082774A1 CN 2011083655 W CN2011083655 W CN 2011083655W WO 2013082774 A1 WO2013082774 A1 WO 2013082774A1
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Prior art keywords
data line
width
array substrate
line
intersection
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French (fr)
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陈虹瑞
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/380,875 priority Critical patent/US20130140712A1/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Definitions

  • the present invention relates to the field of liquid crystal display, and more particularly to an array substrate, a liquid crystal display device, and a method of fabricating an array substrate.
  • the existing array substrate is generally fabricated by an etching process, and sequentially scans the scan lines and the data lines on the transparent substrate in layers, as shown in FIGS. 1 and 2, and includes a plurality of thin film transistors (TFTs) in the array substrate of the liquid crystal display device.
  • TFTs thin film transistors
  • a thin film transistor includes a substrate, a gate and a source, the gate is connected to the scan line, and the source is connected to the data line.
  • the line width of the data line after the wet etching process becomes smaller or even broken, causing vertical disconnection or vertical line defects, which affects the yield.
  • the technical problem to be solved by the present invention is to provide an array substrate, a liquid crystal display device, and a method of manufacturing an array substrate which are less prone to data line breakage.
  • An array substrate includes scan lines and data lines, the width of the data lines at the intersection of the data lines and the scan lines being greater than the width of the remainder of the data lines.
  • the data lines are equal in width at both sides of the intersection.
  • the intensity received on both sides of the data line is equal, so the width is kept equal, and the width of the data line is uniform after the exposure and etching processes, and there is no local narrowing or even disconnection.
  • the widened width of the data line on one side of the intersection is between 0.3 um and 0.7 um.
  • the data line width at the junction should not be too large. The larger the width, the larger the overlap area between the data line and the scan line. The more easily the junction is broken when the static electricity is generated on the array substrate, the sides are widened by 0.5um. After exposure, wet etching, etc., the data line width at the junction can be approximately the same as the width of other parts, and the overlap area of the junction can be reduced under the premise of ensuring reliable connection.
  • the widened width of the data line on one side of the intersection is 0.5 um. This is a preferred broadening value.
  • a liquid crystal display device comprising the above array substrate.
  • a method for manufacturing an array substrate comprising the steps of: setting a data line width parameter in a data line forming process of the array substrate such that a data line width value at a junction of the data line and the scan line is greater than a width value of a remaining portion of the data line.
  • the width of the widened width of the data lines on both sides of the intersection is equal.
  • the intensity received on both sides of the data line is equal, so the width is kept equal, and the width of the data line is uniform after the exposure and etching processes, and there is no local narrowing or even disconnection.
  • the widened width of the data line on one side of the intersection is between 0.3 um and 0.7 um.
  • the data line width at the junction should not be too large. The larger the width, the larger the overlap area between the data line and the scan line. The more easily the junction is broken when the static electricity is generated on the array substrate, the sides are widened by 0.5um. After exposure, wet etching, etc., the data line width at the junction can be approximately the same as the width of other parts, and the overlap area of the junction can be reduced under the premise of ensuring reliable connection.
  • the widened width value of the data line on one side of the intersection is 0.5 um. This is a preferred broadening value.
  • the inventors have found that when the existing array substrate is etched out of the data line, the data line is narrowed or even the disconnected portion is concentrated at the intersection of the data line and the scan line, and the data line needs to be climbed due to the data line. Crossing the scan line, it is easy to over-exposure at the climbing stage during the exposure process, resulting in a narrower data line width (CD) at the climb, and the line width becomes smaller or even broken after the wet etching process.
  • the invention widens the data line at the junction, and the data line at the junction is processed by exposure, wet etching, etc., and in the case of reduced width, the width can still be maintained, and the width is not too narrow. line.
  • the invention can solve the problem that the line width of the data line is narrowed or even broken without adding an additional process, and the yield rate of the liquid crystal display device is improved, the process cylinder is simple, and the cost is low.
  • FIG. 1 is a schematic diagram of a prior art liquid crystal display device array substrate
  • FIG. 2 is a schematic diagram of a data line at a junction in an exposure process
  • FIG. 3 is a schematic view of an array substrate of a liquid crystal display device of the present invention.
  • a liquid crystal display device includes an array substrate, the array substrate includes a plurality of thin film transistors 4, a scan line connecting the gates of the thin film transistors 4, and a data line 2 connecting the sources of the thin film transistors 4,
  • the width of the data line 2 at the intersection 3 of the data line 2 and the scan line 1 is greater than the width of the rest of the data line 2. Further, the widened width of the data lines 2 on both sides of the intersection 3 is equal.
  • the intensity received on both sides of the data line 2 is equal, so that the width is kept equal, and the width of the data line 2 is uniform after the exposure and etching processes, and local narrowing or even disconnection does not occur.
  • the widened width of the data line 2 on one side of the junction 3 is between 0.3 um and 0.7 um.
  • the width of the data line 2 at the junction 3 should not be too large.
  • the larger the width the larger the overlapping area of the data line 2 and the scanning line 1.
  • the data line 2 is widened by 0.5 um on both sides of the junction 3.
  • the width of the data line 2 of the junction 3 can be substantially the same as the width of other parts, and a reliable connection can be ensured. Under the premise, reduce the overlap area of the junction 3.
  • the method for manufacturing the above array substrate includes the following steps:
  • the data line 2 width parameter is set such that the data line 2 width value at the intersection of the data line 2 and the scan line 1 is greater than the width value of the remaining portion of the data line 2.
  • the widened width values of the data lines 2 on both sides of the intersection 3 are equal.
  • the intensity received on both sides of the data line 2 is equal, so that the width is kept equal, and the width of the data line 2 is hooked after the exposure and etching processes, and local narrowing or even disconnection does not occur.
  • the widened width value of the data line 2 on one side of the junction 3 is Between 0.3um ⁇ 0.7um.
  • the width of the data line 2 of the junction 3 should not be too large. The larger the width, the larger the overlapping area of the data line 2 and the scanning line 1.
  • the junction 3 is more likely to be broken when the array substrate generates static electricity.
  • Each width is 0.5um. After the exposure, wet etching, etc., the width of the data line 2 of the junction 3 can be substantially the same as the width of other parts, and the overlapping area of the junction 3 can be reduced under the premise of ensuring reliable connection. .
  • the inventors have found that when the existing array substrate is etched out of the data line 2, the data line 2 is narrowed or even the broken portion is concentrated at the intersection 3 of the data line 2 and the scanning line 1, and the intersection 3 Since the data line 2 needs to climb the slope across the scan line 1, it is easy to over-exposure at the climbing stage during the exposure process, causing the data line 2 line width (CD) to be reduced at the climb, and the line width becomes after the wet etching process.
  • CD data line width
  • the present invention widens the data line 2 at the junction 3, and the data line 2 of the junction 3 is processed by exposure, wet etching, etc., and in the case of a reduced width, the final Keep the width so good that it won't break because the width is too narrow.
  • the invention can solve the problem that the data line 2 line width is narrowed or even broken without adding an additional process, and the yield rate of the liquid crystal display device is improved, the process tube is simple, and the cost is low.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及液晶显示装置。该液晶显示装置包括阵列基板。阵列基板包括扫描线（1）和数据线（2），所述数据线（2）在数据线（2）和扫描线（1）的交接处的宽度大于数据线（2）其余部分的宽度。还提供了一种阵列基板的制造方法，包括步骤在阵列基板的数据线（2）成型工艺中，设置数据线（2）宽度参数，使数据线（2）与扫描线（1）交接处的数据线（2）宽度值大于数据线（2）其余部分的宽度值。该阵列基板可以在不增加额外工序的前提下提升液晶显示装置的良品率，工艺简单，成本低廉。

Description

一种阵列基板及液晶显示装置、 阵列基板的制造方法
【技术领域】
本发明涉及液晶显示领域， 更具体的说， 涉及一种阵列基板及液晶显示装 置、 阵列基板的制造方法。
【背景技术】
现有的阵列基板一般采用蚀刻工艺制作， 依次在透明基板上分层依次蚀刻 出扫描线和数据线， 如图 1、 2所示， 在液晶显示装置的阵列基板中包括多个薄 膜晶体管 （TFT ), —个薄膜晶体管包括一个基板、 一个闸极和一个源极， 闸极 连接扫描线， 源极连接数据线。 在现有的阵列基板中， 湿式蚀刻制程后数据线 的线线宽会变小甚至断线， 造成垂直断线或垂直线缺陷， 影响良品率。
【发明内容】
本发明所要解决的技术问题是提供一种不易出现数据线断线的阵列基板及 液晶显示装置、 阵列基板的制造方法。
本发明的目的是通过以下技术方案来实现的：
一种阵列基板， 包括扫描线和数据线， 所述数据线在数据线和扫描线的交 接处的宽度大于数据线其余部分的宽度。
优选的， 所述数据线在交接处两侧的加宽宽度相等。 在曝光、 蚀刻过程中 数据线两侧受到的强度是对等的， 因此保持加宽宽度相等， 在曝光、 蚀刻过程 后数据线的宽度均匀， 不会出现局部收窄甚至断线。
优选的， 所述数据线在交接处单侧的加宽宽度在 0.3um~0.7um之间。 交接 处的数据线宽度不宜过大， 宽度越大， 数据线和扫描线的交叠面积就越大， 在 阵列基板产生静电的时候交接处就越容易被击穿， 两侧各加宽 0.5um, 在经过曝 光、 湿式蚀刻等制程后， 交接处的数据线宽度可以跟其他部分的宽度大致保持 一致， 可以保证可靠连接的前提下， 减少交接处的交叠面积。 优选的， 所述数据线在交接处单侧的加宽宽度为 0.5um。此为优选的加宽数 值。
一种液晶显示装置， 包括上述的阵列基板。
一种阵列基板的制造方法， 其步骤包括： 在阵列基板的数据线成型工艺中， 设置数据线宽度参数， 使数据线与扫描线交接处的数据线宽度值大于数据线其 余部分的宽度值。
优选的， 所述数据线在交接处两侧的加宽的宽度值相等。 在曝光、 蚀刻过 程中数据线两侧受到的强度是对等的， 因此保持加宽宽度相等， 在曝光、 蚀刻 过程后数据线的宽度均匀， 不会出现局部收窄甚至断线。
优选的， 所述数据线在交接处单侧的加宽的宽度值在 0.3um~0.7um之间。 交接处的数据线宽度不宜过大， 宽度越大， 数据线和扫描线的交叠面积就越大， 在阵列基板产生静电的时候交接处就越容易被击穿， 两侧各加宽 0.5um, 在经过 曝光、 湿式蚀刻等制程后， 交接处的数据线宽度可以跟其他部分的宽度大致保 持一致， 可以保证可靠连接的前提下， 减少交接处的交叠面积。
优选的， 所述数据线在交接处单侧的加宽的宽度值为 0.5um。 此为优选的加 宽数值。
本发明中， 发明人研究发现现有的阵列基板在蚀刻出数据线时， 数据线变 窄甚至于断线的部位集中在数据线和扫描线的交接处， 该交接处由于数据线需 爬坡跨越扫描线， 容易于在曝光制程时爬坡处曝光量过大， 造成爬坡处数据线 线宽 (CD)缩小， 而于湿式蚀刻制程后线宽变得更小甚至断线， 为此， 本发明在 交接处加宽了数据线， 交接处的数据线在经过曝光、 湿式蚀刻等制程的加工， 在宽度减少的情况下， 最终仍然可以保持合适的宽度， 不至于因为宽度太窄造 成断线。 本发明可以在不增加额外工序的前提下解决数据线线宽变窄甚至断线 的问题， 提升了液晶显示装置的良品率， 工艺筒单， 成本低廉。
【附图说明】 图 1现有技术的液晶显示装置阵列基板示意图
图 2是交接处数据线在曝光制程中的示意图；
图 3是本发明液晶显示装置阵列基板示意图；
其中： 1、 扫描线； 2、 数据线； 3、 交接处； 4 薄膜晶体管。
【具体实施方式】
下面结合附图和较佳的实施例对本发明作进一步说明。
如图 3所示， 一种液晶显示装置， 包括阵列基板， 所述阵列基板包括多个 薄膜晶体管 4, 连接薄膜晶体管 4闸极的扫描线 1、 连接薄膜晶体管 4源极的数 据线 2,所述数据线 2在数据线 2和扫描线 1的交接处 3的宽度大于数据线 2其 余部分的宽度。 进一步的， 所述数据线 2在交接处 3两侧的加宽宽度相等。 在 曝光、 蚀刻过程中数据线 2两侧受到的强度是对等的， 因此保持加宽宽度相等， 在曝光、 蚀刻过程后数据线 2的宽度均匀， 不会出现局部收窄甚至断线。
进一步的，所述数据线 2在交接处 3单侧的加宽宽度在 0.3um~0.7um之间。 交接处 3的数据线 2宽度不宜过大， 宽度越大， 数据线 2和扫描线 1的交叠面 积就越大， 在阵列基板产生静电的时候交接处 3 就越容易被击穿， 进一步的， 所述数据线 2在交接处 3两侧各加宽 0.5um, 在经过曝光、 湿式蚀刻等制程后， 交接处 3的数据线 2宽度可以跟其他部分的宽度大致保持一致， 可以保证可靠 连接的前提下， 减少交接处 3的交叠面积。
上述阵列基板的制造方法， 其步骤包括：
在阵列基板的数据线 2成型工艺中， 设置数据线 2宽度参数， 使数据线 2 与扫描线 1交接处 3的数据线 2宽度值大于数据线 2其余部分的宽度值。
进一步的， 在置数据线 2宽度参数时， 所述数据线 2在交接处 3两侧的加 宽的宽度值相等。 在曝光、 蚀刻过程中数据线 2 两侧受到的强度是对等的， 因 此保持加宽宽度相等， 在曝光、 蚀刻过程后数据线 2 的宽度均勾， 不会出现局 部收窄甚至断线。 对应的， 所述数据线 2 在交接处 3 单侧的加宽的宽度值在 0.3um~0.7um之间。 交接处 3的数据线 2宽度不宜过大， 宽度越大， 数据线 2 和扫描线 1的交叠面积就越大， 在阵列基板产生静电的时候交接处 3就越容易 被击穿， 两侧各加宽 0.5um, 在经过曝光、 湿式蚀刻等制程后， 交接处 3的数据 线 2 宽度可以跟其他部分的宽度大致保持一致， 可以保证可靠连接的前提下， 减少交接处 3的交叠面积。
本发明中， 发明人研究发现现有的阵列基板在蚀刻出数据线 2时， 数据线 2 变窄甚至于断线的部位集中在数据线 2和扫描线 1的交接处 3 ,该交接处 3由于 数据线 2需爬坡跨越扫描线 1 , 容易于在曝光制程时爬坡处曝光量过大， 造成爬 坡处数据线 2线宽 (CD)缩小， 而于湿式蚀刻制程后线宽变得更小甚至断线， 为 此， 本发明在交接处 3加宽了数据线 2, 交接处 3的数据线 2在经过曝光、 湿式 蚀刻等制程的加工， 在宽度减少的情况下， 最终仍然可以保持合适的宽度， 不 至于因为宽度太窄造成断线。 本发明可以在不增加额外工序的前提下解决数据 线 2线宽变窄甚至断线的问题， 提升了液晶显示装置的良品率， 工艺筒单， 成 本低廉。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明， 不 能认定本发明的具体实施只局限于这些说明。 对于本发明所属技术领域的普通 技术人员来说， 在不脱离本发明构思的前提下， 还可以做出若干筒单推演或替 换， 都应当视为属于本发明的保护范围。

Claims

权利要求
1、 一种阵列基板， 包括： 扫描线和数据线， 所述数据线在数据线和扫 描线的交接处的宽度大于数据线其余部分的宽度。
2、 如权利要求 1所述的一种阵列基板， 所述数据线在交接处两侧的加 宽宽度相等。
3、 如权利要求 1或 2所述的一种阵列基板， 所述数据线在交接处单侧 的加宽宽度在 0.3um~0.7um之间。
4、 如权利要求 3所述的一种阵列基板， 所述数据线在交接处单侧的加 宽宽度为 0.5um。
5、 一种液晶显示装置， 包括如权利要求 1所述的一种阵列基板， 所述 阵列基板包括： 扫描线和数据线， 所述数据线在数据线和扫描线的交接处 的宽度大于数据线其余部分的宽度。。
6、 如权利要求 5所述的一种阵列基板， 所述数据线在交接处两侧的加 宽宽度相等。
7、 如权利要求 5或 6所述的一种阵列基板， 所述数据线在交接处单侧 的加宽宽度在 0.3um~0.7um之间。
8、 如权利要求 7所述的一种阵列基板， 所述数据线在交接处单侧的加 宽宽度为 0.5um。
9、 一种阵列基板的制造方法， 其步骤包括： 在阵列基板的数据线成型 工艺中， 设置数据线宽度参数， 使数据线与扫描线交接处的数据线宽度值 大于数据线其余部分的宽度值。
10、 如权利要求 9所述的一种阵列基板的制造方法， 所述数据线在交 接处两侧的加宽的宽度值相等。
11、 如权利要求 9或 10所述的一种阵列基板的制造方法， 所述数据线 在交接处单侧的加宽的宽度值在 0.3um~0.7um之间。
12、 如权利要求 9所述的一种阵列基板的制造方法， 所述数据线在交 接处单侧的加宽的宽度值为 0.5um。
PCT/CN2011/083655 2011-12-05 2011-12-07 一种阵列基板及液晶显示装置、阵列基板的制造方法 Ceased WO2013082774A1 (zh)

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US13/380,875 US20130140712A1 (en) 2011-12-05 2011-12-07 Array Substrate, LCD Device, and Method for Manufacturing Array Substrate

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CN114442387B (zh) 2020-10-30 2025-04-22 京东方科技集团股份有限公司 阵列基板及其制造方法、显示装置
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