WO2013075506A1 - 一种显示面板栅驱动电路及显示屏 - Google Patents

一种显示面板栅驱动电路及显示屏 Download PDF

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Publication number
WO2013075506A1
WO2013075506A1 PCT/CN2012/078236 CN2012078236W WO2013075506A1 WO 2013075506 A1 WO2013075506 A1 WO 2013075506A1 CN 2012078236 W CN2012078236 W CN 2012078236W WO 2013075506 A1 WO2013075506 A1 WO 2013075506A1
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WIPO (PCT)
Prior art keywords
gate
signal
shift register
circuit
unit
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PCT/CN2012/078236
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English (en)
French (fr)
Inventor
游帅
李洪
马骏
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上海天马微电子有限公司
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Application filed by 上海天马微电子有限公司 filed Critical 上海天马微电子有限公司
Priority to EP12839166.1A priority Critical patent/EP2784770B1/en
Priority to KR1020137011977A priority patent/KR101475243B1/ko
Publication of WO2013075506A1 publication Critical patent/WO2013075506A1/zh
Priority to US13/936,082 priority patent/US9418606B2/en

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/04—Partial updating of the display screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/10—Special adaptations of display systems for operation with variable images
    • G09G2320/103—Detection of image changes, e.g. determination of an index representative of the image change
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/16—Determination of a pixel data signal depending on the signal applied in the previous frame

Definitions

  • the present invention relates to the field of liquid crystal display (LCD) technology, and in particular, to a display panel gate driving circuit and a display screen.
  • LCD liquid crystal display
  • Figure 1 shows the Gate wiring scheme of the GIP circuit in the prior art.
  • the GIP utilizes repeatable units (i.e., Units shown in the figure, such as Un, Un+1, Un+2, Un+3, etc.) and less.
  • the peripheral wiring can save a lot of space in the periphery, adapting to the light and thin development of the screen.
  • GIP circuit structure eliminates a large amount of peripheral wiring, it is difficult to address it.
  • ASG amorphous silicon gate drive
  • the addressing circuit is actually a decoder, that is, for different address lines. Different 0, 1 values, the output of the Gate signal has one and only one way is true.
  • an 800-line Gate line needs to add 10 more address lines for addressing, and at least 10 PMOSs are required for each line of Gate lines. Or NMOS tube is strobed.
  • prior art amorphous silicon materials do not have suitable implementations to implement such decoding circuits.
  • the ASG circuit that is, the ordinary amorphous silicon circuit is also not suitable for PMOS, and the circuit performance is not high, so it is very difficult to realize decoding.
  • the embodiment of the invention provides a display panel gate driving circuit for more conveniently addressing the Gate signal, avoiding the cumbersome use of the decoding circuit, occupying a smaller circuit area, saving cost, and improving the addressing speed.
  • a display panel gate driving circuit and a display screen are provided for driving a gate line disposed on a display panel, wherein the display panel gate driving circuit includes a shift register and a plurality of gate enabling units.
  • the shift register includes at least two stages of shift register units, and a gate signal output end of each of the shift register units is connected to a gate enable unit input end, and an output end of the gate enable unit is coupled to a
  • the gate line is connected, the gate enable unit further has an enable signal input end, and the gate enable unit controls the shift register unit by using an enable signal received by the enable signal input end. Whether a gate signal output from the gate signal output is transmitted to the gate line.
  • a display screen provided by an embodiment of the invention includes the display panel gate driving circuit.
  • the above display panel gate driving circuit provided by the embodiment of the invention realizes a GIP circuit capable of more conveniently addressing the Gate signal, thereby avoiding the cumbersome use of the decoding circuit, occupying a smaller circuit area, and saving cost, and It can improve the addressing speed and is suitable for amorphous silicon materials.
  • FIG. 1 is a schematic structural view of a GIP circuit in the prior art
  • FIG. 2 is a schematic structural diagram of an addressing circuit in the prior art
  • FIG. 3 is a schematic structural diagram of a GIP circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a GIP circuit according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of an integrated circuit according to an embodiment of the present invention.
  • FIG. 6 is a schematic diagram of a shift register unit in a GIP circuit according to an embodiment of the present invention
  • FIG. 7 is a timing waveform diagram of a GIP circuit according to an embodiment of the present invention
  • FIG. 8 is a first embodiment of the present invention.
  • FIG. 9 is a schematic diagram of determining a non-scanning area according to an embodiment of the present invention. 10 is a schematic diagram of clock signals and enable signals of different frequencies when a GIP circuit performs gate signal addressing according to an embodiment of the present invention;
  • FIG. 11 is a schematic structural diagram of a shift register unit and a gate enable unit according to Embodiment 2 of the present invention.
  • FIG. 12 is a schematic structural diagram of a comparison circuit according to an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a gating circuit according to an embodiment of the present invention.
  • the embodiment of the invention provides a display panel gate driving circuit and a display screen for more conveniently addressing the Gate signal, avoiding the cumbersome use of the decoding circuit, occupying a smaller circuit area, saving cost, and improving the addressing speed. .
  • the embodiment of the present invention mainly implements Gate addressing by adding a GIP peripheral circuit, and thus the embodiment of the present invention is not directed to a specific GIP circuit and a specific GIP circuit configuration.
  • a display panel gate driving circuit for driving a gate line disposed on a display panel, and the display panel gate driving circuit includes:
  • each shift register unit is connected to a corresponding gate enable unit, and each gate enable unit constitutes a Gate EN CIRDUIT (gate enable circuit) as shown in FIG.
  • the shift register unit includes at least two stages of shift register units. Referring to FIG. 4, a gate signal output end of each of the shift register units is connected to a gate enable unit input, and the gate is enabled. The output end of the unit is connected to a gate line, the gate enable unit further has an enable signal input end, and the enable signal received by the gate enable unit through the enable signal input terminal is controlled by the control unit. Whether a gate signal outputted from a gate signal output terminal of the shift register unit is transferred to the gate line.
  • the display panel gate driving circuit further includes:
  • An integrated circuit IC that provides an enable signal to the gate enable unit.
  • the integrated circuit IC includes a comparison circuit, and the comparison circuit compares image information of all pixels in the same row of adjacent frame images that need to be displayed through the display panel, and The comparison result is output as an enable signal to the enable of the gate enable unit Signal input.
  • the enable signal causes the gate signal outputted by the gate signal output end of the shift register unit not to be transmitted to the The gate line, that is, the image data of the row is not refreshed; if the image information of one pixel in the same row of the adjacent frame image is different, the enable signal causes the gate signal of the shift register unit to be output
  • the gate signal outputted by the terminal is transmitted to the gate line, that is, the image data of the row is refreshed.
  • the integrated circuit IC further includes:
  • a gating circuit for providing a clock signal for each stage of the shift register unit
  • a reset circuit for providing a reset signal (RESET) for each stage shift register unit; a first trigger circuit for providing a first trigger signal (STV1) to the first stage shift register unit, wherein the first trigger The signal is a signal for triggering operation of the first stage shift register unit.
  • the strobe circuit provides different clock signals to the shift register units of the stages according to a comparison result of the comparison circuit.
  • the reset signal (RESET) of each stage of the shift register unit in Fig. 5 is only a preferred embodiment, and does not constitute a limitation of the present invention.
  • the output of the next stage can be reset to the previous stage.
  • CK and CKB appear in pairs, but this is only a preferred embodiment, and does not constitute a limitation on the present invention, and may not be in pairs.
  • the signal Gn from the shift register unit of the nth stage triggers the operation of the n+1th shift register unit
  • CK and CKB is its clock signal
  • RESET is its reset signal
  • CK, CKB, and RESET are all provided by the integrated circuit IC.
  • the signal outputted by the n+1th stage shift register unit is Gn+1, which is used to trigger the operation of the n+2th stage shift register unit, and is also transmitted to the corresponding scan line as needed.
  • the first stage shift register unit it is triggered by the first trigger signal STV1 provided by the integrated circuit IC.
  • the gating circuit provides the first clock signal (CK1, CKB1) to the shift register units of each level;
  • the image information of one pixel in the same row of the frame image is different, the gate circuit provides a second clock signal (CK2, CKB2) to the register units of the stages, the frequency of the first clock signal is higher than The frequency of the second clock signal, that is, the frequency of CK1 is greater than the frequency of CK2; the frequency of CKB1 is large The frequency of CKB2.
  • the principle of the GIP circuit is to use a logic signal line to transmit a specific waveform signal generated by an integrated circuit (IC), and then generate a Gate signal output in a shift register unit (also referred to as a repeatable unit), thereby performing step-by-step triggering, such as As shown in FIG. 7, the Gate signal Gn generated by the nth stage shift register unit triggers the n+1th stage shift register unit, and the n+1th stage shift register unit generates the Gate signal Gn+1.
  • the speed of the Gate scan the speed of the device, and the frequency of the control signal.
  • the scanning speed of the Gate can be changed by changing the frequency of the clock signal within the tolerance range of the device, wherein the clock signal generally refers to an input signal with various waveforms, for example, in FIG.
  • the illustrated clock signals CK and CKB, etc. are not a single clock signal in a narrow sense.
  • a gate enabling unit connected to each shift register unit includes two N-type thin film field effect transistors TFT, wherein:
  • a gate signal output terminal of the shift register unit is connected to a source of the first thin film field effect transistor TFT, a drain of the first TFT is connected to a source of the second TFT, and serves as an output end of the gate enable unit,
  • the gate of the first TFT is provided with an enable signal EN by the integrated circuit IC
  • the gate of the second TFT is provided with a reverse enable signal ENB by the integrated circuit IC
  • the drain of the second TFT is provided with a gate low level by the integrated circuit IC Voltage signal VGL.
  • the enable signal EN outputted to the gate of the first TFT by the integrated circuit IC is a high level signal
  • the reverse enable signal ENB outputted by the integrated circuit IC to the gate of the second TFT is a low level signal.
  • the first TFT is turned on, the second TFT is turned off, the drain of the first TFT outputs a gate signal, and the gate signal is output through the output end of the gate enable unit;
  • the enable signal EN outputted to the gate of the first TFT by the integrated circuit IC is a low level signal
  • the reverse enable signal ENB outputted by the integrated circuit IC to the gate of the second TFT is a high level signal
  • the first The TFT is turned off, the second TFT is turned on, and the integrated circuit IC outputs a VGL signal to the drain of the second TFT, and the VGL signal is output through the output terminal of the gate enable unit.
  • EN and ENB are provided by the IC and are ordinary digital signals.
  • EN When EN is high and ENB is low, the TFT tube controlled by EN is turned on, and the TFT tube controlled by ENB is turned off. At this time, the Gate line will have a loss.
  • EN When EN is low and ENB is high, EN controls the TFT tube to turn off, and the ENB controlled TFT turns on, causing Gate to lock at VGL (gate low level voltage), that is, no output.
  • the image area that is not to be scanned can be skipped at a faster speed, and then the frequency of the clock signal is reduced, and the input is matched with the input.
  • the enable signal of the gate enable unit is used to perform scanning of a designated area of the image to achieve an address scanning purpose.
  • two pictures ie, the current display picture and the refresh picture
  • the current display picture and the refresh picture can be compared, thereby obtaining the number of lines of the image area that needs to be skipped, that is, the behavior of G3 to Gn-1.
  • the non-scanned area of the image As shown in FIG. 9, before the display refresh process, two pictures (ie, the current display picture and the refresh picture) can be compared, thereby obtaining the number of lines of the image area that needs to be skipped, that is, the behavior of G3 to Gn-1.
  • the non-scanned area of the image is not limited to the image.
  • the frequencies of the clock signals CK and CKB are lower. After the G2 line, the frequency of CK and CKB is accelerated before the image area of the desired scan display is reached, which will be enabled.
  • the signal EN is set low and the enable signal ENB is set high, which causes the Gate to perform a fast scan (SKIP process in the figure). During this process, the Gate is not subject to the EN and ENB signals, so there is no output.
  • the specified scan position of the image is reached, for example, when the nth row is gated, the signal frequency of CK and CKB is restored, the EN enable signal is set to a high level, and the enable signal ENB is set to a low level, and the image designated area is refreshed. .
  • the above gate enable unit structure is for an amorphous silicon thin film field effect transistor (a-si TFT), but for a low temperature polysilicon thin film field effect transistor (LTPS-TFT) process, a structure can still be provided.
  • a-si TFT amorphous silicon thin film field effect transistor
  • LTPS-TFT low temperature polysilicon thin film field effect transistor
  • the EN and ENB signals can be combined into one to become a uniform enable signal EN.
  • the P-type thin film field effect transistor TFT i.e., T1 shown in Fig. 11
  • the N-type thin film field effect transistor TFT i.e., T2 shown in Fig. 11
  • the gate enable unit connected to each shift register unit includes a P-type thin film field effect transistor TFT and an N-type thin film field effect transistor TFT, wherein:
  • the gate of the field effect transistor TFT is each provided with an enable signal EN by the integrated circuit IC; the source of the N-type thin film field effect transistor TFT is supplied with a gate low level voltage signal VGL by the integrated circuit IC.
  • the integrated circuit IC When the integrated circuit IC outputs the enable signal EN of the gate of the P-type thin film field effect transistor TFT and the gate of the N-type thin film field effect transistor TFT to a high level signal, the P-type thin film field effect transistor TFT is turned on, N The thin film field effect transistor TFT is disconnected, and the drain of the P-type thin film field effect transistor TFT outputs a gate signal, and the gate signal is output through the output end of the gate enable unit;
  • the integrated circuit IC When the integrated circuit IC outputs the enable signal EN of the gate of the P-type thin film field effect transistor TFT and the gate of the N-type thin film field effect transistor TFT to a low level signal, the N-type thin film field effect transistor TFT is turned on, P The thin film field effect transistor TFT is turned off, and the integrated circuit IC outputs the VGL signal to the source of the N-type thin film field effect transistor TFT, and the VGL signal is output through the output terminal of the gate enable unit.
  • the initial trigger signal can be derived in some shift register units, as shown in Figure 3, between Un+1 and Un+2.
  • an additional N trigger signal STV2 line can reduce the average addressing time to 1/N, but it also has the consequence of increasing the occupied area. Therefore, the speed is required in the specific design. Balance with area.
  • the maximum time required for fast scanning is 400T, where T is a fast scan, and each gate is averaged. Occupied scan time.
  • the integrated circuit IC further includes:
  • a second trigger circuit for providing a second trigger signal (STV2) to the selected shift register unit, wherein the second trigger signal is a signal for triggering operation of the selected shift register unit.
  • STV2 second trigger signal
  • a comparison circuit in an integrated circuit includes a future frame list.
  • the comparison circuit While the screen is being displayed, the comparison circuit stores the picture being displayed and the picture to be displayed, respectively, in the current frame unit and the future frame unit as shown in FIG. Then, during the display interval of the preceding and following lines, the two pictures are compared, and the area to be scanned is stored in a binary form in a memory (generally a register), that is, the sequence scan area truth table shown in FIG. In the unit.
  • a memory generally a register
  • the future frame unit, the current frame unit, and the scan-area truth table unit are all memories.
  • the capacity of the current frame unit and the future frame unit are the same as the picture size, and the size of the scan area truth table unit is related to the number of gates. If the number of poles is 800, the area to be scanned must be set to 800*1 registers, that is, 800 1-bit registers.
  • the comparison circuit can be expressed in the verilog language.
  • the data to be scanned for each line of the current frame and the future frame is introduced to the comparison circuit, and the data streams of 0 and 1 are output, and then the 0 and 1 shifts are stored in the area to be scanned.
  • the value table unit In the value table unit.
  • the gating circuit in the integrated circuit provided by the embodiment of the present invention is as shown in FIG. 13, and may be, for example, a common 2-to-1 multiplexer, and the circuit characteristics thereof may also be described in verilog language, and may be outputted at each output.
  • the value of the truth region table to be scanned in the comparison circuit ie, the comparison result of the comparison circuit
  • the clock signal outputted from the output terminal of the gate circuit can be at CK1.
  • CKB1, and CK2, CKB2 switch thus adjusting the frequency of the output clock signal, and introducing this clock signal into the GIP circuit, the variable frequency drive can be realized.
  • a display screen provided by an embodiment of the present invention may include the above various display panel gate driving circuits.
  • the display panel gate driving circuit provided by the embodiment of the present invention can realize the variable frequency driving GIP addressing by adding a small number of address lines and control lines, and the initial trigger signal line is added in the GIP structure, thereby further Increased addressing speed.
  • the implementation of the addressing does not need to be decoded on the panel, that is, the decoding circuit is not required, the decoding circuit is omitted, and the smaller area is occupied, which is suitable for the amorphous silicon material.
  • the technical solution provided by the embodiment of the invention is applicable to various display screens with a Gate addressing circuit.
  • embodiments of the present invention can be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or a combination of software and hardware. Moreover, the invention may be packaged in one or more of them Computers containing computer usable program code may be in the form of a computer program product embodied on a storage medium, including but not limited to disk storage and optical storage.
  • the computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising the instruction device.
  • the apparatus implements the functions specified in one or more blocks of a flow or a flow and/or block diagram of the flowchart.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示面板栅极驱动电路及显示屏，用以更加便捷地对Gate信号进行寻址，避免采用译码电路的繁琐，占用电路面积更小，节省成本，提供寻址速度。该显示面板栅极驱动电路，用于驱动显示面板的栅极线。所述显示面板栅极驱动电路包括移位寄存器和多个栅极使能单元，所述移位寄存器包括至少两级移位寄存器单元，每一所述移位寄存器单元的栅极信号输出端与一栅极使能单元输入端相连，所述栅极使能单元的输出端与一栅极线相连，所述栅极使能单元还具有使能信号输入端，所述栅极使能单元通过所述使能信号输入端接收到的使能信号，控制所述移位寄存器单元的栅极信号输出端输出的栅极信号是否传送给所述栅极线。

Description

一种显示面板栅驱动电路及显示屏 本申请要求 2011年 11月 22日提交中国专利局、申请号为 201110373342.4、 发明名称为"一种显示面板栅驱动电路及显示屏"的中国专利申请的优先权，其 全部内容通过引用结合在本申请中。
技术领域
本发明涉及液晶显示器（Liquid Crystal Display, LCD )技术领域， 尤其 涉及一种显示面板栅驱动电路及显示屏。
背景技术
随着 LCD显示的日益发展， 传统栅极（Gate )布线方式已经满足不了日 益增高的屏幕分辨率的要求。 面板栅驱动集成（Gate In Panel, GIP )技术成为 业界热点。
图 1所示为现有技术中 GIP 电路的 Gate布线方案， GIP利用可重复单元 (即图中所示的 Unit, 例如 Un、 Un+1、 Un+2、 Un+3等等）和较少的外围布 线， 可在外围节省大量空间， 适应了屏幕的轻、 薄化发展。
但是，正由于 GIP电路结构省去了大量的外围布线，所以对它进行寻址驱 动变得很难。 尤其在非晶硅栅驱动集成（Amorphous Silicon Gate, ASG )电路 中， 难以制作性能良好的寻址电路。
普通的 LCD显示， 由于其缺乏很好的保持特性， 整个屏幕都需要不断刷 新， 才能维持显示， 因此并无针对特定区域寻址进行刷新的需求。 但随着双稳 态技术的发展， 电纸书 （Ebook )、 记忆液晶 （ Memory In Pixel )等， 对寻址驱 动的需求日益强烈。 针对性的对屏幕动态区域进行刷新， 不仅能节省功耗， 而 且能提高刷新速度。
现有技术中，如图 2所示， 大部分寻址方案都是通过对地址线译码实现信 号选择性输出的，寻址电路实际上是一种译码器， 即针对不同的地址线的不同 的 0、 1取值， 输出的 Gate信号有且仅有一路为真。
因此， 现有技术为了对 Gate线路寻址， 需要增加地址线的布线空间和随 之带来的庞大的译码电路。 以普通的 WVGA为例， 800行 Gate线路需要多增 加 10根地址线来进行寻址，而且对于每行 Gate线至少需要相应的 10个 PMOS 或 NMOS管进行选通。 并且， 现有技术中的非晶硅材料无合适的实现方案来 实现这样的译码电路。 ASG 电路， 即普通非晶硅电路也不适合做 PMOS, 而 且电路性能不高， 因此实现译码非常困难。
发明内容
本发明实施例提供了一种显示面板栅驱动电路， 用以更加便捷地对 Gate 信号进行寻址， 避免采用译码电路的繁瑣， 占用电路面积更小， 节省成本， 提 高寻址速度。
本发明实施例提供的一种显示面板栅驱动电路及显示屏，用于驱动配置于 显示面板的栅极线，所述显示面板栅驱动电路包括移位寄存器和多个栅极使能 单元， 所述移位寄存器包括至少两级移位寄存器单元，每一所述移位寄存器单 元的栅极信号输出端与一栅极使能单元输入端相连， 所述栅极使能单元的输 出端与一栅极线相连， 所述栅极使能单元还具有使能信号输入端， 所述栅极 使能单元通过所述使能信号输入端接收到的使能信号， 控制所述移位寄存器 单元的栅极信号输出端输出的栅极信号是否传送给所述栅极线。
本发明实施例提供的一种显示屏， 包括所述的显示面板栅驱动电路。
通过本发明实施例提供的上述显示面板栅驱动电路，实现了能够更加便捷 地对 Gate信号进行寻址的 GIP电路， 从而避免了采用译码电路的繁瑣， 占用 电路面积更小， 节省成本， 并且可以提高寻址速度， 适合非晶硅材料。
附图说明
图 1为现有技术中的 GIP电路结构示意图；
图 2为现有技术中的寻址电路结构示意图；
图 3为本发明实施例提供的 GIP电路的结构示意图；
图 4为本发明实施例提供的 GIP电路的结构示意图；
图 5为本发明实施例提供的集成电路结构示意图；
图 6为本发明实施例提供的 GIP电路中的移位寄存器单元的示意图； 图 7为本发明实施例提供的与 GIP电路配合输送的时序波形示意图； 图 8 为本发明实施例中实施例一提供的移位寄存器单元与栅极使能单元 的结构示意图；
图 9为本发明实施例提供的确定非扫描区域的示意图； 图 10为本发明实施例提供的 GIP电路进行栅极信号寻址时的不同频率的 时钟信号及使能信号的示意图；
图 11为本发明实施例中实施例二提供的移位寄存器单元与栅极使能单元 的结构示意图；
图 12为本发明实施例提供的比较电路的结构示意图；
图 13为本发明实施例提供的选通电路的结构示意图。
具体实施方式
本发明实施例提供了一种显示面板栅驱动电路及显示屏，用以更加便捷地 对 Gate信号进行寻址， 避免采用译码电路的繁瑣， 占用电路面积更小， 节省 成本， 提高寻址速度。
本发明实施例主要是通过增加 GIP外围电路， 实现 Gate寻址， 因此本发 明实施例并不针对于特定的 GIP电路和具体的 GIP电路形态。
下面结合附图对本发明实施例提供的技术方案进行说明。
参见图 3, 本发明实施例提供的一种显示面板栅驱动电路， 用于驱动配置 于显示面板的栅极线， 所述显示面板栅驱动电路包括：
移位寄存器和栅极使能单元， 其中， 所述的移位寄存器包括级连的移位寄 存器单元， 即图 3中所示的 Unit, 例如 Un、 Un+1、 Un+2、 Un+3等等， 每一 移位寄存器单元连接有一根对应的栅极使能单元， 各栅极使能单元构成图 3 中所示的 Gate EN CIRDUIT (栅极使能电路）。
所述移位寄存器单元包括至少两级移位寄存器单元， 参见图 4, 每一所述 移位寄存器单元的栅极信号输出端与一栅极使能单元输入端相连，所述栅极使 能单元的输出端与一栅极线相连， 所述栅极使能单元还具有使能信号输入端， 所述栅极使能单元通过所述使能信号输入端接收到的使能信号， 控制所述移 位寄存器单元的栅极信号输出端输出的栅极信号是否传送给所述栅极线。
参见图 4, 较佳地， 所述显示面板栅驱动电路还包括：
向所述栅极使能单元提供使能信号的集成电路 IC。
参见图 5, 较佳地， 所述集成电路 IC包括一比较电路， 所述比较电路将 需要通过显示面板进行显示的相邻帧图像的相同行中的所有像素点的图像信 息进行比较，并将所述比较结果作为使能信号输出给所述栅极使能单元的使能 信号输入端。
较佳地， 若相邻帧图像的相同行中的所有像素点的图像信息相同， 所述使 能信号使所述移位寄存器单元的栅极信号输出端输出的栅极信号不传送给所 述栅极线， 即该行的图像数据不被刷新； 若相邻帧图像的相同行中有一个像素 点的图像信息不相同，所述使能信号使所述移位寄存器单元的栅极信号输出端 输出的栅极信号传送给所述栅极线， 即该行的图像数据被刷新。
参见图 5, 较佳地， 所述集成电路 IC还包括：
用于为每一级移位寄存器单元提供时钟信号的选通电路；
用于为每一级移位寄存器单元提供复位信号 （RESET ) 的复位电路； 用于为第一级移位寄存器单元提供第一触发信号 （STV1 ) 的第一触发电 路， 其中所述第一触发信号为用于触发第一级移位寄存器单元工作的信号 较佳地， 所述选通电路根据所述比较电路的比较结果， 向所述各级移位寄 存器单元提供不同的时钟信号。
另外， 图 5中每一级移位寄存器单元都具有复位信号（RESET )仅为一个 优选实施方式， 并不构成对本发明的限定， 例如可以通过下一级的输出给上一 级做复位。 图 5中 CK, CKB成对出现， 但这也仅为一个优选实施方式， 并不 构成对本发明的限定， 也可以不成对出现。
以第 n+1级移位寄存器单元为例，其信号的输入输出如图 6所示，来自第 n级的移位寄存器单元的信号 Gn触发第 n+1级移位寄存器单元工作， CK和 CKB分别是其时钟信号， RESET是其复位信号， CK、 CKB和 RESET均由集 成电路 IC提供。 第 n+1级移位寄存器单元输出的信号为 Gn+1 , 用于触发第 n+2级移位寄存器单元工作， 同时也根据需要传输给相应的扫描线。
对于第 1 级移位寄存器单元， 是通过集成电路 IC提供的第一触发信号 STV1触发工作的。
较佳地， 若相邻帧图像的相同行中的所有像素点的图像信息相同， 所述选 通电路向所述各级移位寄存器单元提供第一时钟信号（CK1、 CKB1 ); 若相邻 帧图像的相同行中有一个像素点的图像信息不相同，所述选通电路向所述各级 寄存器单元提供第二时钟信号（CK2、 CKB2 ), 所述第一时钟信号的频率高于 所述第二时钟信号的频率， 即 CK1的频率大于 CK2的频率； CKB1的频率大 于 CKB2的频率。
GIP电路的原理是利用逻辑信号线传递由集成电路（IC )产生的特定的波 形信号， 然后在移位寄存器单元（也称为可重复单元） 内产生 Gate信号输出， 进而进行逐级触发， 如图 7所示， 第 n级移位寄存器单元产生的 Gate信号 Gn 触发第 n+1级移位寄存器单元，第 n+1级移位寄存器单元产生 Gate信号 Gn+1。 一般来说， 对 Gate的扫描速度起决定因素的有两个： 器件的速度， 以及控制 信号的频率。
所以， 本发明实施例在器件容许范围内， 通过改变时钟信号的频率， 就可 以改变 Gate的扫描速度， 其中， 所述的时钟信号泛指带有各种波形的输入信 号， 例如， 图 7中所示的时钟信号 CK和 CKB等等， 而并非狭义上的单一的 时钟信号。
较佳地， 参见图 8, 与每一移位寄存器单元相连的栅极使能单元， 包括两 个 N型薄膜场效应晶体管 TFT, 其中：
移位寄存器单元的栅极信号输出端， 与第一薄膜场效应晶体管 TFT的源 极相连， 第一 TFT的漏极与第二 TFT的源极相连， 并且作为栅极使能单元的 输出端， 第一 TFT的栅极由集成电路 IC提供使能信号 EN、 第二 TFT的栅极 由集成电路 IC提供反向使能信号 ENB, 第二 TFT的漏极由集成电路 IC提供 栅极低电平电压信号 VGL。
较佳地， 当集成电路 IC输出给第一 TFT的栅极的使能信号 EN为高电平 信号， 集成电路 IC输出给第二 TFT的栅极的反向使能信号 ENB为低电平信 号时， 第一 TFT导通， 第二 TFT断开， 第一 TFT的漏极输出栅极信号， 该栅 极信号通过栅极使能单元的输出端输出；
当集成电路 IC输出给第一 TFT的栅极的使能信号 EN为低电平信号， 集 成电路 IC输出给第二 TFT的栅极的反向使能信号 ENB为高电平信号时， 第 一 TFT断开，第二 TFT导通，集成电路 IC输出 VGL信号给第二 TFT的漏极， 该 VGL信号通过栅极使能单元的输出端输出。
EN和 ENB的控制机理：
EN和 ENB由 IC提供， 为普通数字信号。 当 EN为高电平， ENB为低电 平时， EN控制的 TFT管导通， ENB控制的 TFT管关闭， 此时 Gate线将有输 出； 当 EN为低电平， ENB为高电平时， EN控制 TFT管关闭， ENB控制的 TFT打开， 使 Gate锁定在 VGL ( Gate低电平电压）， 即无输出。
本发明实施例可以通过提高时钟信号的频率，并且配合输入给栅极使能单 元的使能信号， 可以以较快速度跳过不想扫描的图像区域， 然后， 降低时钟信 号的频率， 同时配合输入给栅极使能单元的使能信号，从而进行图像的指定区 域的扫描， 达到一种寻址扫描的目的。
如图 9所示， 在显示刷新过程前， 可以将两幅画面（即当前显示画面和刷 新画面）进行比较， 从而得出需要跳过扫描的图像区域的行数， 即 G3至 Gn-1 行为图像的非扫描区域。
参见图 10, 在扫描 G1和 G2行时， 将时钟信号 CK和 CKB的频率较低， G2行之后，在未到达所需扫描显示的图像区域前，将 CK和 CKB的频率加快， 将使能信号 EN置为低电平， 使能信号 ENB置为高电平， 使得 Gate进行快速 扫描（图中的 SKIP过程 ), 在此过程中 Gate由于受制于 EN和 ENB信号， 因 此并无输出， 当到达图像的指定扫描的位置， 如第 n行 Gate时， 恢复 CK和 CKB的信号频率， 将 EN使能信号置为高电平， 使能信号 ENB置为低电平， 进行图像指定区域的刷新。
以上栅极使能单元结构是针对非晶硅薄膜场效应晶体管（a-si TFT ), 但对 于低温多晶硅薄膜场效应管（LTPS-TFT )工艺， 仍可以提供一种结构来实现。 如图 11所示， 由于 LTPS可以提供良好的 P型薄膜场效应晶体管 TFT, 因此， 可以将 EN和 ENB信号合二为一， 成为一个统一的使能信号 EN。 P型薄膜场 效应晶体管 TFT (即图 11中所示的 T1 )和 N型薄膜场效应晶体管 TFT (即 图 11中所示的 T2 )组成了一个常见的 CMOS结构。 其工作原理是： 当 EN为 高电平时， T1导通， T2截止， 移位寄存器单元 Un输出的栅极信号 Gn, 通过 T1能对 Gate线有输出。 反之， 若 EN为低电平， T1截止， T2导通， Gate线 将通过 T2锁定在 VGL信号， 即无输出。 从图 11可以看出， 在 Gate线锁定在 VGL电平时， 并不会影响 Gn对下一级移位寄存器单元的信号传递。
因此， 较佳地， 与每一移位寄存器单元相连的栅极使能单元， 包括一个 P 型薄膜场效应晶体管 TFT和一个 N型薄膜场效应晶体管 TFT, 其中：
P型薄膜场效应晶体管 TFT的源极与移位寄存器单元的栅极信号输出端 相连； P型薄膜场效应晶体管 TFT的漏极与 N型薄膜场效应晶体管 TFT的漏 极相连， 并作为栅极使能单元的输出端； P型薄膜场效应晶体管 TFT的栅极和 N型薄膜场效应晶体管 TFT 的栅极均由集成电路 IC提供使能信号 EN; N型 薄膜场效应晶体管 TFT的源极由集成电路 IC提供栅极低电平电压信号 VGL。
当集成电路 IC输出给 P型薄膜场效应晶体管 TFT的栅极和 N型薄膜场效 应晶体管 TFT 的栅极的使能信号 EN为高电平信号时， P型薄膜场效应晶体 管 TFT导通， N型薄膜场效应晶体管 TFT断开， P型薄膜场效应晶体管 TFT 的漏极输出栅极信号， 该栅极信号通过栅极使能单元的输出端输出；
当集成电路 IC输出给 P型薄膜场效应晶体管 TFT的栅极和 N型薄膜场效 应晶体管 TFT 的栅极的使能信号 EN为低电平信号时， N型薄膜场效应晶体 管 TFT导通， P型薄膜场效应晶体管 TFT断开， 集成电路 IC将 VGL信号输 出给 N型薄膜场效应晶体管 TFT的源极，该 VGL信号通过栅极使能单元的输 出端输出。
此外， 由于非晶硅 TFT的速度限制， 为了达到更快的寻址效果， 可以在 某些移位寄存器单元引出初始触发信号， 如图 3所示， 在 Un+1和 Un+2之间 引出了初始信号 STV2。 如果指定需要初始化区域的起始地址线大于 N+1 , 便 可以直接输入 STV2 信号代替上一级移位寄存器单元输出的栅极信号触发 GIP, 这样需要扫描的时间会大大减少。 一般意义上来说， 额外增加 N根触发 信号 STV2线， 可使平均的寻址时间减小为 1/N, 但同时也会带来占用面积增 加的后果， 因此在具体的设计方案中需对速度和面积进行平衡。
例如， 显示器分辨率为 800 ( Gate ) *480, 如果将第 401级的移位寄存器 单元的触发信号 STV2引出， 需要快速扫描的最长时间为 400T, 其中 T为快 速扫描时， 平均每根 Gate占用的扫描时间。
因此， 较佳地， 如图 5所示， 所述集成电路 IC还包括：
用于向选定的移位寄存器单元提供第二触发信号 （STV2 ) 的第二触发电 路， 其中所述第二触发信号， 为用于触发选定的移位寄存器单元工作的信号。
下面分别给出本发明实施例提供的集成电路中的比较电路和选通电路的 原理介绍。
参见图 12, 本发明实施例提供的集成电路中的比较电路， 包括将来帧单 元、 当前帧单元和需扫描区域真值表单元。
在显示画面的同时，比较电路将正在显示的图片和即将显示的图片分别存 入如图 12所示的当前帧单元和将来帧单元中。 然后， 在前后行的显示间隔时 间内，对这两个图片进行比较，并将需扫描的区域以二进制形式存入存储器（一 般为寄存器）， 即图 12中所示的序扫描区域真值表单元中。
将来帧单元、 当前帧单元和需扫描区域真值表单元均为存储器， 当前帧单 元和将来帧单元的容量和图片大小相同，需扫描区域真值表单元的大小和栅极 数目有关，如果栅极数目为 800,则可以把需扫描区域真值表单元设置成 800*1 寄存器， 即 800个 1位的寄存器。
比较电路可以用 verilog语言表述， 将当前帧和将来帧的每一行需要扫描 的数据引到这个比较电路， 就会输出 0和 1的数据流， 然后将 0、 1移位存入 需扫描区域真值表单元中。
本发明实施例提供的集成电路中的选通电路如图 13所示， 例如可以是常 见的 2选 1多路复用器， 其电路特性也可以用 verilog语言描述， 可以在每个 需要输出的时钟信号的上升沿到来后，将比较电路中需扫描区域真值表单元的 值（即比较电路的比较结果）输入到选通电路， 于是选通电路输出端输出的时 钟信号便可以在 CK1、 CKB1 , 和 CK2、 CKB2之间切换， 从而调整输出的时 钟信号的频率， 将此时钟信号引入到 GIP电路中， 就可以实现变频驱动了。
最后，本发明实施例提供的一种显示屏， 可以包括上述各种显示面板栅驱 动电路。
综上所述， 本发明实施例提供的显示面板栅驱动电路， 只需增加少量的地 址线和控制线， 就可以实现变频驱动 GIP寻址， 在 GIP结构中增加了初始触 发信号线， 从而进一步提高了寻址速度。 并且， 寻址的实现方式无需在面板 ( panel )上实现译码， 即无需增加译码电路， 省去了译码电路， 占用更小的 面积， 适合非晶硅材料。 本发明实施例提供的技术方案， 适用于带有 Gate寻 址电路的各类显示屏。
本领域内的技术人员应明白， 本发明的实施例可提供为方法、 系统、 或计 算机程序产品。 因此， 本发明可采用完全硬件实施例、 完全软件实施例、 或结 合软件和硬件方面的实施例的形式。 而且， 本发明可采用在一个或多个其中包 含有计算机可用程序代码的计算机可用存储介质 (包括但不限于磁盘存储器和 光学存储器等）上实施的计算机程序产品的形式。
本发明是参照根据本发明实施例的方法、 设备（系统）、 和计算机程序产 品的流程图和 /或方框图来描述的。应理解可由计算机程序指令实现流程图和 /或方框图中的每一流程和 /或方框、以及流程图和 /或方框图中的流程和 / 或方框的结合。 可提供这些计算机程序指令到通用计算机、 专用计算机、 嵌入 式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算 个流程或多个流程和 /或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设 备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中 的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个 流程和 /或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使 得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处 理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个 流程或多个流程和 /或方框图一个方框或多个方框中指定的功能的步骤。 明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及 其等同技术的范围之内， 则本发明也意图包含这些改动和变型在内。

Claims

权 利 要 求
1、 一种显示面板栅驱动电路， 用于驱动配置于显示面板的栅极线， 其特 征在于： 所述显示面板栅驱动电路包括移位寄存器和多个栅极使能单元，所述 移位寄存器包括至少两级移位寄存器单元，每一所述移位寄存器单元的栅极信 号输出端与一栅极使能单元输入端相连， 所述栅极使能单元的输出端与一栅 极线相连， 所述栅极使能单元还具有使能信号输入端， 所述栅极使能单元通 过所述使能信号输入端接收到的使能信号， 控制所述移位寄存器单元的栅极 信号输出端输出的栅极信号是否传送给所述栅极线。
2、 根据权利要求 1所述的显示面板栅驱动电路， 其特征在于， 所述显示 面板栅驱动电路还包括：
向所述栅极使能单元提供使能信号的集成电路 IC。
3、 根据权利要求 2所述的显示面板栅驱动电路， 其特征在于， 所述集成 电路 IC包括一比较电路， 所述比较电路将需要通过显示面板进行显示的相邻 帧图像的相同行中的所有像素点的图像信息进行比较，并将所述比较结果作为 使能信号输出给所述栅极使能单元的使能信号输入端。
4、 根据权利要求 3所述的显示面板栅驱动电路， 其特征在于， 若相邻帧 图像的相同行中的所有像素点的图像信息相同，所述使能信号使所述移位寄存 器单元的栅极信号输出端输出的栅极信号不传送给所述栅极线；若相邻帧图像 的相同行中有一个像素点的图像信息不相同，所述使能信号使所述移位寄存器 单元的栅极信号输出端输出的栅极信号传送给所述栅极线。
5、 根据权利要求 4所述的显示面板栅驱动电路， 其特征在于， 所述集成 电路 IC还包括：
用于为每一级移位寄存器单元提供时钟信号的选通电路；
用于为每一级移位寄存器单元提供复位信号的复位电路；
用于为第一级移位寄存器单元提供第一触发信号的第一触发电路，其中所 述第一触发信号为用于触发第一级移位寄存器单元工作的信号。
6、 根据权利要求 5所述的显示面板栅驱动电路， 其特征在于， 所述选通 电路根据所述比较电路的比较结果，向所述各级移位寄存器单元提供不同的时 钟信号。
7、 根据权利要求 6所述的显示面板栅驱动电路， 其特征在于， 若相邻帧 图像的相同行中的所有像素点的图像信息相同，所述选通电路向所述各级移位 寄存器单元提供第一时钟信号（CK1、 CKB1 ); 若相邻帧图像的相同行中有一 个像素点的图像信息不相同，所述选通电路向所述各级寄存器单元提供第二时 钟信号（CK2、 CKB2 ), 所述第一时钟信号的频率高于所述第二时钟信号的频 率。
8、 根据权利要求 5所述的显示面板栅驱动电路， 其特征在于， 所述集成 电路 IC还包括：
用于向选定的移位寄存器单元提供第二触发信号的第二触发电路，其中所 述第二触发信号， 为用于触发选定的移位寄存器单元工作的信号。
9、 根据权利要求 1所述的显示面板栅驱动电路， 其特征在于， 与每一移 位寄存器单元相连的栅极使能单元， 包括两个 N型薄膜场效应晶体管 TFT, 其中：
移位寄存器单元的栅极信号输出端， 与第一薄膜场效应晶体管 TFT的源 极相连， 第一 TFT的漏极与第二 TFT的源极相连， 并且作为栅极使能单元的 输出端， 第一 TFT的栅极由集成电路 IC提供使能信号 EN、 第二 TFT的栅极 由集成电路 IC提供反向使能信号 ENB, 第二 TFT的漏极由集成电路 IC提供 栅极低电平电压信号 VGL。
10、 根据权利要求 1 所述的电路， 其特征在于， 与每一移位寄存器单元 相连的栅极使能单元， 包括一个 P型薄膜场效应晶体管 TFT和一个 N型薄膜 场效应晶体管 TFT, 其中：
P型薄膜场效应晶体管 TFT的源极与移位寄存器单元的栅极信号输出端 相连； P型薄膜场效应晶体管 TFT的漏极与 N型薄膜场效应晶体管 TFT的源 极相连， 并作为栅极使能单元的输出端； P型薄膜场效应晶体管 TFT的栅极和 N型薄膜场效应晶体管 TFT 的栅极均由集成电路 IC提供使能信号 EN; N型 薄膜场效应晶体管 TFT的漏极由集成电路 IC提供栅极低电平电压信号 VGL。
11、 一种显示屏， 其特征在于， 该显示屏包括权利要求 1 所述的显示面 板栅驱动电路。
PCT/CN2012/078236 2011-11-22 2012-07-05 一种显示面板栅驱动电路及显示屏 WO2013075506A1 (zh)

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