WO2013071632A1 - 液晶显示器 - Google Patents

液晶显示器 Download PDF

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Publication number
WO2013071632A1
WO2013071632A1 PCT/CN2011/082828 CN2011082828W WO2013071632A1 WO 2013071632 A1 WO2013071632 A1 WO 2013071632A1 CN 2011082828 W CN2011082828 W CN 2011082828W WO 2013071632 A1 WO2013071632 A1 WO 2013071632A1
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pixel
common electrode
liquid crystal
crystal display
electrode
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PCT/CN2011/082828
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English (en)
French (fr)
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施明宏
廖作敏
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深圳市华星光电技术有限公司
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Priority to US13/379,873 priority Critical patent/US20130128167A1/en
Publication of WO2013071632A1 publication Critical patent/WO2013071632A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned

Definitions

  • This invention relates to a liquid crystal display, and more particularly to a liquid crystal display that provides better aperture ratio and transmittance.
  • FIG. 1 is a schematic plan view of a pixel unit of a conventional liquid crystal display.
  • the pixel unit is disposed in a pixel region defined by the gate line 90 and the data line 92, and includes a common line 91, a transistor, a pixel electrode 94, and a common electrode 95.
  • the common line 91 is parallel to the gate line 90.
  • the transistor includes a gate, a semiconductor layer 93, a source 921 and a drain 922, wherein the gate is the gate line 90, and the semiconductor layer 93 is disposed on the gate line 90, A source electrode 921 extends from the data line 92 and is provided on the semiconductor layer 93.
  • the drain electrode 922 is disposed on the semiconductor layer 93 and has a side parallel to the source electrode 921.
  • the pixel electrode 94 is disposed in the pixel region and connected to the drain 922 through a through hole 920, and has a plurality of slits 940.
  • the common electrode 95 overlaps the pixel electrode 94 and is connected to the common line 91. Furthermore, the common electrode 95 correspondingly connects the common electrode of the adjacent pixel region across the gate line 90 in a corner of the pixel region through a bridge unit 96, wherein the common line 91 and the common line An insulating layer is disposed on the gate line 90, and a via 960 is formed on the insulating layer corresponding to the corner of the pixel region.
  • the cross-bridge unit 96 is further connected to the common line 91 through the via 960.
  • the above-mentioned common line 91 is connected in series by the cross-bridge unit 96 to form a common mesh line of the entire pixel array.
  • This mesh configuration can reduce the floating of the potential of the common line and help reduce the crosstalk effect (Crosstalk). ).
  • the main object of the present invention is to provide a liquid crystal display to solve the problem of poor aperture ratio of a liquid crystal display having a pixel structure with a mesh design.
  • the invention provides a liquid crystal display comprising:
  • each of the pixel units including a transistor, a pixel electrode, a common electrode, and at least one interface portion, wherein the pixel electrode is located in the pixel region and connected to the transistor a drain electrode having a plurality of slits; the common electrode is connected to a corresponding common line and overlapping the pixel electrode; the connecting portion is located on the same plane as the common electrode and is connected to the common electrode, and is insulated
  • the common electrode of the pixel unit of the adjacent pixel region is connected by the gate line.
  • the transistor includes a gate, a semiconductor layer, a source and a drain
  • the gate is one of the gate lines
  • the semiconductor layer is disposed on the gate
  • the source A pole extends from one of the data lines and is located on the semiconductor layer
  • the drain is disposed on the semiconductor layer.
  • the gate line corresponds to a pixel region and has two first conductor layers and a second conductor layer, the two first conductor layers are separated by a pitch, and the second conductor layer The two ends are respectively connected to the first conductor layer, and the connecting portion extends insulatively between the opposite ends of the two first conductor layers and below the second conductor layer.
  • the two first conductor layers and the surface of the connecting portion are provided with an insulating layer, and the insulating layer forms a perforation corresponding to the opposite ends of the two first conductor layers. Both ends of the two conductor layers are respectively connected to opposite ends of the two first conductor layers through the through holes.
  • the slits of the pixel electrodes are arranged in parallel.
  • the material of the connecting portion and the common electrode is a transparent conductive material
  • the connecting portion is an extended portion of the common electrode
  • the material of the connecting portion and the common electrode is indium tin oxide.
  • the invention further provides a liquid crystal display, the liquid crystal display comprising:
  • each of the pixel units including a transistor, a pixel electrode, a common electrode, and at least one interface portion, wherein the pixel electrode is located in the pixel region and connected to the transistor a drain having a plurality of slits, the slits being arranged in parallel; the common electrode being connected to a corresponding common line and overlapping the pixel electrode; the connecting portion being located on the same plane as the common electrode and connected
  • the common electrode is electrically connected to the common electrode of the pixel unit of the adjacent pixel region through the gate line, wherein the gate line corresponds to a pixel region and has two first conductor layers and a second conductor layer. The two first conductor layers are separated by a spacing, the two ends of the second conductor layer are respectively connected to the first conductor layer, and the connecting portion is insulatedly extended between the opposite ends of the two first conductor layers and Below the second conductor layer.
  • the present invention mainly forms an interface portion that connects adjacent common electrodes on a plane on which the common electrode is formed, which can solve the disadvantage that the aperture ratio is poor in the pixel region as in the prior art.
  • FIG. 1 is a schematic plan view of a pixel unit of a conventional liquid crystal display.
  • FIG. 2 is a schematic plan view showing a pixel unit of a preferred embodiment of the liquid crystal display of the present invention.
  • Figure 3 is a cross-sectional view taken along line A-A of Figure 2;
  • FIG. 2 is a schematic plan view of a pixel unit according to a preferred embodiment of the liquid crystal display of the present invention.
  • the liquid crystal display includes a plurality of gate lines 20, a plurality of data lines 50, a plurality of common lines 22, and a plurality of pixel units.
  • the gate lines 20 are interleaved with the data lines 50 to define a plurality of pixel regions.
  • the common line 22 is interleaved with the data line 50 and parallel to the gate line 20.
  • the pixel units are respectively located in the plurality of pixel regions, and each of the pixel units includes a transistor, a pixel electrode 40, a common electrode 30, and at least one connecting portion 31.
  • the pixel electrode 40 is located in the pixel region and is connected to the drain 52 of the transistor and has a plurality of slits 41.
  • the pixel electrode 40 is connected to the drain through a through hole 500 of an insulating layer. An extension of 52.
  • the slits 41 of the pixel electrode 40 are preferably arranged in parallel.
  • the common electrode 30 is connected to a corresponding common line 22 and overlaps the pixel electrode 40.
  • the connecting portion 31 is located on the same plane as the common electrode 30 and is connected to the common electrode 30, and is electrically connected to the common electrode 30 of the pixel unit of the adjacent pixel region through the gate line 20.
  • the material of the engaging portion 31 and the common electrode 30 is a transparent conductive material, and is preferably indium tin oxide.
  • the engaging portion 31 is preferably an extended portion of the common electrode 30.
  • the transistor includes a gate, a semiconductor layer 60, a source 52, and a drain 51.
  • the gate is a gate line 20
  • the semiconductor layer 60 is disposed on the gate
  • the source 52 extends from one of the data lines 50 to be located on the semiconductor layer 60.
  • a drain electrode 52 is provided on the semiconductor layer 60.
  • FIG. 3 is a cross-sectional view taken along line A-A of FIG.
  • the gate line 20 corresponds to a pixel region and has two first conductor layers 20a and a second conductor layer 20b.
  • the two first conductor layers 20a are separated by a spacing, and the two ends of the second conductor layer 20b are respectively
  • the first conductor layer 20a is connected, and the connecting portion 31 extends insulatively between the opposite ends of the two first conductor layers 20a and below the second conductor layer 20b.
  • the two first conductor layers 20a and the surface of the connecting portion 31 are provided with an insulating layer 100, and the insulating layer 100 forms a through hole 210 corresponding to opposite ends of the two first conductor layers 20a.
  • Both ends of the second conductor layer 20b are respectively connected to opposite ends of the two first conductor layers 20a through the through holes 210.
  • the present invention can connect the adjacent common electrodes 30 through the connecting portion 31, and the common line 22 connecting the common electrodes 30 can thus form a mesh configuration, which can also reduce the floating of the potential of the common line 22, thereby contributing to Reduce crosstalk effects (Crosstalk).
  • the liquid crystal configuration of the common line of the conventional liquid crystal display must form a via hole in the pixel region to connect the common line across the top of the gate line by the bridge unit, thereby causing a problem that the aperture ratio is lowered, and the liquid crystal of the present invention
  • the display causes one side of the common electrode at the bottom of the pixel electrode to extend out of the connecting portion to insulately pass under the gate line, so that it is not necessary to form a via hole in the pixel region, thereby contributing to increasing the aperture ratio of the pixel region and the transmittance of the liquid crystal panel. , further reducing the energy consumption of the liquid crystal display.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种液晶显示器，包含多个由栅极线（20）与资料线（50）定义的像素区及多个像素单元。每一像素单元包含晶体管、像素电极（40）、公共电极（30）及至少一衔接部（31），所述像素电极（40）连接晶体管的漏极（51）；所述公共电极（30）连接一对应的公共线（22）且与所述像素电极（40）重叠，所述衔接部（31）与所述公共电极（30）位于同一平面上并连接所述公共电极（30），且绝缘地通过栅极线（20）并连接相邻像素区的像素单元的公共电极（30）。通过上述结构配置，所述液晶显示器能提供较佳的开口率和穿透率。

Description

液晶显示器 技术领域
本发明是有关于一种液晶显示器，特别是有关于一种提供较佳的开口率和穿透率的液晶显示器。
 背景技术
请参考图1所示，图1是现有液晶显示器的像素单元的平面示意图。所述像素单元是配置于栅极线90与资料线92所定义的像素区内，并包含公共线91、一晶体管、一像素电极94及一公共电极95。所述公共线91是平行所述栅极线90。所述晶体管包含栅极、半导体层93、源极921及漏极922，其中所述栅极即是所述栅极线90，所述半导体层93设置于所述栅极线90上，所述源极921从所述资料线92延伸出而设于所述半导体层93上。所述漏极922设于半导体层93且一侧边与所述源极921呈平行。所述像素电极94设于所述像素区内并通过一穿孔920连接所述漏极922，且具有多个狭缝940。所述公共电极95与所述像素电极94重叠，并连接所述公共线91。再者，所述公共电极95在所述像素区角落通过一跨桥单元96绝缘地跨过所述栅极线90而对应连接相邻像素区的公共电极，其中所述公共线91与所述栅极线90上会先设置一绝缘层，再于绝缘层上对应所述像素区的角落成形一过孔960，所述跨桥单元96再通过所述过孔960连接所述公共线91。
上述通过跨桥单元96串接公共线91可使整个像素阵列的公共线构成一网形(Mesh)配置，此网形配置可降低公共线的电位的浮动，而有助于减少串扰效应(Crosstalk)。
然而，由于上述网形配置是在所述像素区成形过孔960，再利用跨桥单元96连接公共线91，因此会导致像素区的开口率降低。
故，有必要提供一种液晶显示器，以解决现有技术所存在的问题。
 技术问题
本发明的主要目的在于提供一种液晶显示器，以解决现有具网孔设计的像素结构的液晶显示器的开口率不佳的问题。
 技术解决方案
本发明提供一种液晶显示器，其包含：
多条栅极线；
多条资料线，与所述栅极线交错而定义多个像素区；
多条公共线，与所述资料线交错，且与所述栅极线互相平行；
多个像素单元，分别位于所述多个像素区内，每一像素单元包含晶体管、像素电极、公共电极及至少一衔接部，所述像素电极位于所述像素区内，并连接所述晶体管的漏极且具有多个狭缝；所述公共电极连接一对应的公共线且与所述像素电极重叠；所述衔接部与所述公共电极位于同一平面上并连接所述公共电极，且绝缘地通过闸极线而连接相邻像素区的像素单元的公共电极。
在本发明的一实施例中，所述晶体管包含栅极、半导体层、源极及漏极，所述栅极为其中一栅极线，所述半导体层设置于所述栅极上，所述源极自其中一资料线延伸出而位于所述半导体层上，所述漏极设于所述半导体层上。
在本发明的一实施例中，所述栅极线对应一像素区而具有两个第一导体层及一第二导体层，所述两第一导体层相隔一间距，所述第二导体层的两端分别连接所述第一导体层，所述衔接部绝缘地延伸于所述两第一导体层的相对端之间及所述第二导体层的下方。
在本发明的一实施例中，所述两个第一导体层与所述衔接部的表面设有一绝缘层，所述绝缘层对应所述两第一导体层的相对端形成穿孔，所述第二导体层的两端通过所述穿孔分别连接所述两第一导体层的相对端。
在本发明的一实施例中，所述像素电极的狭缝呈平行排列。
在本发明的一实施例中，所述衔接部与所述公共电极的材料是透明导电材，所述衔接部是所述公共电极的延伸部份。
在本发明的一实施例中，所述衔接部与所述公共电极的材料是铟锡氧化物。
本发明另提供一种液晶显示器，所述液晶显示器包含：
多条栅极线；
多条资料线，与所述栅极线交错而定义多个像素区；
多条公共线，与所述资料线交错，且与所述栅极线互相平行；以及
多个像素单元，分别位于所述多个像素区内，每一像素单元包含晶体管、像素电极、公共电极及至少一衔接部，所述像素电极位于所述像素区内，并连接所述晶体管的漏极且具有多个狭缝，所述狭缝呈平行排列；所述公共电极连接一对应的公共线且与所述像素电极重叠；所述衔接部与所述公共电极位于同一平面上并连接所述公共电极，且绝缘地通过闸极线而连接相邻像素区的像素单元的公共电极，其中所述栅极线对应一像素区而具有两个第一导体层及一第二导体层，所述两第一导体层相隔一间距，所述第二导体层的两端分别连接所述第一导体层，所述衔接部绝缘地延伸于所述两第一导体层的相对端之间及所述第二导体层的下方。
 有益效果
本发明主要是在形成公共电极的平面上进一步也形成衔接相邻公共电极的衔接部，如此可解决像现有技术在像素区形成开孔而导致开口率不佳的缺点。
 附图说明
图1是现有液晶显示器的像素单元的平面示意图。
图2是本发明液晶显示器一较佳实施例的像素单元的平面示意图。
图3是图2沿A-A线的剖视图。
 本发明的最佳实施方式
为让本发明上述目的、特征及优点更明显易懂，下文特举本发明较佳实施例，并配合附图，作详细说明如下。再者，本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参考图2所示，图2为本发明液晶显示器一较佳实施例的像素单元的平面示意图。所述液晶显示器包含多个由多条栅极线20、多条资料线50、多条公共线22及多个像素单元。所述栅极线20与所述资料线50交错而定义多个像素区。所述公共线22与所述资料线50交错，且与所述栅极线20互相平行。所述像素单元分别位于所述多个像素区内，每一像素单元包含晶体管、像素电极40、公共电极30及至少一衔接部31。
所述像素电极40位于所述像素区内，并连接所述晶体管的漏极52且具有多个狭缝41，其中所述像素电极40是通过一绝缘层的通孔500而连接所述漏极52的一延伸部。本实施例中，所述像素电极40的狭缝41优选是呈平行排列。
所述公共电极30连接一对应的公共线22且与所述像素电极40重叠。
所述衔接部31与所述公共电极30位于同一平面上并连接所述公共电极30，且绝缘地通过闸极线20而连接相邻像素区的像素单元的公共电极30。在本实施例中，所述衔接部31与所述公共电极30的材料是透明导电材，且优选是铟锡氧化物。所述衔接部31优选是所述公共电极30的延伸部份。
所述晶体管包含栅极、半导体层60、源极52及漏极51。所述栅极即为其中一栅极线20，所述半导体层60设置于所述栅极上，所述源极52自其中一资料线50延伸出而位于所述半导体层60上，所述漏极52设于所述半导体层60上。
进一步参考图3所示，图3是图2沿A-A线的剖视图。所述栅极线20对应一像素区而具有两个第一导体层20a及一第二导体层20b，所述两第一导体层20a相隔一间距，所述第二导体层20b的两端分别连接所述第一导体层20a，所述衔接部31绝缘地延伸于所述两第一导体层20a的相对端之间及所述第二导体层20b的下方。更详细地，所述两个第一导体层20a与所述衔接部31的表面设有一绝缘层100，所述绝缘层100对应所述两第一导体层20a的相对端形成穿孔210，所述第二导体层20b的两端通过所述穿孔210分别连接所述两第一导体层20a的相对端。如此，本发明可通过所述衔接部31连接相邻的公共电极30，连接公共电极30的公共线22可因此构成网形配置，同样可达到降低公共线22的电位的浮动，而有助于减少串扰效应(Crosstalk)。
相较于现有液晶显示器的公共线的网形配置必须在像素区成形过孔，来利用跨桥单元跨过栅极线顶部来连接公共线，而造成开口率下降的问题，本发明的液晶显示器令像素电极底部的公共电极的一侧延伸出衔接部来绝缘地通过栅极线下方，可不必在像素区成形过孔，进而有助于提升像素区的开口率和液晶面板的穿透率，更进一步地降低了液晶显示器的能耗。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。
 本发明的实施方式
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Claims (8)

  1. 一种液晶显示器，其特征在于：所述液晶显示器包含：
    多条栅极线；
    多条资料线，与所述栅极线交错而定义多个像素区；
    多条公共线，与所述资料线交错，且与所述栅极线互相平行；
    多个像素单元，分别位于所述多个像素区内，每一像素单元包含晶体管、像素电极、公共电极及至少一衔接部，所述像素电极位于所述像素区内，并连接所述晶体管的漏极且具有多个狭缝，所述狭缝呈平行排列；所述公共电极连接一对应的公共线且与所述像素电极重叠；所述衔接部与所述公共电极位于同一平面上并连接所述公共电极，且绝缘地通过闸极线而连接相邻像素区的像素单元的公共电极，其中所述栅极线对应一像素区而具有两个第一导体层及一第二导体层，所述两第一导体层相隔一间距，所述第二导体层的两端分别连接所述第一导体层，所述衔接部绝缘地延伸于所述两第一导体层的相对端之间及所述第二导体层的下方。
  2. 一种液晶显示器，其特征在于：所述液晶显示器包含：
    多条栅极线；
    多条资料线，与所述栅极线交错而定义多个像素区；
    多条公共线，与所述资料线交错，且与所述栅极线互相平行；
    多个像素单元，分别位于所述多个像素区内，每一像素单元包含晶体管、像素电极、公共电极及至少一衔接部，所述像素电极位于所述像素区内，并连接所述晶体管的漏极且具有多个狭缝；所述公共电极连接一对应的公共线且与所述像素电极重叠；所述衔接部与所述公共电极位于同一平面上并连接所述公共电极，且绝缘地通过闸极线而连接相邻像素区的像素单元的公共电极。
  3. 如权利要求2所述的液晶显示器，其特征在于：所述晶体管包含栅极、半导体层、源极及漏极，所述栅极为其中一栅极线，所述半导体层设置于所述栅极上，所述源极自其中一资料线延伸出而位于所述半导体层上，所述漏极设于所述半导体层上。
  4. 如权利要求2所述的液晶显示器，其特征在于：所述栅极线对应一像素区而具有两个第一导体层及一第二导体层，所述两第一导体层相隔一间距，所述第二导体层的两端分别连接所述第一导体层，所述衔接部绝缘地延伸于所述两第一导体层的相对端之间及所述第二导体层的下方。
  5. 如权利要求4所述的液晶显示器，其特征在于：所述两个第一导体层与所述衔接部的表面设有一绝缘层，所述绝缘层对应所述两第一导体层的相对端形成穿孔，所述第二导体层的两端通过所述穿孔分别连接所述两第一导体层的相对端。
  6. 如权利要求2所述的液晶显示器，其特征在于：所述像素电极的狭缝呈平行排列。
  7. 如权利要求2所述的液晶显示器，其特征在于：所述衔接部与所述公共电极的材料是透明导电材，所述衔接部是所述公共电极的延伸部份。
  8. 如权利要求7所述的液晶显示器，其特征在于：所述衔接部与所述公共电极的材料是铟锡氧化物。
PCT/CN2011/082828 2011-11-18 2011-11-24 液晶显示器 WO2013071632A1 (zh)

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