WO2013069070A1 - Dispositif à semi-conducteurs, et circuit d'entraînement de matrice active mettant en œuvre celui-ci - Google Patents

Dispositif à semi-conducteurs, et circuit d'entraînement de matrice active mettant en œuvre celui-ci Download PDF

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WO2013069070A1
WO2013069070A1 PCT/JP2011/006324 JP2011006324W WO2013069070A1 WO 2013069070 A1 WO2013069070 A1 WO 2013069070A1 JP 2011006324 W JP2011006324 W JP 2011006324W WO 2013069070 A1 WO2013069070 A1 WO 2013069070A1
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layer
oxide film
source
semiconductor
drain
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PCT/JP2011/006324
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English (en)
Japanese (ja)
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周哲 秋山
大塚　正志
勝美 吉沢
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パイオニア株式会社
パイオニア・マイクロ・テクノロジー株式会社
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Publication of WO2013069070A1 publication Critical patent/WO2013069070A1/fr

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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Definitions

  • the present invention relates to a semiconductor device including a one-side LOCOS offset type MOS transistor and an active matrix driving circuit using the same.
  • a drain region composed of a P-type field relaxation layer and a P-type high-concentration drain layer formed in an N-type semiconductor layer a source region composed of a P-type high-concentration source layer, a drain region and a source region
  • a gate oxide film formed in the active region on the semiconductor layer surface a LOCOS oxide film formed on the semiconductor layer surface between the drain region and the gate oxide film, and formed on the gate oxide film across the LOCOS oxide film
  • a semiconductor device including a one-side LOCOS offset type (offset drain type) MOS transistor having a gate electrode formed and a P-type drift layer (offset layer) formed under a LOCOS oxide film (patent) Reference 1).
  • the electric field relaxation layer is adjacent to the drift layer, and the impurity concentration of the electric field relaxation layer is higher than that of the drift layer and thinner than that of the high concentration drain layer.
  • the high-concentration drain layer is included in the electric field relaxation layer and is separated from the end of the LOCOS oxide film. For this reason, the impurity concentration gradient near the bird's beak at the end of the LOCOS oxide film is gentle. Thereby, the breakdown voltage in the drain region is improved.
  • the conventional semiconductor device has a problem that a high voltage cannot be applied to the drain region because the breakdown voltage of the source region is low.
  • the breakdown voltage in the source region can be improved by adopting the double-sided LOCOS offset type in which the LOCOS oxide film and the drift layer are provided in the source region as well as the drift region.
  • the double-sided LOCOS offset type MOS transistor has a larger area than the one-sided LOCOS offset type, and thus it has been difficult to apply to an integrated circuit that requires miniaturization.
  • the semiconductor device of the present invention includes a first conductivity type semiconductor layer formed on a semiconductor substrate, a drain region having a second conductivity type drain electrode layer formed on the semiconductor layer, and a first region formed on the semiconductor layer.
  • a source region having a source offset layer and a source electrode layer of two conductivity types, a gate oxide film formed in an active region on the surface of the semiconductor layer between the drain region and the source region, and between the drain region and the gate oxide film A LOCOS oxide film formed on the surface of the semiconductor layer; and a gate electrode formed on the gate oxide film across the LOCOS oxide film.
  • the source offset layer is formed adjacent to the gate oxide film,
  • the impurity concentration of the offset layer is higher than the impurity concentration of the semiconductor layer and lower than the impurity concentration of the source electrode layer, and the source electrode layer is separated from the gate oxide film. Characterized in that it is formed over the scan offset layer.
  • the source electrode layer is formed in the source offset layer and at a position separated from the gate oxide film.
  • the impurity concentration of the source offset layer is higher than that of the semiconductor layer and lower than that of the source electrode layer.
  • the source electrode layer is preferably formed to be separated from the end of the gate oxide film by 0.4 ⁇ m or more and 0.7 ⁇ m or less.
  • the impurity concentration of the source offset layer is preferably 1.4E + 16 / cm 3 or more and 1.3E + 17 / cm 3 or less.
  • the junction depth of the source offset layer with respect to the semiconductor layer is preferably 0.3 ⁇ m or more and 1.0 ⁇ m or less.
  • the reduction of the transistor area and the improvement of the breakdown voltage of the source region can be achieved at a high level.
  • the drain electric field relaxation layer further includes a drain region having a second conductivity type drain electric field relaxation layer including the drain electrode layer, and a second conductivity type drift layer formed under the LOCOS oxide film. Is formed adjacent to the drift layer, the impurity concentration of the drain electric field relaxation layer is higher than the impurity concentration of the drift layer and lower than the impurity concentration of the drain electrode layer, and the drain electrode layer is formed of a LOCOS oxide film. It is preferably formed by self-alignment as a mask.
  • the drain electrode layer is formed in the drain electric field relaxation layer.
  • the impurity concentration of the drain electric field relaxation layer is higher than that of the drift layer and lower than that of the drain electrode layer. For this reason, since the concentration gradient of the impurity concentration from the drift layer to the drain electrode layer becomes gentle, the electric field concentration is alleviated and the breakdown voltage of the drain region is improved.
  • An active matrix driving circuit includes a semiconductor array in which a plurality of the above semiconductor devices are arranged in a matrix, a horizontal scanning circuit that scans and switches the semiconductor array in the horizontal direction, and the semiconductor array in the vertical direction. And a vertical scanning circuit that performs scanning and switching.
  • a high active matrix driving circuit can be configured. Thereby, for example, it can be used as a drive circuit for a high-resolution imaging device or the like.
  • This imaging apparatus includes an imaging device in which an electron-emitting device array in which a plurality of so-called surface conduction type electron-emitting devices are arranged in a matrix functions as one pixel.
  • FIG. 1 is a side sectional view schematically showing the configuration of the imaging apparatus 100.
  • FIG. 2 is a perspective view schematically showing the configuration of the electron emission substrate portion 110.
  • FIG. 3 is a side sectional view schematically showing the structure of the imaging element array 113 (electron emission element 210).
  • the imaging apparatus 100 includes an electron emission substrate unit 110 in which a plurality of electron emission elements 210 are formed, and the electron emission substrate unit 110 facing the electron emission substrate unit 110 with a vacuum space, and A light receiving substrate unit 120 serving as a target, and a mesh electrode 130 that is spaced between the electron emission substrate unit 110 and the light receiving substrate unit 120 and controls the trajectory of emitted electrons are provided.
  • the electron emission substrate section 110 includes a silicon substrate 111, a drive circuit layer 112 formed on the silicon substrate 111, and an image sensor array 113 formed on the drive circuit layer 112. ,have.
  • an active matrix drive circuit 114 (switch circuit) for driving a plurality of imaging element arrays 113 (electron emission elements 210) is formed on a silicon substrate 111.
  • a horizontal scanning circuit 115 and a vertical scanning circuit 116 for controlling the active matrix driving circuit 114 are disposed on the periphery of the silicon substrate 111.
  • the image sensor array 113 is stacked on the drive circuit layer 112 (active matrix drive circuit 114) via an insulating layer 117.
  • the imaging element array 113 is configured by a plurality of emission element arrays 118 functioning as one pixel arranged in a matrix.
  • the emitter array 118 includes a plurality of electron-emitting devices 210 that emit electrons (emit an electron beam) in a matrix.
  • Each electron-emitting device 210 is formed by laminating a lower metal electrode 220, a silicon layer 230, a silicon oxide layer 240, an upper metal electrode 250, and a carbon thin film 260 in this order.
  • a surface emission portion 270 (emission site) from which electrons are emitted is formed on the surface of each electron-emitting device 210 so as to be recessed to the surface of the silicon layer 230.
  • the silicon oxide layer 240, the upper metal electrode 250, and the carbon thin film 260 are common to all pixels. That is, it is configured integrally with all the emitting element arrays 118.
  • the lower metal electrode 220 and the silicon layer 230 are divided for each emitting element array 118. In other words, each emitting element array 118 is integrally formed.
  • the potential of each lower metal electrode 220 is obtained.
  • scanning is sequentially performed for each pixel, and an electron beam is emitted from the emitting element array 118 (dot sequential driving).
  • the plurality of electron-emitting devices 210 of the emitting device array 118 constituting one pixel are integrally driven by the active matrix driving circuit 114 and the like.
  • the light receiving substrate unit 120 includes a transparent glass substrate 121, an anode electrode layer 122 (transparent electrode) laminated on the back surface of the glass substrate 121, and a photoelectric layer laminated on the back surface of the anode electrode layer 122.
  • a conversion layer 123 the light receiving substrate 120 includes a circuit for supplying signals and voltages necessary for driving, a circuit for outputting the detected video signal, and the like.
  • the light incident from the surface of the glass substrate 121 generates electron / hole pairs corresponding to the light amount in the photoelectric conversion layer 123.
  • the generated holes are accelerated by the voltage applied to the anode electrode layer 122 and continuously collide with atoms constituting the photoelectric conversion layer 123 to generate new electron / hole pairs (avalanche multiplication). ).
  • the avalanche-multiplied holes are accumulated near the back surface of the photoelectric conversion layer 123 to form a hole pattern corresponding to the incident light image.
  • the mesh electrode 130 controls the trajectory of electrons emitted from the electron emission substrate unit 110 (imaging device array 113) and absorbs surplus electrons between the electron emission substrate unit 110 and the light receiving substrate unit 120. It is arranged. A voltage that is significantly higher than the drive voltage of the drive circuit layer 112 of the electron emission substrate 110 is applied to the mesh electrode 130.
  • Electrons emitted from the electron emission substrate portion 110 are drawn out to the photoelectric conversion layer 123 side by the voltage applied to the mesh electrode 130, and also by an electric field formed between the image sensor array 113 and the photoelectric conversion layer 123. And converged on the photoelectric conversion layer 123 (back surface). Then, the emitted electrons are combined with a hole pattern grown near the surface of the photoelectric conversion layer 123.
  • the imaging apparatus 100 obtains a video signal corresponding to an incident light image by detecting, as an output, a current when the electron and hole patterns are combined.
  • the active matrix drive circuit 114 formed in the drive circuit layer 112 will be described with reference to FIG. 4 and FIG.
  • the active matrix driving circuit 114 is provided for each pixel column 1 and a plurality of pixel transistors 1 (semiconductor devices) arranged in a matrix so as to correspond to the respective emission element arrays 118.
  • Column selection transistor 2 semiconductor device
  • the pixel transistor 1 includes a P-type P-type buried layer 11 and a semiconductor layer 12 formed on an N-type silicon substrate (not shown), and an N-type drain electrode formed in the semiconductor layer 12.
  • a drain region 13 having a layer 21, a source region 14 having an N-type source electrode layer 31 formed in the semiconductor layer 12, and an active region on the surface of the semiconductor layer 12 between the drain region 13 and the source region 14.
  • the pixel transistor 1 is a so-called one-side LOCOS offset type MOS transistor. Since the column selection transistor 2 has substantially the same structure as the pixel transistor 1, description thereof is omitted. However, since the source is grounded, the structure of the pixel transistor 1 and the source region 14 may not be the same. .
  • the drain electrode layer 21 of each pixel transistor 1 is connected to the lower metal electrode 220 of each emitting element array 118 through a via hole 117a provided in the insulating layer 117 (see FIG. 3). As shown in FIG. 4, the gate electrode 18 of each pixel transistor 1 is connected to the horizontal scanning circuit 115. The source electrode layer 31 of each pixel transistor 1 is connected to the drain electrode layer 21 of the column selection transistor 2 in the corresponding column with a low resistance.
  • each column selection transistor 2 is connected to the vertical scanning circuit 116.
  • the source electrode layer 31 of each column selection transistor 2 is grounded.
  • a control device (not shown) inputs a clock signal, a synchronization signal, and the like to the horizontal scanning circuit 115 and the vertical scanning circuit 116 and appropriately drives them to thereby drain the drain potential of the pixel transistor 1 disposed for each pixel (emission element array 118). That is, the potential of the lower metal electrode 220 of each emitter array 118 is controlled. Further, a high voltage (20 V) or a low voltage (0 V) is applied to the gate electrodes 18 of the transistors 1 and 2 via the horizontal scanning circuit 115 and the vertical scanning circuit 116. Thereby, the emission of electrons can be switched for each pixel.
  • the applied voltage (high voltage and low voltage) may be arbitrarily set.
  • a voltage (23 V) is applied to the drain electrode layer 21 of each pixel transistor 1.
  • the horizontal scanning circuit 115 and the vertical scanning circuit 116 select the corresponding row and column, and a high voltage (20 V) is applied to the gate electrode 18 of the center pixel transistor 1 and the corresponding gate electrode 18 of the column selection transistor 2. Applied (state (H, H)).
  • a through current flows through the center pixel transistor 1 and the column selection transistor 2 of the corresponding column.
  • the center pixel transistor 1 is selected.
  • hot electron injection occurs in the vicinity of the drain electrode layer 21 of the central pixel transistor 1.
  • the potential of the source electrode layer 31 of the central pixel transistor 1 is at the GND level (0 V).
  • a high voltage (20 V) is applied to the gate electrode 18 of this pixel transistor 1, and the column selection transistor of the corresponding column.
  • a low voltage (0 V) is applied to the second gate electrode 18 (states (H, L)). Also in this case, since no through current flows, hot electron injection does not occur, but the potential of the source electrode layer 31 is at a high voltage level (23 V).
  • the potential of the source electrode layer 31 is a value (about 19 V) lowered by the pinch-off voltage (about ⁇ 4 V).
  • each pixel transistor 1 is required not only to have a high drain breakdown voltage (high breakdown voltage of the drain region 13) but also to a state in which a high voltage is applied to the source region 14 (states (L, L) and It is also required to cope with the state (H, L). Further, since the imaging device 100 is required to increase the number of pixels of the imaging element array 113, the active matrix driving circuit 114 is also required to be highly integrated. For this reason, the pixel transistor 1 (column selection transistor 2) is preferably configured as a one-sided LOCOS offset type having a small transistor area.
  • a pixel transistor 1 semiconductor device that is a one-sided LOCOS offset type having a small transistor area and improved the withstand voltage of the source region 14 will be described. Since the column selection transistor 2 has the same structure as the pixel transistor 1, the description thereof is omitted hereinafter.
  • the pixel transistor 1 (semiconductor device) includes a P-type P-type buried layer 11 and a semiconductor layer 12 formed on an N-type silicon substrate (not shown), and an N-type formed on the semiconductor layer 12.
  • a type drain region 13, an N type source region 14, a gate oxide film 15, a LOCOS oxide film 16, a drift layer 17 and a gate electrode 18 are provided.
  • the drain region 13 has an N-type drain electrode layer 21 and an N-type drain electric field relaxation layer 22 that encloses the drain electrode layer 21.
  • the drain electric field relaxation layer 22 is formed adjacent to the drift layer 17.
  • the drain electrode layer 21 is formed in the drain electric field relaxation layer 22 and at a distance of 0.4 ⁇ m or more and 0.7 ⁇ m or less from the end of the LOCOS oxide film 16.
  • the impurity concentration of the drain electric field relaxation layer 22 is higher than the impurity concentration of the drift layer 17 and lower than the impurity concentration of the drain electrode layer 21. In this way, by making the concentration gradient of the impurity concentration from the drift layer 17 to the drain electrode layer 21 gentle, the electric field concentration is alleviated and the breakdown voltage of the drain region 13 is improved.
  • the drift layer 17 has an ion species of single charge phosphorus (P +), an acceleration voltage of 60 keV, and a dose of about 1.5 ⁇ 10 13 ions / cm 2 to 3.5 ⁇ 10 13 ions / cm 2. Preferably it is formed.
  • the drain electric field relaxation layer 22 is preferably formed with ion species of double-charged phosphorus (P ++), an acceleration voltage of 80 to 150 keV, and a dose of about 0.76 ⁇ 10 13 ions / cm 2 .
  • the drain electrode layer 21 has an ion species of single-charged arsenic (As +), an acceleration voltage of 50 keV, and a dose of about 2.0 ⁇ 10 15 ions / cm 2 to 4.0 ⁇ 10 15 ions / cm 2. It is preferable to be formed as.
  • the source region 14 includes an N-type source electrode layer 31 and an N-type source offset layer 32 that encloses the source electrode layer 31.
  • the source offset layer 32 is formed adjacent to the gate oxide film 15.
  • the source electrode layer 31 is formed in the source offset layer 32 and separated from the end of the gate oxide film 15 by 0.4 ⁇ m or more and 0.7 ⁇ m or less.
  • the impurity concentration of the source offset layer 32 is higher than that of the semiconductor layer 12 and lower than that of the source electrode layer 31.
  • the depletion layer is extended in both directions of the junction. .
  • the pressure resistance of the source region 14 (between the source electrode layer 31 and the semiconductor layer 12) can be improved while keeping the area small in the form of a one-side LOCOS offset MOS transistor.
  • the semiconductor layer 12 has an ion species of double-charged boron (B ++), an acceleration voltage of 150 keV, and a dose of about 0.1 ⁇ 10 13 ions / cm 2 to 0.3 ⁇ 10 13 ions / cm 2. Preferably it is formed.
  • the source offset layer 32 has an ion species of single-charge phosphorus (P +), an acceleration voltage of 100 to 160 kev, and a dose of 0.5 ⁇ 10 13 ions / cm 2 to 1.5 ⁇ 10 13 ions / cm. It is preferably formed as about 2 .
  • the source electrode layer 31 is made of single-charged arsenic (As +), the acceleration voltage is 50 keV, and the dose amount is about 2.0 ⁇ 10 15 ions / cm 2 to 4.0 ⁇ 10 15 ions / cm 2. It is preferable to be formed as.
  • the pixel transistor 1 (column selection transistor 2) configured as a one-side LOCOS offset type as described above is a both-side LOCOS offset type MOS in which the LOCOS oxide film 16 and the drift layer 17 are provided for the drain region 13 and the source region 14, respectively. Compared with a transistor, the transistor area can be reduced. The applicant of the present application reduces the transistor area by 22.5% when the one-side LOCOS offset type pixel transistor 1 (column selection transistor 2) is configured to have substantially the same driving capability as the double-sided LOCOS offset type MOS transistor. The result that can be done is confirmed.
  • FIGS. 6 and 7 are process cross-sectional views showing the manufacturing process of the pixel transistor 1.
  • a process for ensuring a breakdown voltage of 22 V or more between the source electrode layer 31 and the semiconductor layer 12 is shown.
  • a P-type buried layer 11 and a semiconductor layer 12 are sequentially formed on an N-type silicon substrate (not shown).
  • the semiconductor layer 12 is formed by epitaxial growth to a layer thickness of 3.05 ⁇ m or more.
  • a pad oxide film 41 is formed on the semiconductor layer 12, and a LOCOS isolation nitride film 42 is partially formed on the pad oxide film 41.
  • phosphorus (P) is implanted at a position to be a LOCOS offset region to form the drift layer 17.
  • the drift layer 17 is ion-implanted with a single charge of phosphorus (P +), an acceleration voltage of 60 keV, a dose of 2.3 ⁇ 10 13 ions / cm 2 and a 7 ° tilted rotational implantation. Is set to
  • the LOCOS oxide film 16 (film thickness 400 to 600 nm) is grown using the LOCOS isolation nitride film 42 as a mask. Thereafter, the LOCOS isolation nitride film 42 is removed, and ion implantation is performed on the semiconductor layer 12.
  • the ion implantation conditions into the semiconductor layer 12 are as follows: the ion species is boron (B ++ (divalent)), the acceleration voltage is 150 keV, and the dose is 0.23 ⁇ 10 13 ions / cm 2. Is set to
  • a gate oxide film 15 is formed on the semiconductor layer 12 as shown in FIG.
  • a first gate electrode film 18a made of polysilicon is formed on the gate oxide film 15 and the LOCOS oxide film 16.
  • phosphorus (P) is implanted into a position to be the drain region 13 of the semiconductor layer 12 to form the drain electric field relaxation layer 22.
  • the drain electric field relaxation layer 22 is ion-implanted under the condition that the ion species is double-charged phosphorus (P ++), the acceleration voltage is 150 keV, and the dose is 0.76 ⁇ 10 13 ions / cm 2. Is set to do.
  • a second gate electrode film 18b made of polysilicon is formed on the gate oxide film 15, as shown in FIG. Thereafter, the first gate electrode film 18a and the second gate electrode film 18b are removed by photoetching, leaving only the portion straddling the LOCOS oxide film 16 on the drain region 13 (drain electric field relaxation layer 22) side. Unnecessary portions are removed, and the first gate electrode film 18 a and the second gate electrode film 18 b formed across the LOCOS oxide film 16 become the gate electrode 18.
  • ions are implanted into the semiconductor layer 12 at a position to be the source region 14 to form a source offset layer 32.
  • the ion implantation conditions of the source offset layer 32 are set so that the ion implantation is phosphorus (P + (monovalent)), the acceleration voltage is 100 keV, the dose is 1.0E + 13 ions / cm 2 , and rotational implantation at 7 ° is performed. Has been.
  • the pressure resistance in the source region 14 can be improved. It is preferable to increase the depth of ion implantation (increase the acceleration voltage) so that the radius of curvature of the junction between the source offset layer 32 and the source offset layer 32 is increased. However, since ion implantation is performed from above the gate oxide film 15, the acceleration voltage is adjusted to such an extent that ions are not implanted directly below the gate oxide film 15 below the gate electrode 18 (140 keV or less in this embodiment).
  • sidewalls 43 are formed at both ends of the gate electrode 18, and the gate oxide film 15 located on the other side than the lower side of the gate electrode 18 is removed (etched).
  • the sidewall 43 is formed, but the formation of the sidewall 43 is optional.
  • the drain electric field relaxation layer 22 and the source offset layer 32 are masked with a photoresist (not shown), and then ions are implanted to form the drain electrode layer 21 and the source electrode layer. 31 is formed.
  • the drain electrode layer 21 is formed in the drain electric field relaxation layer 22 at a position 0.5 ⁇ m away from the end of the LOCOS oxide film 16.
  • the source electrode layer 31 is formed in the source offset layer 32 at a position 0.5 ⁇ m away from the end of the gate oxide film 15.
  • the ion implantation conditions for the drain electrode layer 21 and the source electrode layer 31 are as follows: the ion species is arsenic (As + (monovalent)), the acceleration voltage is 50 keV, the dose is 2.0 ⁇ 10 15 ions / cm 2 , and the inclination is 7 °. It is set to perform rotary injection.
  • the pixel transistor 1 (column selection transistor 2) having a small transistor area and improved breakdown voltage of the drain region 13 and the source region 14 can be manufactured.
  • the offset amount was changed by setting the impurity concentration of the source offset layer 32 to 1.3E + 17 / cm 3 and the junction depth to 0.3 ⁇ m.
  • the ion species is P +
  • the acceleration voltage is 100 keV
  • the dose is 1.0E + 13 ions / cm 2 .
  • the pressure resistance is low in the range where the offset amount is less than 0.4 ⁇ m, and the improvement in pressure resistance is confirmed when the offset amount is 0.4 ⁇ m or more. For this reason, by setting the offset amount (interval between the source electrode layer 31 and the gate oxide film 15) to 0.4 ⁇ m to 0.7 ⁇ m, it is possible to ensure the improvement of the pressure resistance in the source region 14. It is considered a thing. As a result, a breakdown voltage of 22 V or more can be achieved. Therefore, the pixel transistor 1 (column selection transistor 2) can be manufactured by arbitrarily selecting the offset amount and the impurity concentration so that a desired breakdown voltage can be obtained.
  • the pixel transistor 1 (column selection transistor 2) may be configured with an offset amount of 0.5 ⁇ m. preferable.
  • a plurality of pixel transistors 1 (column selection transistors 2) having a small transistor area and improved withstand voltage characteristics of the source region 14 are arranged in a matrix, thereby providing an active matrix having a high withstand voltage and a high degree of integration.
  • the drive circuit 114 can be configured. Thereby, the high-resolution imaging device 100 can be manufactured.
  • 1 pixel transistor, 2: column selection transistor, 12: semiconductor layer, 13: drain region, 14: source region, 15: gate oxide film, 16: LOCOS oxide film, 17: drift layer, 18: gate electrode, 21: Drain electrode layer, 22: Drain electric field relaxation layer, 31: Source electrode layer, 32: Source offset layer, 100: Imaging device, 114: Active matrix driving circuit, 115: Horizontal scanning circuit, 116: Vertical scanning circuit

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Le dispositif de l'invention est équipé : d'une couche semi-conductrice (12) d'un premier type de conductivité formée sur un substrat semi-conducteur; d'une région déversoir (13) possédant une couche d'électrode déversoir (21) d'un second type de conductivité formée sur la couche semi-conductrice (12); d'une région source (14) possédant une couche d'électrode déversoir (31) et une couche de décalage de source (32) d'un second type de conductivité formée sur la couche semi-conductrice (12); d'un film d'oxyde de grille (15) formé sur une région active de la surface de la couche semi-conductrice (12) entre la région déversoir (13) et la région source (14); d'un film d'oxyde LOCOS (16) formé à la surface de la couche semi-conductrice (12) entre la région déversoir (13) et le film d'oxyde de grille (15); et d'une électrode grille (18) formée sur le film d'oxyde de grille (15) et à cheval sur le film d'oxyde LOCOS (16). La couche de décalage de source (32) est formée de manière adjacente au film d'oxyde de grille (15). La densité d'impuretés dans la couche de décalage de source (32), est supérieure à celle de la couche semi-conductrice (12), et inférieure à celle de la couche d'électrode déversoir (31). La couche d'électrode déversoir (31) est formée séparément du film d'oxyde de grille (15) et à l'intérieur de la couche de décalage de source (32).
PCT/JP2011/006324 2011-11-11 2011-11-11 Dispositif à semi-conducteurs, et circuit d'entraînement de matrice active mettant en œuvre celui-ci WO2013069070A1 (fr)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563188A (ja) * 1991-06-24 1993-03-12 Nippondenso Co Ltd 半導体装置の製造方法
JP2000232224A (ja) * 1999-02-10 2000-08-22 Matsushita Electronics Industry Corp 半導体装置及びその製造方法
JP2002026140A (ja) * 2000-07-10 2002-01-25 Nec Corp 半導体装置及びその製造方法
JP2002124670A (ja) * 2000-10-19 2002-04-26 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2002134738A (ja) * 2000-10-19 2002-05-10 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2002176175A (ja) * 2000-09-21 2002-06-21 Texas Instruments Inc 自己整合チャンネルおよびドレイン拡張部を備えた高圧ドレイン拡張トランジスタ
JP2005228556A (ja) * 2004-02-12 2005-08-25 Pioneer Electronic Corp 電子放出素子を用いた光電変換装置および撮像装置
JP2006324346A (ja) * 2005-05-17 2006-11-30 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0563188A (ja) * 1991-06-24 1993-03-12 Nippondenso Co Ltd 半導体装置の製造方法
JP2000232224A (ja) * 1999-02-10 2000-08-22 Matsushita Electronics Industry Corp 半導体装置及びその製造方法
JP2002026140A (ja) * 2000-07-10 2002-01-25 Nec Corp 半導体装置及びその製造方法
JP2002176175A (ja) * 2000-09-21 2002-06-21 Texas Instruments Inc 自己整合チャンネルおよびドレイン拡張部を備えた高圧ドレイン拡張トランジスタ
JP2002124670A (ja) * 2000-10-19 2002-04-26 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2002134738A (ja) * 2000-10-19 2002-05-10 Sanyo Electric Co Ltd 半導体装置とその製造方法
JP2005228556A (ja) * 2004-02-12 2005-08-25 Pioneer Electronic Corp 電子放出素子を用いた光電変換装置および撮像装置
JP2006324346A (ja) * 2005-05-17 2006-11-30 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法

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