WO2013069070A1 - Semiconductor device and active matrix drive circuit using same - Google Patents

Semiconductor device and active matrix drive circuit using same Download PDF

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WO2013069070A1
WO2013069070A1 PCT/JP2011/006324 JP2011006324W WO2013069070A1 WO 2013069070 A1 WO2013069070 A1 WO 2013069070A1 JP 2011006324 W JP2011006324 W JP 2011006324W WO 2013069070 A1 WO2013069070 A1 WO 2013069070A1
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layer
oxide film
source
semiconductor
drain
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PCT/JP2011/006324
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French (fr)
Japanese (ja)
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周哲 秋山
大塚　正志
勝美 吉沢
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パイオニア株式会社
パイオニア・マイクロ・テクノロジー株式会社
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Priority to PCT/JP2011/006324 priority Critical patent/WO2013069070A1/en
Publication of WO2013069070A1 publication Critical patent/WO2013069070A1/en

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    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14614—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor having a special gate structure
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
    • H—ELECTRICITY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L27/144—Devices controlled by radiation
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    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14687—Wafer level processing
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

Definitions

  • the present invention relates to a semiconductor device including a one-side LOCOS offset type MOS transistor and an active matrix driving circuit using the same.
  • a drain region composed of a P-type field relaxation layer and a P-type high-concentration drain layer formed in an N-type semiconductor layer a source region composed of a P-type high-concentration source layer, a drain region and a source region
  • a gate oxide film formed in the active region on the semiconductor layer surface a LOCOS oxide film formed on the semiconductor layer surface between the drain region and the gate oxide film, and formed on the gate oxide film across the LOCOS oxide film
  • a semiconductor device including a one-side LOCOS offset type (offset drain type) MOS transistor having a gate electrode formed and a P-type drift layer (offset layer) formed under a LOCOS oxide film (patent) Reference 1).
  • the electric field relaxation layer is adjacent to the drift layer, and the impurity concentration of the electric field relaxation layer is higher than that of the drift layer and thinner than that of the high concentration drain layer.
  • the high-concentration drain layer is included in the electric field relaxation layer and is separated from the end of the LOCOS oxide film. For this reason, the impurity concentration gradient near the bird's beak at the end of the LOCOS oxide film is gentle. Thereby, the breakdown voltage in the drain region is improved.
  • the conventional semiconductor device has a problem that a high voltage cannot be applied to the drain region because the breakdown voltage of the source region is low.
  • the breakdown voltage in the source region can be improved by adopting the double-sided LOCOS offset type in which the LOCOS oxide film and the drift layer are provided in the source region as well as the drift region.
  • the double-sided LOCOS offset type MOS transistor has a larger area than the one-sided LOCOS offset type, and thus it has been difficult to apply to an integrated circuit that requires miniaturization.
  • the semiconductor device of the present invention includes a first conductivity type semiconductor layer formed on a semiconductor substrate, a drain region having a second conductivity type drain electrode layer formed on the semiconductor layer, and a first region formed on the semiconductor layer.
  • a source region having a source offset layer and a source electrode layer of two conductivity types, a gate oxide film formed in an active region on the surface of the semiconductor layer between the drain region and the source region, and between the drain region and the gate oxide film A LOCOS oxide film formed on the surface of the semiconductor layer; and a gate electrode formed on the gate oxide film across the LOCOS oxide film.
  • the source offset layer is formed adjacent to the gate oxide film,
  • the impurity concentration of the offset layer is higher than the impurity concentration of the semiconductor layer and lower than the impurity concentration of the source electrode layer, and the source electrode layer is separated from the gate oxide film. Characterized in that it is formed over the scan offset layer.
  • the source electrode layer is formed in the source offset layer and at a position separated from the gate oxide film.
  • the impurity concentration of the source offset layer is higher than that of the semiconductor layer and lower than that of the source electrode layer.
  • the source electrode layer is preferably formed to be separated from the end of the gate oxide film by 0.4 ⁇ m or more and 0.7 ⁇ m or less.
  • the impurity concentration of the source offset layer is preferably 1.4E + 16 / cm 3 or more and 1.3E + 17 / cm 3 or less.
  • the junction depth of the source offset layer with respect to the semiconductor layer is preferably 0.3 ⁇ m or more and 1.0 ⁇ m or less.
  • the reduction of the transistor area and the improvement of the breakdown voltage of the source region can be achieved at a high level.
  • the drain electric field relaxation layer further includes a drain region having a second conductivity type drain electric field relaxation layer including the drain electrode layer, and a second conductivity type drift layer formed under the LOCOS oxide film. Is formed adjacent to the drift layer, the impurity concentration of the drain electric field relaxation layer is higher than the impurity concentration of the drift layer and lower than the impurity concentration of the drain electrode layer, and the drain electrode layer is formed of a LOCOS oxide film. It is preferably formed by self-alignment as a mask.
  • the drain electrode layer is formed in the drain electric field relaxation layer.
  • the impurity concentration of the drain electric field relaxation layer is higher than that of the drift layer and lower than that of the drain electrode layer. For this reason, since the concentration gradient of the impurity concentration from the drift layer to the drain electrode layer becomes gentle, the electric field concentration is alleviated and the breakdown voltage of the drain region is improved.
  • An active matrix driving circuit includes a semiconductor array in which a plurality of the above semiconductor devices are arranged in a matrix, a horizontal scanning circuit that scans and switches the semiconductor array in the horizontal direction, and the semiconductor array in the vertical direction. And a vertical scanning circuit that performs scanning and switching.
  • a high active matrix driving circuit can be configured. Thereby, for example, it can be used as a drive circuit for a high-resolution imaging device or the like.
  • This imaging apparatus includes an imaging device in which an electron-emitting device array in which a plurality of so-called surface conduction type electron-emitting devices are arranged in a matrix functions as one pixel.
  • FIG. 1 is a side sectional view schematically showing the configuration of the imaging apparatus 100.
  • FIG. 2 is a perspective view schematically showing the configuration of the electron emission substrate portion 110.
  • FIG. 3 is a side sectional view schematically showing the structure of the imaging element array 113 (electron emission element 210).
  • the imaging apparatus 100 includes an electron emission substrate unit 110 in which a plurality of electron emission elements 210 are formed, and the electron emission substrate unit 110 facing the electron emission substrate unit 110 with a vacuum space, and A light receiving substrate unit 120 serving as a target, and a mesh electrode 130 that is spaced between the electron emission substrate unit 110 and the light receiving substrate unit 120 and controls the trajectory of emitted electrons are provided.
  • the electron emission substrate section 110 includes a silicon substrate 111, a drive circuit layer 112 formed on the silicon substrate 111, and an image sensor array 113 formed on the drive circuit layer 112. ,have.
  • an active matrix drive circuit 114 (switch circuit) for driving a plurality of imaging element arrays 113 (electron emission elements 210) is formed on a silicon substrate 111.
  • a horizontal scanning circuit 115 and a vertical scanning circuit 116 for controlling the active matrix driving circuit 114 are disposed on the periphery of the silicon substrate 111.
  • the image sensor array 113 is stacked on the drive circuit layer 112 (active matrix drive circuit 114) via an insulating layer 117.
  • the imaging element array 113 is configured by a plurality of emission element arrays 118 functioning as one pixel arranged in a matrix.
  • the emitter array 118 includes a plurality of electron-emitting devices 210 that emit electrons (emit an electron beam) in a matrix.
  • Each electron-emitting device 210 is formed by laminating a lower metal electrode 220, a silicon layer 230, a silicon oxide layer 240, an upper metal electrode 250, and a carbon thin film 260 in this order.
  • a surface emission portion 270 (emission site) from which electrons are emitted is formed on the surface of each electron-emitting device 210 so as to be recessed to the surface of the silicon layer 230.
  • the silicon oxide layer 240, the upper metal electrode 250, and the carbon thin film 260 are common to all pixels. That is, it is configured integrally with all the emitting element arrays 118.
  • the lower metal electrode 220 and the silicon layer 230 are divided for each emitting element array 118. In other words, each emitting element array 118 is integrally formed.
  • the potential of each lower metal electrode 220 is obtained.
  • scanning is sequentially performed for each pixel, and an electron beam is emitted from the emitting element array 118 (dot sequential driving).
  • the plurality of electron-emitting devices 210 of the emitting device array 118 constituting one pixel are integrally driven by the active matrix driving circuit 114 and the like.
  • the light receiving substrate unit 120 includes a transparent glass substrate 121, an anode electrode layer 122 (transparent electrode) laminated on the back surface of the glass substrate 121, and a photoelectric layer laminated on the back surface of the anode electrode layer 122.
  • a conversion layer 123 the light receiving substrate 120 includes a circuit for supplying signals and voltages necessary for driving, a circuit for outputting the detected video signal, and the like.
  • the light incident from the surface of the glass substrate 121 generates electron / hole pairs corresponding to the light amount in the photoelectric conversion layer 123.
  • the generated holes are accelerated by the voltage applied to the anode electrode layer 122 and continuously collide with atoms constituting the photoelectric conversion layer 123 to generate new electron / hole pairs (avalanche multiplication). ).
  • the avalanche-multiplied holes are accumulated near the back surface of the photoelectric conversion layer 123 to form a hole pattern corresponding to the incident light image.
  • the mesh electrode 130 controls the trajectory of electrons emitted from the electron emission substrate unit 110 (imaging device array 113) and absorbs surplus electrons between the electron emission substrate unit 110 and the light receiving substrate unit 120. It is arranged. A voltage that is significantly higher than the drive voltage of the drive circuit layer 112 of the electron emission substrate 110 is applied to the mesh electrode 130.
  • Electrons emitted from the electron emission substrate portion 110 are drawn out to the photoelectric conversion layer 123 side by the voltage applied to the mesh electrode 130, and also by an electric field formed between the image sensor array 113 and the photoelectric conversion layer 123. And converged on the photoelectric conversion layer 123 (back surface). Then, the emitted electrons are combined with a hole pattern grown near the surface of the photoelectric conversion layer 123.
  • the imaging apparatus 100 obtains a video signal corresponding to an incident light image by detecting, as an output, a current when the electron and hole patterns are combined.
  • the active matrix drive circuit 114 formed in the drive circuit layer 112 will be described with reference to FIG. 4 and FIG.
  • the active matrix driving circuit 114 is provided for each pixel column 1 and a plurality of pixel transistors 1 (semiconductor devices) arranged in a matrix so as to correspond to the respective emission element arrays 118.
  • Column selection transistor 2 semiconductor device
  • the pixel transistor 1 includes a P-type P-type buried layer 11 and a semiconductor layer 12 formed on an N-type silicon substrate (not shown), and an N-type drain electrode formed in the semiconductor layer 12.
  • a drain region 13 having a layer 21, a source region 14 having an N-type source electrode layer 31 formed in the semiconductor layer 12, and an active region on the surface of the semiconductor layer 12 between the drain region 13 and the source region 14.
  • the pixel transistor 1 is a so-called one-side LOCOS offset type MOS transistor. Since the column selection transistor 2 has substantially the same structure as the pixel transistor 1, description thereof is omitted. However, since the source is grounded, the structure of the pixel transistor 1 and the source region 14 may not be the same. .
  • the drain electrode layer 21 of each pixel transistor 1 is connected to the lower metal electrode 220 of each emitting element array 118 through a via hole 117a provided in the insulating layer 117 (see FIG. 3). As shown in FIG. 4, the gate electrode 18 of each pixel transistor 1 is connected to the horizontal scanning circuit 115. The source electrode layer 31 of each pixel transistor 1 is connected to the drain electrode layer 21 of the column selection transistor 2 in the corresponding column with a low resistance.
  • each column selection transistor 2 is connected to the vertical scanning circuit 116.
  • the source electrode layer 31 of each column selection transistor 2 is grounded.
  • a control device (not shown) inputs a clock signal, a synchronization signal, and the like to the horizontal scanning circuit 115 and the vertical scanning circuit 116 and appropriately drives them to thereby drain the drain potential of the pixel transistor 1 disposed for each pixel (emission element array 118). That is, the potential of the lower metal electrode 220 of each emitter array 118 is controlled. Further, a high voltage (20 V) or a low voltage (0 V) is applied to the gate electrodes 18 of the transistors 1 and 2 via the horizontal scanning circuit 115 and the vertical scanning circuit 116. Thereby, the emission of electrons can be switched for each pixel.
  • the applied voltage (high voltage and low voltage) may be arbitrarily set.
  • a voltage (23 V) is applied to the drain electrode layer 21 of each pixel transistor 1.
  • the horizontal scanning circuit 115 and the vertical scanning circuit 116 select the corresponding row and column, and a high voltage (20 V) is applied to the gate electrode 18 of the center pixel transistor 1 and the corresponding gate electrode 18 of the column selection transistor 2. Applied (state (H, H)).
  • a through current flows through the center pixel transistor 1 and the column selection transistor 2 of the corresponding column.
  • the center pixel transistor 1 is selected.
  • hot electron injection occurs in the vicinity of the drain electrode layer 21 of the central pixel transistor 1.
  • the potential of the source electrode layer 31 of the central pixel transistor 1 is at the GND level (0 V).
  • a high voltage (20 V) is applied to the gate electrode 18 of this pixel transistor 1, and the column selection transistor of the corresponding column.
  • a low voltage (0 V) is applied to the second gate electrode 18 (states (H, L)). Also in this case, since no through current flows, hot electron injection does not occur, but the potential of the source electrode layer 31 is at a high voltage level (23 V).
  • the potential of the source electrode layer 31 is a value (about 19 V) lowered by the pinch-off voltage (about ⁇ 4 V).
  • each pixel transistor 1 is required not only to have a high drain breakdown voltage (high breakdown voltage of the drain region 13) but also to a state in which a high voltage is applied to the source region 14 (states (L, L) and It is also required to cope with the state (H, L). Further, since the imaging device 100 is required to increase the number of pixels of the imaging element array 113, the active matrix driving circuit 114 is also required to be highly integrated. For this reason, the pixel transistor 1 (column selection transistor 2) is preferably configured as a one-sided LOCOS offset type having a small transistor area.
  • a pixel transistor 1 semiconductor device that is a one-sided LOCOS offset type having a small transistor area and improved the withstand voltage of the source region 14 will be described. Since the column selection transistor 2 has the same structure as the pixel transistor 1, the description thereof is omitted hereinafter.
  • the pixel transistor 1 (semiconductor device) includes a P-type P-type buried layer 11 and a semiconductor layer 12 formed on an N-type silicon substrate (not shown), and an N-type formed on the semiconductor layer 12.
  • a type drain region 13, an N type source region 14, a gate oxide film 15, a LOCOS oxide film 16, a drift layer 17 and a gate electrode 18 are provided.
  • the drain region 13 has an N-type drain electrode layer 21 and an N-type drain electric field relaxation layer 22 that encloses the drain electrode layer 21.
  • the drain electric field relaxation layer 22 is formed adjacent to the drift layer 17.
  • the drain electrode layer 21 is formed in the drain electric field relaxation layer 22 and at a distance of 0.4 ⁇ m or more and 0.7 ⁇ m or less from the end of the LOCOS oxide film 16.
  • the impurity concentration of the drain electric field relaxation layer 22 is higher than the impurity concentration of the drift layer 17 and lower than the impurity concentration of the drain electrode layer 21. In this way, by making the concentration gradient of the impurity concentration from the drift layer 17 to the drain electrode layer 21 gentle, the electric field concentration is alleviated and the breakdown voltage of the drain region 13 is improved.
  • the drift layer 17 has an ion species of single charge phosphorus (P +), an acceleration voltage of 60 keV, and a dose of about 1.5 ⁇ 10 13 ions / cm 2 to 3.5 ⁇ 10 13 ions / cm 2. Preferably it is formed.
  • the drain electric field relaxation layer 22 is preferably formed with ion species of double-charged phosphorus (P ++), an acceleration voltage of 80 to 150 keV, and a dose of about 0.76 ⁇ 10 13 ions / cm 2 .
  • the drain electrode layer 21 has an ion species of single-charged arsenic (As +), an acceleration voltage of 50 keV, and a dose of about 2.0 ⁇ 10 15 ions / cm 2 to 4.0 ⁇ 10 15 ions / cm 2. It is preferable to be formed as.
  • the source region 14 includes an N-type source electrode layer 31 and an N-type source offset layer 32 that encloses the source electrode layer 31.
  • the source offset layer 32 is formed adjacent to the gate oxide film 15.
  • the source electrode layer 31 is formed in the source offset layer 32 and separated from the end of the gate oxide film 15 by 0.4 ⁇ m or more and 0.7 ⁇ m or less.
  • the impurity concentration of the source offset layer 32 is higher than that of the semiconductor layer 12 and lower than that of the source electrode layer 31.
  • the depletion layer is extended in both directions of the junction. .
  • the pressure resistance of the source region 14 (between the source electrode layer 31 and the semiconductor layer 12) can be improved while keeping the area small in the form of a one-side LOCOS offset MOS transistor.
  • the semiconductor layer 12 has an ion species of double-charged boron (B ++), an acceleration voltage of 150 keV, and a dose of about 0.1 ⁇ 10 13 ions / cm 2 to 0.3 ⁇ 10 13 ions / cm 2. Preferably it is formed.
  • the source offset layer 32 has an ion species of single-charge phosphorus (P +), an acceleration voltage of 100 to 160 kev, and a dose of 0.5 ⁇ 10 13 ions / cm 2 to 1.5 ⁇ 10 13 ions / cm. It is preferably formed as about 2 .
  • the source electrode layer 31 is made of single-charged arsenic (As +), the acceleration voltage is 50 keV, and the dose amount is about 2.0 ⁇ 10 15 ions / cm 2 to 4.0 ⁇ 10 15 ions / cm 2. It is preferable to be formed as.
  • the pixel transistor 1 (column selection transistor 2) configured as a one-side LOCOS offset type as described above is a both-side LOCOS offset type MOS in which the LOCOS oxide film 16 and the drift layer 17 are provided for the drain region 13 and the source region 14, respectively. Compared with a transistor, the transistor area can be reduced. The applicant of the present application reduces the transistor area by 22.5% when the one-side LOCOS offset type pixel transistor 1 (column selection transistor 2) is configured to have substantially the same driving capability as the double-sided LOCOS offset type MOS transistor. The result that can be done is confirmed.
  • FIGS. 6 and 7 are process cross-sectional views showing the manufacturing process of the pixel transistor 1.
  • a process for ensuring a breakdown voltage of 22 V or more between the source electrode layer 31 and the semiconductor layer 12 is shown.
  • a P-type buried layer 11 and a semiconductor layer 12 are sequentially formed on an N-type silicon substrate (not shown).
  • the semiconductor layer 12 is formed by epitaxial growth to a layer thickness of 3.05 ⁇ m or more.
  • a pad oxide film 41 is formed on the semiconductor layer 12, and a LOCOS isolation nitride film 42 is partially formed on the pad oxide film 41.
  • phosphorus (P) is implanted at a position to be a LOCOS offset region to form the drift layer 17.
  • the drift layer 17 is ion-implanted with a single charge of phosphorus (P +), an acceleration voltage of 60 keV, a dose of 2.3 ⁇ 10 13 ions / cm 2 and a 7 ° tilted rotational implantation. Is set to
  • the LOCOS oxide film 16 (film thickness 400 to 600 nm) is grown using the LOCOS isolation nitride film 42 as a mask. Thereafter, the LOCOS isolation nitride film 42 is removed, and ion implantation is performed on the semiconductor layer 12.
  • the ion implantation conditions into the semiconductor layer 12 are as follows: the ion species is boron (B ++ (divalent)), the acceleration voltage is 150 keV, and the dose is 0.23 ⁇ 10 13 ions / cm 2. Is set to
  • a gate oxide film 15 is formed on the semiconductor layer 12 as shown in FIG.
  • a first gate electrode film 18a made of polysilicon is formed on the gate oxide film 15 and the LOCOS oxide film 16.
  • phosphorus (P) is implanted into a position to be the drain region 13 of the semiconductor layer 12 to form the drain electric field relaxation layer 22.
  • the drain electric field relaxation layer 22 is ion-implanted under the condition that the ion species is double-charged phosphorus (P ++), the acceleration voltage is 150 keV, and the dose is 0.76 ⁇ 10 13 ions / cm 2. Is set to do.
  • a second gate electrode film 18b made of polysilicon is formed on the gate oxide film 15, as shown in FIG. Thereafter, the first gate electrode film 18a and the second gate electrode film 18b are removed by photoetching, leaving only the portion straddling the LOCOS oxide film 16 on the drain region 13 (drain electric field relaxation layer 22) side. Unnecessary portions are removed, and the first gate electrode film 18 a and the second gate electrode film 18 b formed across the LOCOS oxide film 16 become the gate electrode 18.
  • ions are implanted into the semiconductor layer 12 at a position to be the source region 14 to form a source offset layer 32.
  • the ion implantation conditions of the source offset layer 32 are set so that the ion implantation is phosphorus (P + (monovalent)), the acceleration voltage is 100 keV, the dose is 1.0E + 13 ions / cm 2 , and rotational implantation at 7 ° is performed. Has been.
  • the pressure resistance in the source region 14 can be improved. It is preferable to increase the depth of ion implantation (increase the acceleration voltage) so that the radius of curvature of the junction between the source offset layer 32 and the source offset layer 32 is increased. However, since ion implantation is performed from above the gate oxide film 15, the acceleration voltage is adjusted to such an extent that ions are not implanted directly below the gate oxide film 15 below the gate electrode 18 (140 keV or less in this embodiment).
  • sidewalls 43 are formed at both ends of the gate electrode 18, and the gate oxide film 15 located on the other side than the lower side of the gate electrode 18 is removed (etched).
  • the sidewall 43 is formed, but the formation of the sidewall 43 is optional.
  • the drain electric field relaxation layer 22 and the source offset layer 32 are masked with a photoresist (not shown), and then ions are implanted to form the drain electrode layer 21 and the source electrode layer. 31 is formed.
  • the drain electrode layer 21 is formed in the drain electric field relaxation layer 22 at a position 0.5 ⁇ m away from the end of the LOCOS oxide film 16.
  • the source electrode layer 31 is formed in the source offset layer 32 at a position 0.5 ⁇ m away from the end of the gate oxide film 15.
  • the ion implantation conditions for the drain electrode layer 21 and the source electrode layer 31 are as follows: the ion species is arsenic (As + (monovalent)), the acceleration voltage is 50 keV, the dose is 2.0 ⁇ 10 15 ions / cm 2 , and the inclination is 7 °. It is set to perform rotary injection.
  • the pixel transistor 1 (column selection transistor 2) having a small transistor area and improved breakdown voltage of the drain region 13 and the source region 14 can be manufactured.
  • the offset amount was changed by setting the impurity concentration of the source offset layer 32 to 1.3E + 17 / cm 3 and the junction depth to 0.3 ⁇ m.
  • the ion species is P +
  • the acceleration voltage is 100 keV
  • the dose is 1.0E + 13 ions / cm 2 .
  • the pressure resistance is low in the range where the offset amount is less than 0.4 ⁇ m, and the improvement in pressure resistance is confirmed when the offset amount is 0.4 ⁇ m or more. For this reason, by setting the offset amount (interval between the source electrode layer 31 and the gate oxide film 15) to 0.4 ⁇ m to 0.7 ⁇ m, it is possible to ensure the improvement of the pressure resistance in the source region 14. It is considered a thing. As a result, a breakdown voltage of 22 V or more can be achieved. Therefore, the pixel transistor 1 (column selection transistor 2) can be manufactured by arbitrarily selecting the offset amount and the impurity concentration so that a desired breakdown voltage can be obtained.
  • the pixel transistor 1 (column selection transistor 2) may be configured with an offset amount of 0.5 ⁇ m. preferable.
  • a plurality of pixel transistors 1 (column selection transistors 2) having a small transistor area and improved withstand voltage characteristics of the source region 14 are arranged in a matrix, thereby providing an active matrix having a high withstand voltage and a high degree of integration.
  • the drive circuit 114 can be configured. Thereby, the high-resolution imaging device 100 can be manufactured.
  • 1 pixel transistor, 2: column selection transistor, 12: semiconductor layer, 13: drain region, 14: source region, 15: gate oxide film, 16: LOCOS oxide film, 17: drift layer, 18: gate electrode, 21: Drain electrode layer, 22: Drain electric field relaxation layer, 31: Source electrode layer, 32: Source offset layer, 100: Imaging device, 114: Active matrix driving circuit, 115: Horizontal scanning circuit, 116: Vertical scanning circuit

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Abstract

In the present invention, the following are provided: a first conducting semiconductor layer (12) formed on top of a semiconductor substrate; a drain region (13) formed on the semiconductor layer (12) and having a second conducting drain electrode layer (21); a source region (14) formed on the semiconductor layer (12) and having a second conducting source offset layer (32) and a source electrode layer (31); a gate oxide film (15) formed between the drain region (13) and the source region (14) on an active region on the surface of the semiconductor layer (12); a LOCOS oxide film (16) formed between the drain region (13) and the gate oxide film (15) on the surface of the semiconductor layer (12); and a gate electrode (18) formed on top of the gate oxide film (15) so as to straddle the LOCOS oxide film (16). The source offset layer (32) is formed adjacent to the gate oxide film (15), and the concentration of impurities in the source offset layer (32) is higher than that of the semiconductor layer (12) and lower than that of the source electrode layer (31). The source electrode layer (31) is formed within the source offset layer (32) at a distance from the gate oxide film (15).

Description

半導体装置およびこれを用いたアクティブマトリクス駆動回路Semiconductor device and active matrix drive circuit using the same
　片側ＬＯＣＯＳオフセット型のＭＯＳトランジスタを含む半導体装置およびこれを用いたアクティブマトリクス駆動回路に関する。 TECHNICAL FIELD The present invention relates to a semiconductor device including a one-side LOCOS offset type MOS transistor and an active matrix driving circuit using the same.
　従来、Ｎ型の半導体層に形成されたＰ型の電界緩和層およびＰ型の高濃度ドレイン層から成るドレイン領域と、Ｐ型の高濃度ソース層から成るソース領域と、ドレイン領域とソース領域の間で半導体層表面の活性領域に形成されたゲート酸化膜と、ドレイン領域とゲート酸化膜の間の半導体層表面に形成されたＬＯＣＯＳ酸化膜と、ゲート酸化膜上にＬＯＣＯＳ酸化膜に跨って形成されたゲート電極と、ＬＯＣＯＳ酸化膜下に形成されたＰ型のドリフト層（オフセット層）と、を備えた片側ＬＯＣＯＳオフセット型（オフセットドレイン型）ＭＯＳトランジスタを含む半導体装置が知られている（特許文献１参照）。 Conventionally, a drain region composed of a P-type field relaxation layer and a P-type high-concentration drain layer formed in an N-type semiconductor layer, a source region composed of a P-type high-concentration source layer, a drain region and a source region A gate oxide film formed in the active region on the semiconductor layer surface, a LOCOS oxide film formed on the semiconductor layer surface between the drain region and the gate oxide film, and formed on the gate oxide film across the LOCOS oxide film There is known a semiconductor device including a one-side LOCOS offset type (offset drain type) MOS transistor having a gate electrode formed and a P-type drift layer (offset layer) formed under a LOCOS oxide film (patent) Reference 1).
　この半導体装置では、電界緩和層がドリフト層に隣接しており、電界緩和層の不純物濃度がドリフト層よりも濃く、且つ、高濃度ドレイン層よりも薄く形成されている。また、高濃度ドレイン層は、電界緩和層に内包されており、ＬＯＣＯＳ酸化膜の端部から離間して形成されている。このため、ＬＯＣＯＳ酸化膜端のバーズビーク付近における不純物の濃度勾配が緩やかになっている。これにより、ドレイン領域における耐圧を向上させている。 In this semiconductor device, the electric field relaxation layer is adjacent to the drift layer, and the impurity concentration of the electric field relaxation layer is higher than that of the drift layer and thinner than that of the high concentration drain layer. The high-concentration drain layer is included in the electric field relaxation layer and is separated from the end of the LOCOS oxide film. For this reason, the impurity concentration gradient near the bird's beak at the end of the LOCOS oxide film is gentle. Thereby, the breakdown voltage in the drain region is improved.
特開２００６－３２４３４６号公報JP 2006-324346 A
　しかし、従来の半導体装置では、ソース領域の耐圧が低いため、ドレイン領域に高電圧を印加することができないという問題があった。 However, the conventional semiconductor device has a problem that a high voltage cannot be applied to the drain region because the breakdown voltage of the source region is low.
　この場合、ドリフト領域と同様に、ソース領域に対してもＬＯＣＯＳ酸化膜およびドリフト層を設ける両側ＬＯＣＯＳオフセット型にすることで、ソース領域における耐圧の向上を図ることができる。しかし、両側ＬＯＣＯＳオフセット型のＭＯＳトランジスタは、片側ＬＯＣＯＳオフセット型に比べて、面積が大きくなるため、微細化が求められる集積回路に適用することが困難であった。 In this case, the breakdown voltage in the source region can be improved by adopting the double-sided LOCOS offset type in which the LOCOS oxide film and the drift layer are provided in the source region as well as the drift region. However, the double-sided LOCOS offset type MOS transistor has a larger area than the one-sided LOCOS offset type, and thus it has been difficult to apply to an integrated circuit that requires miniaturization.
　本発明は、上記の問題に鑑みて、トランジスタの面積を小さく維持しつつ、ソース領域の耐圧性を向上させることができる半導体装置およびこれを用いたアクティブマトリクス駆動回路を提供することを課題とする。 In view of the above problems, it is an object of the present invention to provide a semiconductor device capable of improving the withstand voltage of a source region while keeping the area of a transistor small and an active matrix driving circuit using the semiconductor device. .
　本発明の半導体装置は、半導体基板上に形成された第１導電型の半導体層と、半導体層に形成された第２導電型のドレイン電極層を有するドレイン領域と、半導体層に形成された第２導電型のソースオフセット層およびソース電極層を有するソース領域と、ドレイン領域とソース領域の間で半導体層の表面の活性領域に形成されたゲート酸化膜と、ドレイン領域とゲート酸化膜の間で半導体層の表面に形成されたＬＯＣＯＳ酸化膜と、ゲート酸化膜上にＬＯＣＯＳ酸化膜に跨って形成されたゲート電極と、を備え、ソースオフセット層は、ゲート酸化膜に隣接して形成され、ソースオフセット層の不純物濃度は、半導体層の不純物濃度よりも高く、かつ、ソース電極層の不純物濃度よりも低く、ソース電極層は、ゲート酸化膜から離間してソースオフセット層内に形成されていることを特徴とする。 The semiconductor device of the present invention includes a first conductivity type semiconductor layer formed on a semiconductor substrate, a drain region having a second conductivity type drain electrode layer formed on the semiconductor layer, and a first region formed on the semiconductor layer. A source region having a source offset layer and a source electrode layer of two conductivity types, a gate oxide film formed in an active region on the surface of the semiconductor layer between the drain region and the source region, and between the drain region and the gate oxide film A LOCOS oxide film formed on the surface of the semiconductor layer; and a gate electrode formed on the gate oxide film across the LOCOS oxide film. The source offset layer is formed adjacent to the gate oxide film, The impurity concentration of the offset layer is higher than the impurity concentration of the semiconductor layer and lower than the impurity concentration of the source electrode layer, and the source electrode layer is separated from the gate oxide film. Characterized in that it is formed over the scan offset layer.
　この構成によれば、ソース電極層が、ソースオフセット層内で、かつ、ゲート酸化膜から離間した位置に形成されている。また、ソースオフセット層の不純物濃度は、半導体層よりも高く、ソース電極層よりも低くなっている。このように、半導体層とソース電極層との間に、ソース電極層よりも低濃度の不純物領域となるソースオフセット層を形成することで、接合の両方向に空乏層が拡張される。これにより、片側ＬＯＣＯＳオフセット型ＭＯＳトランジスタの形態で面積を小さく維持しつつ、ソース領域（ソース電極層と半導体層との間）の耐圧性を向上させることができる。 According to this configuration, the source electrode layer is formed in the source offset layer and at a position separated from the gate oxide film. The impurity concentration of the source offset layer is higher than that of the semiconductor layer and lower than that of the source electrode layer. In this manner, by forming the source offset layer that becomes an impurity region having a lower concentration than the source electrode layer between the semiconductor layer and the source electrode layer, the depletion layer is extended in both directions of the junction. Thereby, the withstand voltage of the source region (between the source electrode layer and the semiconductor layer) can be improved while keeping the area small in the form of a one-side LOCOS offset type MOS transistor.
　この場合、ソース電極層は、ゲート酸化膜の端部から０．４μｍ以上、０．７μｍ以下離間して形成されていることが好ましい。 In this case, the source electrode layer is preferably formed to be separated from the end of the gate oxide film by 0.4 μm or more and 0.7 μm or less.
　またこの場合、ソースオフセット層の不純物濃度は、１．４Ｅ＋１６個／ｃｍ３以上、１．３Ｅ＋１７個／ｃｍ３以下であることが好ましい。 In this case, the impurity concentration of the source offset layer is preferably 1.4E + 16 / cm 3 or more and 1.3E + 17 / cm 3 or less.
　またこの場合、半導体層に対するソースオフセット層の接合深さは、０．３μｍ以上、１．０μｍ以下であることが好ましい。 In this case, the junction depth of the source offset layer with respect to the semiconductor layer is preferably 0.3 μm or more and 1.0 μm or less.
　この構成によれば、トランジスタ面積の縮小と、ソース領域の耐圧性の向上と、を高い水準で両立させることができる。 According to this configuration, the reduction of the transistor area and the improvement of the breakdown voltage of the source region can be achieved at a high level.
　この場合、ドレイン電極層を内包する第２導電型のドレイン電界緩和層を有したドレイン領域と、ＬＯＣＯＳ酸化膜下に形成された第２導電型のドリフト層と、を更に備え、ドレイン電界緩和層は、ドリフト層に隣接して形成され、ドレイン電界緩和層の不純物濃度は、ドリフト層の不純物濃度よりも高く、かつ、ドレイン電極層の不純物濃度よりも低く、ドレイン電極層は、ＬＯＣＯＳ酸化膜をマスクとしたセルフアラインで形成されていることが好ましい。 In this case, the drain electric field relaxation layer further includes a drain region having a second conductivity type drain electric field relaxation layer including the drain electrode layer, and a second conductivity type drift layer formed under the LOCOS oxide film. Is formed adjacent to the drift layer, the impurity concentration of the drain electric field relaxation layer is higher than the impurity concentration of the drift layer and lower than the impurity concentration of the drain electrode layer, and the drain electrode layer is formed of a LOCOS oxide film. It is preferably formed by self-alignment as a mask.
　この構成によれば、ドレイン電極層が、ドレイン電界緩和層内に形成されている。また、ドレイン電界緩和層の不純物濃度は、ドリフト層よりも高く、ドレイン電極層よりも低くなっている。このため、ドリフト層からドレイン電極層に至る不純物濃度の濃度勾配が緩やかになることで、電界集中が緩和され、ドレイン領域の耐圧性が向上する。 According to this configuration, the drain electrode layer is formed in the drain electric field relaxation layer. The impurity concentration of the drain electric field relaxation layer is higher than that of the drift layer and lower than that of the drain electrode layer. For this reason, since the concentration gradient of the impurity concentration from the drift layer to the drain electrode layer becomes gentle, the electric field concentration is alleviated and the breakdown voltage of the drain region is improved.
　本発明のアクティブマトリクス駆動回路は、上記のいずれかの半導体装置の複数をマトリクス状に配設した半導体アレイと、半導体アレイを水平方向に走査してスイッチングする水平走査回路と、半導体アレイを垂直方向に走査してスイッチングする垂直走査回路と、を備えていることを特徴とする。 An active matrix driving circuit according to the present invention includes a semiconductor array in which a plurality of the above semiconductor devices are arranged in a matrix, a horizontal scanning circuit that scans and switches the semiconductor array in the horizontal direction, and the semiconductor array in the vertical direction. And a vertical scanning circuit that performs scanning and switching.
　この構成によれば、トランジスタ面積が小さく、ソース領域（ソース電極層と半導体層との間）の耐圧性を向上させた複数の半導体装置をマトリクス状に配設することにより、高耐圧で集積度の高いアクティブマトリクス駆動回路を構成することができる。これにより、例えば、高解像度の撮像装置等の駆動回路として用いることができる。 According to this configuration, a plurality of semiconductor devices having a small transistor area and improved withstand voltage in the source region (between the source electrode layer and the semiconductor layer) are arranged in a matrix, thereby providing high integration with high withstand voltage. A high active matrix driving circuit can be configured. Thereby, for example, it can be used as a drive circuit for a high-resolution imaging device or the like.
撮像装置の構成を模式的に表した側断面図である。It is a side sectional view showing typically composition of an imaging device. 電子放出基板部の構成を模式的に表した斜視図である。It is the perspective view which represented typically the structure of the electron emission board | substrate part. 撮像素子アレイ（電子放出素子）の構造を模式的に表した側断面図である。It is a side sectional view showing typically the structure of an image sensor array (electron emission element). アクティブマトリクス駆動回路の構造を模式的に表した説明図である。It is explanatory drawing which represented the structure of the active matrix drive circuit typically. 画素トランジスタ（列選択トランジスタ）の構造を模式的に表した側断面図である。It is a sectional side view showing typically the structure of a pixel transistor (column selection transistor). 画素トランジスタ（列選択トランジスタ）の製造工程（前半）を表した工程断面図である。It is process sectional drawing showing the manufacturing process (first half) of a pixel transistor (column selection transistor). 画素トランジスタ（列選択トランジスタ）の製造工程（後半）を表した工程断面図である。It is process sectional drawing showing the manufacturing process (latter half) of the pixel transistor (column selection transistor). 実証例に係るソース領域の耐圧性との関係を示したグラフである。It is the graph which showed the relationship with the pressure | voltage resistance of the source region which concerns on a demonstration example.
　以下、添付した図面を参照して、本発明の一実施形態に係るアクティブマトリクス駆動回路を用いた撮像装置について説明する。この撮像装置は、いわゆる表面伝導型の電子放出素子の複数をマトリクス状に配設した電子放出素子アレイが１の画素として機能する撮像素子を備えたものである。 Hereinafter, an imaging apparatus using an active matrix driving circuit according to an embodiment of the present invention will be described with reference to the accompanying drawings. This imaging apparatus includes an imaging device in which an electron-emitting device array in which a plurality of so-called surface conduction type electron-emitting devices are arranged in a matrix functions as one pixel.
　図１は、撮像装置１００の構成を模式的に表した側断面図である。図２は、電子放出基板部１１０の構成を模式的に表した斜視図である。図３は、撮像素子アレイ１１３（電子放出素子２１０）の構造を模式的に表した側断面図である。 FIG. 1 is a side sectional view schematically showing the configuration of the imaging apparatus 100. FIG. 2 is a perspective view schematically showing the configuration of the electron emission substrate portion 110. FIG. 3 is a side sectional view schematically showing the structure of the imaging element array 113 (electron emission element 210).
　図１に示すように、撮像装置１００は、複数の電子放出素子２１０を作り込んだ電子放出基板部１１０と、電子放出基板部１１０と真空空間を存して対向配置され、放出された電子のターゲットとなる受光基板部１２０と、電子放出基板部１１０と受光基板部１２０との間に離間配置され、放出された電子の軌道を制御するメッシュ電極１３０と、を備えている。 As shown in FIG. 1, the imaging apparatus 100 includes an electron emission substrate unit 110 in which a plurality of electron emission elements 210 are formed, and the electron emission substrate unit 110 facing the electron emission substrate unit 110 with a vacuum space, and A light receiving substrate unit 120 serving as a target, and a mesh electrode 130 that is spaced between the electron emission substrate unit 110 and the light receiving substrate unit 120 and controls the trajectory of emitted electrons are provided.
　図１および図２に示すように、電子放出基板部１１０は、シリコン基板１１１と、シリコン基板１１１上に形成された駆動回路層１１２と、駆動回路層１１２上に形成された撮像素子アレイ１１３と、を有している。 As shown in FIGS. 1 and 2, the electron emission substrate section 110 includes a silicon substrate 111, a drive circuit layer 112 formed on the silicon substrate 111, and an image sensor array 113 formed on the drive circuit layer 112. ,have.
　駆動回路層１１２には、シリコン基板１１１上に、複数の撮像素子アレイ１１３（電子放出素子２１０）を駆動するアクティブマトリクス駆動回路１１４（スイッチ回路）が形成されている。シリコン基板１１１の周辺部には、アクティブマトリクス駆動回路１１４を制御する水平走査回路１１５および垂直走査回路１１６が、配設されている。 In the drive circuit layer 112, an active matrix drive circuit 114 (switch circuit) for driving a plurality of imaging element arrays 113 (electron emission elements 210) is formed on a silicon substrate 111. A horizontal scanning circuit 115 and a vertical scanning circuit 116 for controlling the active matrix driving circuit 114 are disposed on the periphery of the silicon substrate 111.
　図３に示すように、撮像素子アレイ１１３は、絶縁層１１７を介して駆動回路層１１２（アクティブマトリクス駆動回路１１４）上に積層されている。撮像素子アレイ１１３は、１の画素として機能する放出素子アレイ１１８が、マトリクス状に複数配設されて構成されている。放出素子アレイ１１８は、電子を放出（電子ビームを放射）する電子放出素子２１０が、マトリクス状に複数配設されて構成されている。 As shown in FIG. 3, the image sensor array 113 is stacked on the drive circuit layer 112 (active matrix drive circuit 114) via an insulating layer 117. The imaging element array 113 is configured by a plurality of emission element arrays 118 functioning as one pixel arranged in a matrix. The emitter array 118 includes a plurality of electron-emitting devices 210 that emit electrons (emit an electron beam) in a matrix.
　各電子放出素子２１０は、下部金属電極２２０、シリコン層２３０、酸化シリコン層２４０、上部金属電極２５０および炭素薄膜２６０の順に積層して形成されている。また、各電子放出素子２１０の表面には、電子が放出される面放出部２７０（エミッションサイト）が、シリコン層２３０の表面まで窪入形成されている。なお、本実施形態では、酸化シリコン層２４０、上部金属電極２５０および炭素薄膜２６０は、全画素共通となっている。つまり、全ての放出素子アレイ１１８に対して一体に構成されている。一方、下部金属電極２２０およびシリコン層２３０は、放出素子アレイ１１８毎に分割されている。つまり、放出素子アレイ１１８毎に一体に構成されている。 Each electron-emitting device 210 is formed by laminating a lower metal electrode 220, a silicon layer 230, a silicon oxide layer 240, an upper metal electrode 250, and a carbon thin film 260 in this order. In addition, a surface emission portion 270 (emission site) from which electrons are emitted is formed on the surface of each electron-emitting device 210 so as to be recessed to the surface of the silicon layer 230. In the present embodiment, the silicon oxide layer 240, the upper metal electrode 250, and the carbon thin film 260 are common to all pixels. That is, it is configured integrally with all the emitting element arrays 118. On the other hand, the lower metal electrode 220 and the silicon layer 230 are divided for each emitting element array 118. In other words, each emitting element array 118 is integrally formed.
　上部金属電極２５０に正の電圧を印加し、アクティブマトリクス駆動回路１１４を介して水平走査回路１１５および垂直走査回路１１６から、クロック信号や同期信号等を入力することで、各下部金属電極２２０の電位を制御する。これにより、画素毎に、順次走査され、放出素子アレイ１１８から電子ビームが放射される（点順次駆動）。なお、１の画素を構成する放出素子アレイ１１８の複数の電子放出素子２１０は、アクティブマトリクス駆動回路１１４等によって、一体として駆動される。 By applying a positive voltage to the upper metal electrode 250 and inputting a clock signal, a synchronization signal, or the like from the horizontal scanning circuit 115 and the vertical scanning circuit 116 via the active matrix driving circuit 114, the potential of each lower metal electrode 220 is obtained. To control. Accordingly, scanning is sequentially performed for each pixel, and an electron beam is emitted from the emitting element array 118 (dot sequential driving). Note that the plurality of electron-emitting devices 210 of the emitting device array 118 constituting one pixel are integrally driven by the active matrix driving circuit 114 and the like.
　図１に示すように、受光基板部１２０は、透明なガラス基板１２１と、ガラス基板１２１の裏面に積層されたアノード電極層１２２（透明電極）と、アノード電極層１２２の裏面に積層された光電変換層１２３と、を有している。また、図示は省略するが、受光基板部１２０は、駆動に必要な信号や電圧を供給する回路、検出した映像信号を出力する回路等も備えている。 As shown in FIG. 1, the light receiving substrate unit 120 includes a transparent glass substrate 121, an anode electrode layer 122 (transparent electrode) laminated on the back surface of the glass substrate 121, and a photoelectric layer laminated on the back surface of the anode electrode layer 122. A conversion layer 123. Although not shown, the light receiving substrate 120 includes a circuit for supplying signals and voltages necessary for driving, a circuit for outputting the detected video signal, and the like.
　ガラス基板１２１の表面から入射した光は、光電変換層１２３において、その光量に応じた電子・正孔対を生成させる。生成された正孔は、アノード電極層１２２に印加された電圧により加速され、光電変換層１２３を構成する原子と連続的に衝突して、新たな電子・正孔対を生成する（アバランシェ増倍）。アバランシェ増倍された正孔は、光電変換層１２３の裏面付近に蓄積され、入射光像に対応する正孔パターンを形成する。 The light incident from the surface of the glass substrate 121 generates electron / hole pairs corresponding to the light amount in the photoelectric conversion layer 123. The generated holes are accelerated by the voltage applied to the anode electrode layer 122 and continuously collide with atoms constituting the photoelectric conversion layer 123 to generate new electron / hole pairs (avalanche multiplication). ). The avalanche-multiplied holes are accumulated near the back surface of the photoelectric conversion layer 123 to form a hole pattern corresponding to the incident light image.
　メッシュ電極１３０は、電子放出基板部１１０（撮像素子アレイ１１３）から放出された電子の軌道を制御すると共に、余剰電子を吸収するために、電子放出基板部１１０と受光基板部１２０との間に配設されている。メッシュ電極１３０には、電子放出基板部１１０の駆動回路層１１２の駆動電圧に比べて格段に高い電圧が印加されている。 The mesh electrode 130 controls the trajectory of electrons emitted from the electron emission substrate unit 110 (imaging device array 113) and absorbs surplus electrons between the electron emission substrate unit 110 and the light receiving substrate unit 120. It is arranged. A voltage that is significantly higher than the drive voltage of the drive circuit layer 112 of the electron emission substrate 110 is applied to the mesh electrode 130.
　電子放出基板部１１０から放出された電子は、メッシュ電極１３０に印加された電圧によって、光電変換層１２３側に引き出されると共に、撮像素子アレイ１１３と光電変換層１２３との間に形成された電界によって、光電変換層１２３上（裏面）に収束される。そして、放出された電子は、光電変換層１２３の表面付近に成長した正孔パターンと結合する。この撮像装置１００は、電子と正孔パターンとの結合時の電流を出力として検出することで、入射光像に対応した映像信号を得ている。なお、受光基板部１２０（ガラス基板１２１）の表面にカラーフィルタを形成してもよい。かかる場合には、Ｒ・Ｇ・Ｂの画像（映像）を個々に取り込むことにより、カラーによる撮像が可能となる。 Electrons emitted from the electron emission substrate portion 110 are drawn out to the photoelectric conversion layer 123 side by the voltage applied to the mesh electrode 130, and also by an electric field formed between the image sensor array 113 and the photoelectric conversion layer 123. And converged on the photoelectric conversion layer 123 (back surface). Then, the emitted electrons are combined with a hole pattern grown near the surface of the photoelectric conversion layer 123. The imaging apparatus 100 obtains a video signal corresponding to an incident light image by detecting, as an output, a current when the electron and hole patterns are combined. In addition, you may form a color filter in the surface of the light-receiving substrate part 120 (glass substrate 121). In such a case, color images can be captured by individually capturing R, G, and B images (videos).
　次に、図４および図５を参照して、駆動回路層１１２に形成されたアクティブマトリクス駆動回路１１４について説明する。図４に示すように、アクティブマトリクス駆動回路１１４は、各放出素子アレイ１１８に対応するようにマトリクス状に配設された複数の画素トランジスタ１（半導体装置）と、マトリクスの列毎に配設された列選択トランジスタ２（半導体装置）と、を有している。 Next, the active matrix drive circuit 114 formed in the drive circuit layer 112 will be described with reference to FIG. 4 and FIG. As shown in FIG. 4, the active matrix driving circuit 114 is provided for each pixel column 1 and a plurality of pixel transistors 1 (semiconductor devices) arranged in a matrix so as to correspond to the respective emission element arrays 118. Column selection transistor 2 (semiconductor device).
　図５に示すように、画素トランジスタ１は、図外のＮ型シリコン基板上に形成されたＰ型のＰ型埋め込み層１１および半導体層１２と、半導体層１２に形成されたＮ型のドレイン電極層２１を有するドレイン領域１３と、半導体層１２に形成されたＮ型のソース電極層３１を有するソース領域１４と、ドレイン領域１３とソース領域１４の間で半導体層１２の表面の活性領域に形成されたゲート酸化膜１５と、ドレイン領域１３とゲート酸化膜１５の間で半導体層１２の表面に形成されたＬＯＣＯＳ酸化膜１６と、ＬＯＣＯＳ酸化膜１６下に形成されたＮ型のドリフト層１７と、ゲート酸化膜１５上にＬＯＣＯＳ酸化膜１６に跨って形成されたゲート電極１８と、を備えている。画素トランジスタ１は、いわゆる片側ＬＯＣＯＳオフセット型のＭＯＳトランジスタである。なお、列選択トランジスタ２は、画素トランジスタ１と略同様の構造であるため、その説明は省略するが、ソース接地されているため、画素トランジスタ１とソース領域１４の構造は同一でなくてもよい。 As shown in FIG. 5, the pixel transistor 1 includes a P-type P-type buried layer 11 and a semiconductor layer 12 formed on an N-type silicon substrate (not shown), and an N-type drain electrode formed in the semiconductor layer 12. A drain region 13 having a layer 21, a source region 14 having an N-type source electrode layer 31 formed in the semiconductor layer 12, and an active region on the surface of the semiconductor layer 12 between the drain region 13 and the source region 14. Gate oxide film 15, LOCOS oxide film 16 formed on the surface of semiconductor layer 12 between drain region 13 and gate oxide film 15, N-type drift layer 17 formed under LOCOS oxide film 16, and And a gate electrode 18 formed over the LOCOS oxide film 16 on the gate oxide film 15. The pixel transistor 1 is a so-called one-side LOCOS offset type MOS transistor. Since the column selection transistor 2 has substantially the same structure as the pixel transistor 1, description thereof is omitted. However, since the source is grounded, the structure of the pixel transistor 1 and the source region 14 may not be the same. .
　各画素トランジスタ１のドレイン電極層２１は、絶縁層１１７に設けられたビアホール１１７ａを介して各放出素子アレイ１１８の下部金属電極２２０に接続されている（図３参照）。図４に示すように、各画素トランジスタ１のゲート電極１８は、水平走査回路１１５に接続されている。また、各画素トランジスタ１のソース電極層３１は、該当する列の列選択トランジスタ２のドレイン電極層２１に低抵抗で接続されている。 The drain electrode layer 21 of each pixel transistor 1 is connected to the lower metal electrode 220 of each emitting element array 118 through a via hole 117a provided in the insulating layer 117 (see FIG. 3). As shown in FIG. 4, the gate electrode 18 of each pixel transistor 1 is connected to the horizontal scanning circuit 115. The source electrode layer 31 of each pixel transistor 1 is connected to the drain electrode layer 21 of the column selection transistor 2 in the corresponding column with a low resistance.
　各列選択トランジスタ２のゲート電極１８は、垂直走査回路１１６に接続されている。また、各列選択トランジスタ２のソース電極層３１は、接地されている。 The gate electrode 18 of each column selection transistor 2 is connected to the vertical scanning circuit 116. The source electrode layer 31 of each column selection transistor 2 is grounded.
　図外の制御装置は、水平走査回路１１５および垂直走査回路１１６にクロック信号や同期信号等を入力し適宜駆動することにより、画素（放出素子アレイ１１８）毎に配置された画素トランジスタ１のドレイン電位、すなわち各放出素子アレイ１１８の下部金属電極２２０の電位を制御する。また、水平走査回路１１５および垂直走査回路１１６を介して、各トランジスタ１，２のゲート電極１８に高電圧（２０Ｖ）または低電圧（０Ｖ）が印加される。これにより、画素毎に電子の放出を切り替えることができる。なお、印加する電圧（高電圧および低電圧）は、任意に設定してよい。 A control device (not shown) inputs a clock signal, a synchronization signal, and the like to the horizontal scanning circuit 115 and the vertical scanning circuit 116 and appropriately drives them to thereby drain the drain potential of the pixel transistor 1 disposed for each pixel (emission element array 118). That is, the potential of the lower metal electrode 220 of each emitter array 118 is controlled. Further, a high voltage (20 V) or a low voltage (0 V) is applied to the gate electrodes 18 of the transistors 1 and 2 via the horizontal scanning circuit 115 and the vertical scanning circuit 116. Thereby, the emission of electrons can be switched for each pixel. The applied voltage (high voltage and low voltage) may be arbitrarily set.
　ここで、図４において、中央（２行２列目）の画素トランジスタ１（画素）を選択する場合を考える。この場合、各画素トランジスタ１のドレイン電極層２１に電圧（２３Ｖ）を印加する。また、水平走査回路１１５および垂直走査回路１１６は、該当する行および列を選択して、中央の画素トランジスタ１のゲート電極１８および対応する列選択トランジスタ２のゲート電極１８に高電圧（２０Ｖ）が印加される（状態（Ｈ，Ｈ））。すると、中央の画素トランジスタ１および該当する列の列選択トランジスタ２に貫通電流が流れる。これにより、中央の画素トランジスタ１が選択されたこととなる。なお、このとき、中央の画素トランジスタ１のドレイン電極層２１近傍では、ホットエレクトロン注入が発生している。また、このとき、中央の画素トランジスタ１のソース電極層３１の電位は、ＧＮＤレベル（０Ｖ）である。 Here, consider a case where the pixel transistor 1 (pixel) at the center (2nd row, 2nd column) is selected in FIG. In this case, a voltage (23 V) is applied to the drain electrode layer 21 of each pixel transistor 1. The horizontal scanning circuit 115 and the vertical scanning circuit 116 select the corresponding row and column, and a high voltage (20 V) is applied to the gate electrode 18 of the center pixel transistor 1 and the corresponding gate electrode 18 of the column selection transistor 2. Applied (state (H, H)). Then, a through current flows through the center pixel transistor 1 and the column selection transistor 2 of the corresponding column. As a result, the center pixel transistor 1 is selected. At this time, hot electron injection occurs in the vicinity of the drain electrode layer 21 of the central pixel transistor 1. At this time, the potential of the source electrode layer 31 of the central pixel transistor 1 is at the GND level (0 V).
　このとき、例えば、左上（１行１列目）の画素トランジスタ１の状態を考えると、この画素トランジスタ１のゲート電極１８および該当する列の列選択トランジスタ２のゲート電極１８には、それぞれ低電圧（０Ｖ）が印加されている（状態（Ｌ，Ｌ））。この場合、貫通電流が流れないため、ホットエレクトロン注入は発生しないが、ソース電極層３１の電位は、高電圧レベル（２３Ｖ）である。 At this time, for example, when considering the state of the pixel transistor 1 in the upper left (first row, first column), a low voltage is applied to the gate electrode 18 of the pixel transistor 1 and the gate electrode 18 of the column selection transistor 2 of the corresponding column. (0V) is applied (state (L, L)). In this case, since no through current flows, hot electron injection does not occur, but the potential of the source electrode layer 31 is at a high voltage level (23 V).
　また、例えば、中央左（２行１列目）の画素トランジスタ１の状態を考えると、この画素トランジスタ１のゲート電極１８には、高電圧（２０Ｖ）が印加され、該当する列の列選択トランジスタ２のゲート電極１８には、低電圧（０Ｖ）が印加されている（状態（Ｈ，Ｌ））。この場合も、貫通電流が流れないため、ホットエレクトロン注入は発生しないが、ソース電極層３１の電位は、高電圧レベル（２３Ｖ）である。 Further, for example, considering the state of the pixel transistor 1 at the center left (2nd row and 1st column), a high voltage (20 V) is applied to the gate electrode 18 of this pixel transistor 1, and the column selection transistor of the corresponding column. A low voltage (0 V) is applied to the second gate electrode 18 (states (H, L)). Also in this case, since no through current flows, hot electron injection does not occur, but the potential of the source electrode layer 31 is at a high voltage level (23 V).
　なお、正確には、状態（Ｌ，Ｌ）、（Ｈ，Ｌ）の場合、ソース電極層３１の電位は、ピンチオフ電圧（－４Ｖ程度）分だけ下がった値（１９Ｖ程度）となる。 To be precise, in the states (L, L) and (H, L), the potential of the source electrode layer 31 is a value (about 19 V) lowered by the pinch-off voltage (about −4 V).
　なお、例えば、中央上（１行２列目）の画素トランジスタ１の状態を考えると、この画素トランジスタ１のゲート電極１８には、低電圧（０Ｖ）が印加され、該当する列の列選択トランジスタ２のゲート電極１８には、高電圧（２０Ｖ）が印加されている（状態（Ｌ，Ｈ））。この場合、貫通電流が流れないため、ホットエレクトロン注入は発生しない。また、このとき、中央上の画素トランジスタ１のソース電極層３１の電位は、ＧＮＤレベル（０Ｖ）である。 For example, when considering the state of the pixel transistor 1 in the upper center (1st row and 2nd column), a low voltage (0 V) is applied to the gate electrode 18 of this pixel transistor 1, and the column selection transistor in the corresponding column A high voltage (20 V) is applied to the second gate electrode 18 (state (L, H)). In this case, since no through current flows, hot electron injection does not occur. At this time, the potential of the source electrode layer 31 of the pixel transistor 1 on the center is at the GND level (0 V).
　以上のように、各画素トランジスタ１には、高いドレイン耐圧（ドレイン領域１３の高耐圧）が必要とされているだけでなく、ソース領域１４に高電圧がかかる状態（状態（Ｌ，Ｌ）および状態（Ｈ，Ｌ））にも対応することが要求されている。また、撮像装置１００では、撮像素子アレイ１１３の高画素化が求められるため、アクティブマトリクス駆動回路１１４も高集積化が要求される。そのため、画素トランジスタ１（列選択トランジスタ２）は、トランジスタ面積の小さい片側ＬＯＣＯＳオフセット型で構成されることが好ましい。 As described above, each pixel transistor 1 is required not only to have a high drain breakdown voltage (high breakdown voltage of the drain region 13) but also to a state in which a high voltage is applied to the source region 14 (states (L, L) and It is also required to cope with the state (H, L). Further, since the imaging device 100 is required to increase the number of pixels of the imaging element array 113, the active matrix driving circuit 114 is also required to be highly integrated. For this reason, the pixel transistor 1 (column selection transistor 2) is preferably configured as a one-sided LOCOS offset type having a small transistor area.
　以下、図５を参照して、トランジスタ面積の小さい片側ＬＯＣＯＳオフセット型で、ソース領域１４の耐圧性を向上させた画素トランジスタ１（半導体装置）について説明する。なお、列選択トランジスタ２は、画素トランジスタ１と同一構造であるため、以降その説明は省略する。 Hereinafter, with reference to FIG. 5, a pixel transistor 1 (semiconductor device) that is a one-sided LOCOS offset type having a small transistor area and improved the withstand voltage of the source region 14 will be described. Since the column selection transistor 2 has the same structure as the pixel transistor 1, the description thereof is omitted hereinafter.
　既に説明したように、画素トランジスタ１（半導体装置）は、図外のＮ型シリコン基板上に形成されたＰ型のＰ型埋め込み層１１および半導体層１２と、半導体層１２に形成された、Ｎ型のドレイン領域１３、Ｎ型のソース領域１４、ゲート酸化膜１５、ＬＯＣＯＳ酸化膜１６、ドリフト層１７およびゲート電極１８と、を備えている。 As already described, the pixel transistor 1 (semiconductor device) includes a P-type P-type buried layer 11 and a semiconductor layer 12 formed on an N-type silicon substrate (not shown), and an N-type formed on the semiconductor layer 12. A type drain region 13, an N type source region 14, a gate oxide film 15, a LOCOS oxide film 16, a drift layer 17 and a gate electrode 18 are provided.
　ドレイン領域１３は、Ｎ型のドレイン電極層２１と、ドレイン電極層２１を内包するＮ型のドレイン電界緩和層２２と、を有している。 The drain region 13 has an N-type drain electrode layer 21 and an N-type drain electric field relaxation layer 22 that encloses the drain electrode layer 21.
　ドレイン電界緩和層２２は、ドリフト層１７に隣接して形成されている。ドレイン電極層２１は、ドレイン電界緩和層２２内で、かつ、ＬＯＣＯＳ酸化膜１６の端部から０．４μｍ以上、０．７μｍ以下離間して形成されている。また、ドレイン電界緩和層２２の不純物濃度は、ドリフト層１７の不純物濃度よりも高く、かつ、ドレイン電極層２１の不純物濃度よりも低くなっている。このように、ドリフト層１７からドレイン電極層２１に至る不純物濃度の濃度勾配を緩やかにすることで、電界集中が緩和され、ドレイン領域１３の耐圧性が向上する。 The drain electric field relaxation layer 22 is formed adjacent to the drift layer 17. The drain electrode layer 21 is formed in the drain electric field relaxation layer 22 and at a distance of 0.4 μm or more and 0.7 μm or less from the end of the LOCOS oxide film 16. The impurity concentration of the drain electric field relaxation layer 22 is higher than the impurity concentration of the drift layer 17 and lower than the impurity concentration of the drain electrode layer 21. In this way, by making the concentration gradient of the impurity concentration from the drift layer 17 to the drain electrode layer 21 gentle, the electric field concentration is alleviated and the breakdown voltage of the drain region 13 is improved.
　なお、ドリフト層１７は、イオン種をシングルチャージのリン（Ｐ＋）として、加速電圧を６０ｋｅＶ、ドーズ量を１．５×１０１３ｉｏｎｓ／ｃｍ２～３．５×１０１３ｉｏｎｓ／ｃｍ２程度として形成されることが好ましい。また、ドレイン電界緩和層２２は、イオン種をダブルチャージのリン（Ｐ＋＋）として、加速電圧を８０～１５０ｋｅＶ、ドーズ量を０．７６×１０１３ｉｏｎｓ／ｃｍ２程度として形成されることが好ましい。また、ドレイン電極層２１は、イオン種をシングルチャージの砒素（Ａｓ＋）として、加速電圧を５０ｋｅＶ、ドーズ量を２．０×１０１５ｉｏｎｓ／ｃｍ２～４．０×１０１５ｉｏｎｓ／ｃｍ２程度として形成されることが好ましい。 The drift layer 17 has an ion species of single charge phosphorus (P +), an acceleration voltage of 60 keV, and a dose of about 1.5 × 10 13 ions / cm 2 to 3.5 × 10 13 ions / cm 2. Preferably it is formed. The drain electric field relaxation layer 22 is preferably formed with ion species of double-charged phosphorus (P ++), an acceleration voltage of 80 to 150 keV, and a dose of about 0.76 × 10 13 ions / cm 2 . In addition, the drain electrode layer 21 has an ion species of single-charged arsenic (As +), an acceleration voltage of 50 keV, and a dose of about 2.0 × 10 15 ions / cm 2 to 4.0 × 10 15 ions / cm 2. It is preferable to be formed as.
　ソース領域１４は、Ｎ型のソース電極層３１と、ソース電極層３１を内包するＮ型のソースオフセット層３２と、を有している。 The source region 14 includes an N-type source electrode layer 31 and an N-type source offset layer 32 that encloses the source electrode layer 31.
　ソースオフセット層３２は、ゲート酸化膜１５に隣接して形成されている。ソース電極層３１は、ソースオフセット層３２内で、かつ、ゲート酸化膜１５の端部から０．４μｍ以上、０．７μｍ以下離間して形成されている。また、ソースオフセット層３２の不純物濃度は、半導体層１２の不純物濃度よりも高く、ソース電極層３１の不純物濃度よりも低くなっている。このように、半導体層１２とソース電極層３１との間に、ソース電極層３１よりも低濃度の不純物領域となるソースオフセット層３２を形成することで、接合の両方向に空乏層が拡張される。これにより、片側ＬＯＣＯＳオフセット型ＭＯＳトランジスタの形態で面積を小さく維持しつつ、ソース領域１４（ソース電極層３１と半導体層１２との間）の耐圧性を向上させることができる。 The source offset layer 32 is formed adjacent to the gate oxide film 15. The source electrode layer 31 is formed in the source offset layer 32 and separated from the end of the gate oxide film 15 by 0.4 μm or more and 0.7 μm or less. The impurity concentration of the source offset layer 32 is higher than that of the semiconductor layer 12 and lower than that of the source electrode layer 31. As described above, by forming the source offset layer 32 that is an impurity region having a lower concentration than the source electrode layer 31 between the semiconductor layer 12 and the source electrode layer 31, the depletion layer is extended in both directions of the junction. . Thereby, the pressure resistance of the source region 14 (between the source electrode layer 31 and the semiconductor layer 12) can be improved while keeping the area small in the form of a one-side LOCOS offset MOS transistor.
　なお、半導体層１２は、イオン種をダブルチャージのホウ素（Ｂ＋＋）として、加速電圧を１５０ｋｅＶ、ドーズ量を０．１×１０１３ｉｏｎｓ／ｃｍ２～０．３×１０１３ｉｏｎｓ／ｃｍ２程度として形成されることが好ましい。また、ソースオフセット層３２は、イオン種をシングルチャージのリン（Ｐ＋）として、加速電圧を１００～１６０ｋｅｖ、ドーズ量を０．５×１０１３ｉｏｎｓ／ｃｍ２～１．５×１０１３ｉｏｎｓ／ｃｍ２程度として形成されることが好ましい。また、ソース電極層３１は、イオン種をシングルチャージの砒素（Ａｓ＋）として、加速電圧を５０ｋｅＶ、ドーズ量を２．０×１０１５ｉｏｎｓ／ｃｍ２～４．０×１０１５ｉｏｎｓ／ｃｍ２程度として形成されることが好ましい。 The semiconductor layer 12 has an ion species of double-charged boron (B ++), an acceleration voltage of 150 keV, and a dose of about 0.1 × 10 13 ions / cm 2 to 0.3 × 10 13 ions / cm 2. Preferably it is formed. The source offset layer 32 has an ion species of single-charge phosphorus (P +), an acceleration voltage of 100 to 160 kev, and a dose of 0.5 × 10 13 ions / cm 2 to 1.5 × 10 13 ions / cm. It is preferably formed as about 2 . Further, the source electrode layer 31 is made of single-charged arsenic (As +), the acceleration voltage is 50 keV, and the dose amount is about 2.0 × 10 15 ions / cm 2 to 4.0 × 10 15 ions / cm 2. It is preferable to be formed as.
　以上のような、片側ＬＯＣＯＳオフセット型で構成された画素トランジスタ１（列選択トランジスタ２）は、ドレイン領域１３およびソース領域１４に対してＬＯＣＯＳ酸化膜１６およびドリフト層１７をそれぞれ設ける両側ＬＯＣＯＳオフセット型ＭＯＳトランジスタと比較して、トランジスタ面積を小さくすることができる。本願出願人は、両側ＬＯＣＯＳオフセット型ＭＯＳトランジスタと略同様の駆動能力を有するように、片側ＬＯＣＯＳオフセット型の画素トランジスタ１（列選択トランジスタ２）を構成すると、トランジスタ面積を２２．５％縮小することができるという結果を確認している。具体的には、両側ＬＯＣＯＳオフセット型ＭＯＳトランジスタでは、幅（Ｗ）＝１２．５５μｍ、長さ（Ｌ）＝１１．６μｍ、面積１４５．５８μｍ２であるのに対し、本実施形態の画素トランジスタ１等（片側ＬＯＣＯＳオフセット型）では、Ｗ＝１２μｍ、Ｌ＝９．４μｍ、面積１１２．８μｍ２である。 The pixel transistor 1 (column selection transistor 2) configured as a one-side LOCOS offset type as described above is a both-side LOCOS offset type MOS in which the LOCOS oxide film 16 and the drift layer 17 are provided for the drain region 13 and the source region 14, respectively. Compared with a transistor, the transistor area can be reduced. The applicant of the present application reduces the transistor area by 22.5% when the one-side LOCOS offset type pixel transistor 1 (column selection transistor 2) is configured to have substantially the same driving capability as the double-sided LOCOS offset type MOS transistor. The result that can be done is confirmed. Specifically, in the both-side LOCOS offset type MOS transistor, the width (W) = 12.55 μm, the length (L) = 11.6 μm, and the area 145.58 μm 2 , whereas the pixel transistor 1 of the present embodiment. Etc. (one-sided LOCOS offset type) W = 12 μm, L = 9.4 μm, and area 112.8 μm 2 .
　次に、図６および図７を参照し、画素トランジスタ１の製造方法（工程）について説明する。図６および図７は、画素トランジスタ１の製造工程を表した工程断面図である。ここでは、例として、ソース電極層３１と半導体層１２との間の耐圧を２２Ｖ以上確保するための工程を示す。 Next, a manufacturing method (process) of the pixel transistor 1 will be described with reference to FIGS. 6 and 7 are process cross-sectional views showing the manufacturing process of the pixel transistor 1. Here, as an example, a process for ensuring a breakdown voltage of 22 V or more between the source electrode layer 31 and the semiconductor layer 12 is shown.
　まず、図６（ａ）に示すように、図外のＮ型シリコン基板上にＰ型埋め込み層１１、半導体層１２を順次形成する。半導体層１２は、３．０５μｍ以上の層厚にエピタキシャル成長させて形成されている。そして、半導体層１２上にパッド酸化膜４１を形成し、パッド酸化膜４１上にＬＯＣＯＳ分離用窒化膜４２を部分的に形成する。続いて、ＬＯＣＯＳ分離用窒化膜４２をマスクとして、ＬＯＣＯＳオフセット領域となる位置にリン（Ｐ）を注入し、ドリフト層１７を形成する。なお、ドリフト層１７のイオン注入条件は、イオン種をシングルチャージのリン（Ｐ＋）、加速電圧を６０ｋｅＶ、ドーズ量を２．３×１０１３ｉｏｎｓ／ｃｍ２として、７°傾斜の回転注入を行うように設定されている。 First, as shown in FIG. 6A, a P-type buried layer 11 and a semiconductor layer 12 are sequentially formed on an N-type silicon substrate (not shown). The semiconductor layer 12 is formed by epitaxial growth to a layer thickness of 3.05 μm or more. Then, a pad oxide film 41 is formed on the semiconductor layer 12, and a LOCOS isolation nitride film 42 is partially formed on the pad oxide film 41. Subsequently, using the LOCOS isolation nitride film 42 as a mask, phosphorus (P) is implanted at a position to be a LOCOS offset region to form the drift layer 17. The drift layer 17 is ion-implanted with a single charge of phosphorus (P +), an acceleration voltage of 60 keV, a dose of 2.3 × 10 13 ions / cm 2 and a 7 ° tilted rotational implantation. Is set to
　次の工程では、図６（ｂ）に示すように、ＬＯＣＯＳ分離用窒化膜４２をマスクとして、ＬＯＣＯＳ酸化膜１６（膜厚４００～６００ｎｍ）を成長させる。その後、ＬＯＣＯＳ分離用窒化膜４２を除去し、半導体層１２に対しイオン注入を行う。半導体層１２へのイオン注入条件は、イオン種をホウ素（Ｂ＋＋（２価））、加速電圧を１５０ｋｅＶ、ドーズ量を０．２３×１０１３ｉｏｎｓ／ｃｍ２として、７°傾斜の回転注入を行うように設定されている。 In the next step, as shown in FIG. 6B, the LOCOS oxide film 16 (film thickness 400 to 600 nm) is grown using the LOCOS isolation nitride film 42 as a mask. Thereafter, the LOCOS isolation nitride film 42 is removed, and ion implantation is performed on the semiconductor layer 12. The ion implantation conditions into the semiconductor layer 12 are as follows: the ion species is boron (B ++ (divalent)), the acceleration voltage is 150 keV, and the dose is 0.23 × 10 13 ions / cm 2. Is set to
　次の工程では、図６（ｃ）に示すように、半導体層１２上にゲート酸化膜１５を形成する。また、ゲート酸化膜１５およびＬＯＣＯＳ酸化膜１６の上には、ポリシリコンからなる第１ゲート電極膜１８ａが形成される。 In the next step, a gate oxide film 15 is formed on the semiconductor layer 12 as shown in FIG. A first gate electrode film 18a made of polysilicon is formed on the gate oxide film 15 and the LOCOS oxide film 16.
　次の工程では、図６（ｄ）に示すように、半導体層１２のドレイン領域１３となる位置にリン（Ｐ）を注入し、ドレイン電界緩和層２２を形成する。なお、ドレイン電界緩和層２２のイオン注入条件は、イオン種をダブルチャージのリン（Ｐ＋＋）、加速電圧を１５０ｋｅＶ、ドーズ量を０．７６×１０１３ｉｏｎｓ／ｃｍ２として、７°傾斜の回転注入を行うように設定されている。 In the next step, as shown in FIG. 6D, phosphorus (P) is implanted into a position to be the drain region 13 of the semiconductor layer 12 to form the drain electric field relaxation layer 22. The drain electric field relaxation layer 22 is ion-implanted under the condition that the ion species is double-charged phosphorus (P ++), the acceleration voltage is 150 keV, and the dose is 0.76 × 10 13 ions / cm 2. Is set to do.
　次の工程では、図７（ｅ）に示すように、ゲート酸化膜１５上には、ポリシリコンからなる第２ゲート電極膜１８ｂが形成される。その後、第１ゲート電極膜１８ａおよび第２ゲート電極膜１８ｂは、フォトエッチングによって、ドレイン領域１３（ドレイン電界緩和層２２）側のＬＯＣＯＳ酸化膜１６に跨った部分のみを残して除去される。不要な部分を除去し、ＬＯＣＯＳ酸化膜１６に跨って形成された第１ゲート電極膜１８ａおよび第２ゲート電極膜１８ｂが、ゲート電極１８となる。 In the next step, a second gate electrode film 18b made of polysilicon is formed on the gate oxide film 15, as shown in FIG. Thereafter, the first gate electrode film 18a and the second gate electrode film 18b are removed by photoetching, leaving only the portion straddling the LOCOS oxide film 16 on the drain region 13 (drain electric field relaxation layer 22) side. Unnecessary portions are removed, and the first gate electrode film 18 a and the second gate electrode film 18 b formed across the LOCOS oxide film 16 become the gate electrode 18.
　次の工程では、図７（ｆ）に示すように、半導体層１２のソース領域１４となる位置にイオンを注入し、ソースオフセット層３２を形成する。ソースオフセット層３２のイオン注入条件は、イオン種をリン（Ｐ＋（１価））、加速電圧を１００ｋｅＶ、ドーズ量を１．０Ｅ＋１３個／ｃｍ２として、７°傾斜の回転注入を行うように設定されている。 In the next step, as shown in FIG. 7F, ions are implanted into the semiconductor layer 12 at a position to be the source region 14 to form a source offset layer 32. The ion implantation conditions of the source offset layer 32 are set so that the ion implantation is phosphorus (P + (monovalent)), the acceleration voltage is 100 keV, the dose is 1.0E + 13 ions / cm 2 , and rotational implantation at 7 ° is performed. Has been.
　なお、後に形成するソース電極層３１のオフセット量（ソース電極層３１とゲート酸化膜１５との間隔）を大きくすることにより、ソース領域１４での耐圧性を向上させることができるため、半導体層１２とソースオフセット層３２との接合部分の曲率半径が大きくなるように、イオン注入の深さを深くする（加速電圧を大きくする）ことが好ましい。しかし、ゲート酸化膜１５の上からイオン注入を行っているため、ゲート電極１８の下側のゲート酸化膜１５直下にイオンが注入されない程度の加速電圧（本実施形態では１４０ｋｅＶ以下）に調整する。 Note that by increasing the offset amount (interval between the source electrode layer 31 and the gate oxide film 15) of the source electrode layer 31 to be formed later, the pressure resistance in the source region 14 can be improved. It is preferable to increase the depth of ion implantation (increase the acceleration voltage) so that the radius of curvature of the junction between the source offset layer 32 and the source offset layer 32 is increased. However, since ion implantation is performed from above the gate oxide film 15, the acceleration voltage is adjusted to such an extent that ions are not implanted directly below the gate oxide film 15 below the gate electrode 18 (140 keV or less in this embodiment).
　次の工程では、図７（ｇ）に示すように、ゲート電極１８の両端部にサイドウォール４３を形成し、ゲート電極１８の下側以外に位置するゲート酸化膜１５を除去（エッチング）する。ただし、本実施形態では同一ＷＦ上にＬＤＤ構造ＭＯＳを作成しているためサイドウォール４３が形成されているが、サイドウォール４３の形成は任意である。 In the next step, as shown in FIG. 7G, sidewalls 43 are formed at both ends of the gate electrode 18, and the gate oxide film 15 located on the other side than the lower side of the gate electrode 18 is removed (etched). However, in this embodiment, since the LDD structure MOS is formed on the same WF, the sidewall 43 is formed, but the formation of the sidewall 43 is optional.
　最後に、図７（ｈ）に示すように、ドレイン電界緩和層２２およびソースオフセット層３２にフォトレジスト（図示省略）でマスキングを行った後、イオンを注入し、ドレイン電極層２１およびソース電極層３１を形成する。ドレイン電極層２１は、ドレイン電界緩和層２２の中で、ＬＯＣＯＳ酸化膜１６の端部から０．５μｍ離れた位置に形成されている。一方、ソース電極層３１は、ソースオフセット層３２の中で、ゲート酸化膜１５の端部から０．５μｍ離れた位置に形成されている。ドレイン電極層２１およびソース電極層３１のイオン注入条件は、イオン種を砒素（Ａｓ＋（１価））、加速電圧を５０ｋｅＶ、ドーズ量を２．０×１０１５ｉｏｎｓ／ｃｍ２として、７°傾斜の回転注入を行うように設定されている。 Finally, as shown in FIG. 7 (h), the drain electric field relaxation layer 22 and the source offset layer 32 are masked with a photoresist (not shown), and then ions are implanted to form the drain electrode layer 21 and the source electrode layer. 31 is formed. The drain electrode layer 21 is formed in the drain electric field relaxation layer 22 at a position 0.5 μm away from the end of the LOCOS oxide film 16. On the other hand, the source electrode layer 31 is formed in the source offset layer 32 at a position 0.5 μm away from the end of the gate oxide film 15. The ion implantation conditions for the drain electrode layer 21 and the source electrode layer 31 are as follows: the ion species is arsenic (As + (monovalent)), the acceleration voltage is 50 keV, the dose is 2.0 × 10 15 ions / cm 2 , and the inclination is 7 °. It is set to perform rotary injection.
　上記の工程により、トランジスタ面積が小さく、ドレイン領域１３およびソース領域１４の耐圧性を向上させた画素トランジスタ１（列選択トランジスタ２）を製造することができる。 Through the above process, the pixel transistor 1 (column selection transistor 2) having a small transistor area and improved breakdown voltage of the drain region 13 and the source region 14 can be manufactured.
　次に、図８を参照して、ソース電極層３１のオフセット量と、ソース領域１４の耐圧性との関係を表した実証データについて説明する。
　この場合、ソースオフセット層３２の不純物濃度を１．３Ｅ＋１７個／ｃｍ３とし、接合深さを０．３μｍとして、オフセット量を変化させた。これをイオン注入条件に置き換えると、イオン種：Ｐ＋、加速電圧：１００ｋｅＶ、ドーズ量：１．０Ｅ＋１３個／ｃｍ２となる。 Next, with reference to FIG. 8, demonstration data representing the relationship between the offset amount of the source electrode layer 31 and the pressure resistance of the source region 14 will be described.
In this case, the offset amount was changed by setting the impurity concentration of the source offset layer 32 to 1.3E + 17 / cm 3 and the junction depth to 0.3 μm. When this is replaced with ion implantation conditions, the ion species is P +, the acceleration voltage is 100 keV, and the dose is 1.0E + 13 ions / cm 2 .
　図８の実証データに示すように、オフセット量が０．４μｍ未満の範囲では、耐圧性が低く、０．４μｍ以上になると耐圧性の向上が確認される。このため、オフセット量（ソース電極層３１とゲート酸化膜１５との間隔）は、０．４μｍ～０．７μｍに設定することにより、ソース領域１４での耐圧性向上を確実に担保することができるものと考えられる。これにより、耐圧２２Ｖ以上を達成可能となっている。このため、所望の耐圧が得られるように、オフセット量および不純物濃度を、それぞれ任意に選択して画素トランジスタ１（列選択トランジスタ２）を製造することができる。 As shown in the demonstration data in FIG. 8, the pressure resistance is low in the range where the offset amount is less than 0.4 μm, and the improvement in pressure resistance is confirmed when the offset amount is 0.4 μm or more. For this reason, by setting the offset amount (interval between the source electrode layer 31 and the gate oxide film 15) to 0.4 μm to 0.7 μm, it is possible to ensure the improvement of the pressure resistance in the source region 14. It is considered a thing. As a result, a breakdown voltage of 22 V or more can be achieved. Therefore, the pixel transistor 1 (column selection transistor 2) can be manufactured by arbitrarily selecting the offset amount and the impurity concentration so that a desired breakdown voltage can be obtained.
　しかし、トランジスタ面積の縮小と、ソース領域１４の耐圧性の向上と、を高い水準で両立させることを考慮すると、オフセット量を０．５μｍとして画素トランジスタ１（列選択トランジスタ２）を構成することが好ましい。 However, in consideration of reducing the transistor area and improving the breakdown voltage of the source region 14 at a high level, the pixel transistor 1 (column selection transistor 2) may be configured with an offset amount of 0.5 μm. preferable.
　以上のような、トランジスタ面積が小さく、ソース領域１４の耐圧性を向上させた複数の画素トランジスタ１（列選択トランジスタ２）をマトリクス状に配設することにより、高耐圧で集積度の高いアクティブマトリクス駆動回路１１４を構成することができる。これにより、高解像度の撮像装置１００を製造することができる。 As described above, a plurality of pixel transistors 1 (column selection transistors 2) having a small transistor area and improved withstand voltage characteristics of the source region 14 are arranged in a matrix, thereby providing an active matrix having a high withstand voltage and a high degree of integration. The drive circuit 114 can be configured. Thereby, the high-resolution imaging device 100 can be manufactured.
　なお、本発明は、上述した実施形態に何ら限定されるものではなく、その要旨を逸脱しない範囲において種々の形態で実施し得るものである。 The present invention is not limited to the embodiment described above, and can be implemented in various forms without departing from the scope of the invention.
　１：画素トランジスタ、２：列選択トランジスタ、１２：半導体層、１３：ドレイン領域、１４：ソース領域、１５：ゲート酸化膜、１６：ＬＯＣＯＳ酸化膜、１７：ドリフト層、１８：ゲート電極、２１：ドレイン電極層、２２：ドレイン電界緩和層、３１：ソース電極層、３２：ソースオフセット層、１００：撮像装置、１１４：アクティブマトリクス駆動回路、１１５：水平走査回路、１１６：垂直走査回路 1: pixel transistor, 2: column selection transistor, 12: semiconductor layer, 13: drain region, 14: source region, 15: gate oxide film, 16: LOCOS oxide film, 17: drift layer, 18: gate electrode, 21: Drain electrode layer, 22: Drain electric field relaxation layer, 31: Source electrode layer, 32: Source offset layer, 100: Imaging device, 114: Active matrix driving circuit, 115: Horizontal scanning circuit, 116: Vertical scanning circuit

Claims (6)

  1. 　半導体基板上に形成された第１導電型の半導体層と、
    　前記半導体層に形成された第２導電型のドレイン電極層を有するドレイン領域と、
    　前記半導体層に形成された第２導電型のソースオフセット層およびソース電極層を有するソース領域と、
    　前記ドレイン領域と前記ソース領域の間で前記半導体層の表面の活性領域に形成されたゲート酸化膜と、
    　前記ドレイン領域と前記ゲート酸化膜の間で前記半導体層の表面に形成されたＬＯＣＯＳ酸化膜と、
    　前記ゲート酸化膜上に前記ＬＯＣＯＳ酸化膜に跨って形成されたゲート電極と、を備え、
    　前記ソースオフセット層は、前記ゲート酸化膜に隣接して形成され、
    　前記ソースオフセット層の不純物濃度は、前記半導体層の不純物濃度よりも高く、かつ、前記ソース電極層の不純物濃度よりも低く、
    　前記ソース電極層は、前記ゲート酸化膜から離間して前記ソースオフセット層内に形成されていることを特徴とする半導体装置。     A first conductivity type semiconductor layer formed on a semiconductor substrate;
    A drain region having a drain electrode layer of a second conductivity type formed in the semiconductor layer;
    A source region having a source offset layer and a source electrode layer of a second conductivity type formed in the semiconductor layer;
    A gate oxide film formed in an active region of the surface of the semiconductor layer between the drain region and the source region;
    A LOCOS oxide film formed on the surface of the semiconductor layer between the drain region and the gate oxide film;
    A gate electrode formed over the LOCOS oxide film on the gate oxide film,
    The source offset layer is formed adjacent to the gate oxide layer;
    The impurity concentration of the source offset layer is higher than the impurity concentration of the semiconductor layer and lower than the impurity concentration of the source electrode layer,
    The semiconductor device according to claim 1, wherein the source electrode layer is formed in the source offset layer so as to be separated from the gate oxide film.
  2. 　前記ソース電極層は、前記ゲート酸化膜の端部から０．４μｍ以上、０．７μｍ以下離間して形成されていることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the source electrode layer is formed so as to be separated from an end portion of the gate oxide film by 0.4 μm or more and 0.7 μm or less.
  3. 　前記ソースオフセット層の不純物濃度は、１．４Ｅ＋１６個／ｃｍ３以上、１．３Ｅ＋１７個／ｃｍ３以下であることを特徴とする請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein the impurity concentration of the source offset layer is 1.4E + 16 / cm 3 or more and 1.3E + 17 / cm 3 or less.
  4. 　前記半導体層に対する前記ソースオフセット層の接合深さは、０．３μｍ以上、１．０μｍ以下であることを特徴とする請求項２に記載の半導体装置。 3. The semiconductor device according to claim 2, wherein a junction depth of the source offset layer with respect to the semiconductor layer is 0.3 μm or more and 1.0 μm or less.
  5. 　前記ドレイン電極層を内包する第２導電型のドレイン電界緩和層を有した前記ドレイン領域と、
    　前記ＬＯＣＯＳ酸化膜下に形成された第２導電型のドリフト層と、を更に備え、
    　前記ドレイン電界緩和層は、前記ドリフト層に隣接して形成され、
    　前記ドレイン電界緩和層の不純物濃度は、前記ドリフト層の不純物濃度よりも高く、かつ、前記ドレイン電極層の不純物濃度よりも低く、
    　前記ドレイン電極層は、前記ＬＯＣＯＳ酸化膜をマスクとしたセルフアラインで形成されていることを特徴とする請求項２に記載の半導体装置。     The drain region having a drain electric field relaxation layer of a second conductivity type enclosing the drain electrode layer;
    A drift layer of a second conductivity type formed under the LOCOS oxide film,
    The drain field relaxation layer is formed adjacent to the drift layer;
    The impurity concentration of the drain electric field relaxation layer is higher than the impurity concentration of the drift layer and lower than the impurity concentration of the drain electrode layer,
    The semiconductor device according to claim 2, wherein the drain electrode layer is formed by self-alignment using the LOCOS oxide film as a mask.
  6. 　請求項２に記載の半導体装置の複数をマトリクス状に配設した半導体アレイと、
    　前記半導体アレイを水平方向に走査してスイッチングする水平走査回路と、
    　前記半導体アレイを垂直方向に走査してスイッチングする垂直走査回路と、を備えていることを特徴とするアクティブマトリクス駆動回路。     A semiconductor array in which a plurality of the semiconductor devices according to claim 2 are arranged in a matrix;
    A horizontal scanning circuit that scans and switches the semiconductor array in a horizontal direction;
    An active matrix driving circuit comprising: a vertical scanning circuit that scans and switches the semiconductor array in a vertical direction.
PCT/JP2011/006324 2011-11-11 2011-11-11 Semiconductor device and active matrix drive circuit using same WO2013069070A1 (en)

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JP2000232224A (en) * 1999-02-10 2000-08-22 Matsushita Electronics Industry Corp Semiconductor device and manufacture thereof
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