WO2013063788A1 - 显示面板的像素结构及其制造方法 - Google Patents

显示面板的像素结构及其制造方法 Download PDF

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Publication number
WO2013063788A1
WO2013063788A1 PCT/CN2011/081773 CN2011081773W WO2013063788A1 WO 2013063788 A1 WO2013063788 A1 WO 2013063788A1 CN 2011081773 W CN2011081773 W CN 2011081773W WO 2013063788 A1 WO2013063788 A1 WO 2013063788A1
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Prior art keywords
electrode
gate
electrically connected
pixel
forming
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English (en)
French (fr)
Inventor
侯鸿龙
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/379,880 priority Critical patent/US8405086B1/en
Publication of WO2013063788A1 publication Critical patent/WO2013063788A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a pixel structure of a display panel and a method of fabricating the same.
  • Liquid crystal display (Liquid Crystal Display, LCD) has been widely used in a variety of electronic products, most of the liquid crystal display is a backlight type liquid crystal display, which is composed of a liquid crystal display panel and a backlight module (backlight Module).
  • a general liquid crystal display panel includes a color filter (CF) substrate and a thin film transistor (TFT). Matrix substrate. A plurality of color filters and a common electrode are disposed on the CF substrate.
  • the TFT matrix substrate is provided with a plurality of parallel scan lines, a plurality of parallel data lines, a plurality of thin film transistors and pixel electrodes, wherein the scan lines are perpendicular to the data lines, and two adjacent scan lines and two adjacent data
  • a pixel (Pixel) region can be defined between the lines.
  • the invention provides a pixel structure of a display panel and a manufacturing method thereof to solve the problem of signal delay.
  • a main object of the present invention is to provide a pixel structure of a display panel, which is formed on a substrate, and the pixel structure includes:
  • the first transistor includes a first gate electrode, a first source electrode, and a first drain electrode, wherein the first drain electrode is electrically connected to the pixel electrode, and the first source electrode is electrically connected to the data line ;as well as
  • the second transistor includes a second gate electrode, a second source electrode, and a second drain electrode, wherein the second source electrode is electrically connected to the first gate line, and the second drain electrode is electrically connected to the second gate electrode The first gate electrode of the first transistor, the second gate electrode is electrically connected to the second gate line.
  • the second gate line is parallel to the first gate line.
  • the second gate electrode is formed by a portion of the second gate line.
  • the second source electrode is extended by the first gate line.
  • the second gate line is parallel to the data line.
  • the second gate electrode is electrically connected to the second gate line through a first connection hole.
  • the second source electrode is electrically connected to the first gate line through a second connection hole.
  • the second drain electrode is electrically connected to the first gate electrode through the third via.
  • Another object of the present invention is to provide a method of fabricating a pixel structure, the method of manufacturing comprising the steps of:
  • first source electrode and a first drain electrode Forming a first source electrode and a first drain electrode on the semiconductor layer, wherein the first source electrode and the first drain electrode are located opposite to the first electrode, and a portion of the first electrode is a gate electrode;
  • the first electrode, the second electrode, and the first gate line are simultaneously formed on the substrate, and the second electrode is formed by the first gate The line extends.
  • first semiconductor layer and a second semiconductor layer Forming a first semiconductor layer and a second semiconductor layer on the gate insulating layer, wherein the first semiconductor layer is opposite to the first gate electrode, and the second semiconductor layer is opposite to the second gate electrode;
  • the first gate electrode, the second gate electrode, and the first gate line are simultaneously formed on the substrate.
  • the first source electrode, the second source electrode, the first drain electrode, the second drain electrode, and the second gate line are simultaneously formed, and the second gate The line is parallel to the data line.
  • the second gate electrode is electrically connected to the second gate line through a first connection hole
  • the second source electrode is electrically connected to the first electrode through a second connection hole
  • a gate line, the second drain electrode is electrically connected to the first gate electrode through the third connection hole.
  • the pixel structure of the display panel of the present invention and the manufacturing method thereof can ensure the correctness of the gate signal transmitted by the gate line, thereby improving the deformation problem caused by the delay of the signal waveform, and ensuring the correctness of the charging of the data line signal. Therefore, with the pixel structure of the display panel of the present invention, the pixel charging effect of the display panel can be improved.
  • FIG. 1 shows a cross-sectional view of a display panel and a backlight module in accordance with an embodiment of the present invention
  • FIG. 2 is an equivalent circuit diagram showing a pixel structure of a display panel in accordance with a first embodiment of the present invention
  • Figure 3 shows a schematic diagram of a pixel structure in accordance with a first embodiment of the present invention
  • Figure 4 is a cross-sectional view along line A-A of Figure 3 in accordance with the present invention.
  • Figure 5 is a waveform diagram showing a gate signal of a display panel in accordance with the present invention.
  • FIG. 6 is an equivalent circuit diagram showing a pixel structure of a display panel in accordance with a first embodiment of the present invention
  • Figure 7 shows a schematic diagram of a pixel structure in accordance with a first embodiment of the present invention
  • Figure 8 is a cross-sectional view taken along line B-B of Figure 7 in accordance with the present invention.
  • FIG. 1 shows a cross-sectional view of a display panel and a backlight module according to an embodiment of the invention.
  • the display panel 100 of the present invention may be, for example, a liquid crystal display (LCD) panel, an organic light emitting diode display (OLED). Panel, plasma display (PDP) or field emission display panel (Field Emission) Display) panel.
  • LCD liquid crystal display
  • OLED organic light emitting diode display
  • PDP plasma display
  • Field Emission Field Emission
  • FIG. 2 shows an equivalent circuit diagram of a pixel structure of a display panel according to a first embodiment of the present invention
  • FIG. 3 shows a schematic diagram of a pixel structure according to a first embodiment of the present invention
  • Figure 4 is a cross-sectional view along line AA of Figure 3 in accordance with the present invention.
  • the display panel 100 of the present embodiment includes a substrate 110, a plurality of pixels 120, a plurality of data lines 130, a plurality of first gate lines 140, and a plurality of second gate lines 150.
  • the data line 130 and the first gate line 140 are alternately arranged on the substrate 110.
  • the pixels 120 are arranged on the substrate 110 in a matrix form, and are located between the data line 130 and the first gate line 140, and second.
  • the gate lines 150 are arranged between the pixels 120, wherein the second gate lines 150 may be parallel to the data lines 130 or the first gate lines 140. In the first embodiment, the second gate line 150 is parallel to the first gate line 140.
  • the substrate 110 can be, for example, a glass substrate or a flexible plastic substrate.
  • the substrate 110 can be, for example, a thin film transistor (Thin Film).
  • the display panel 100 may further include a liquid crystal layer (not shown) and another substrate (not shown), such as a color filter, when the display panel 100 is a liquid crystal display panel.
  • Slice a filter, CF) substrate which is disposed relative to the substrate 110.
  • the liquid crystal layer is formed between the TFT matrix substrate (substrate 110) and the CF substrate, and the other substrate may be provided with a common electrode (not shown).
  • Vcom common voltage
  • each of the pixels 120 may include a pixel electrode 121, a first transistor 122, and a second transistor 123.
  • the pixel electrode 121 is preferably made of a light-transmitting conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), aluminum-doped zinc oxide (AZO), and gallium doping. Zinc oxide (GZO), zinc oxide (ZnO) or polyethylene dioxythiophene (PEDOT).
  • the first transistor 122 and the second transistor 123 are, for example, thin film transistors (TFTs) electrically connected to the data line 130, the first gate line 140, the second gate line 150, and the pixel electrode 121.
  • TFTs thin film transistors
  • the first transistor 122 includes a first gate electrode 124, a first source electrode 125, and a first drain electrode 126.
  • the first drain electrode 126 is electrically connected to the pixel electrode 121, and the first source electrode 125 is Electrically connected to the data line 130.
  • the second transistor 123 includes a second gate electrode 127, a second source electrode 128, and a second drain electrode 129.
  • the second source electrode 128 is electrically connected to the first gate line 140, and the second drain electrode 129 is electrically connected.
  • the second gate electrode 127 is electrically connected to the second gate line 150 .
  • the gate signal transmitted by the first gate line 140 can be corrected by the second transistor 123, and the modified gate The signal may be provided to the first transistor 122 through the second transistor 123. Therefore, when the data line 130 transmits the data signal to the pixel electrode 121 through the first transistor 122, the first transistor 122 can be turned on by the correct corrected gate signal, thereby ensuring the correctness of the signal charging of the data line 130. The delay of the gate signal is greatly improved.
  • FIG. 5 is a waveform diagram of a gate signal of a display panel according to the present invention.
  • the line segment 102 is a gate signal waveform of a display panel of the prior art, and the line segment 103 is modified by the display panel 100 of the present invention.
  • Gate signal waveform As shown in FIG. 5, the modified gate signal waveform of the line segment 103 can improve the signal deformation problem of the gate signal due to signal delay, compared to the deformation waveform of the line segment 102. Therefore, the pixel 120 of the display panel 100 of the present invention can improve the delay of the gate signal and ensure the correctness of the signal charging of the data line 130.
  • the first electrode 111 and the second electrode 112 are formed on the substrate 110, and the first electrode 111 and the second electrode 112 are provided between A gap.
  • the first electrode 111 and the second electrode 112 may be formed by a photolithography process, and the material thereof is, for example, Al, Ag, Cu, Mo, Cr, W, Ta, Ti, metal nitride or an alloy of any combination thereof, or A multilayer structure having a heat resistant metal film and a low resistivity film, such as a two-layer structure of a molybdenum nitride film and an aluminum film.
  • the electrodes 111, 112 and the first gate line 140 can be simultaneously formed on the substrate 110 by a photolithography process, and the second electrode 112 is extended by the first gate line 140.
  • a first gate insulating layer 113 is formed on the first electrode 111.
  • the material of the first gate insulating layer 113 is, for example, silicon nitride (SiNx) or silicon oxide (SiOx), which is, for example, plasma enhanced chemical vapor deposition (Plasma) Enhanced Chemical Vapor Deposition, PECVD) way to deposit formation.
  • a semiconductor layer 114 is formed on the first gate insulating layer 113 and the second electrode 112.
  • the material of the semiconductor layer 114 is, for example, N+ amorphous silicon (a-Si) heavily doped with an N-type impurity such as arsenic. Or its silicide is formed.
  • the first source electrode 125 and the first drain electrode 126 are formed on the semiconductor layer 114, wherein the first source electrode 125 and the first drain electrode 126 are located opposite to the first electrode 111, that is, the first The source electrode 125 and the first drain electrode 126 are located above the first electrode 111.
  • a portion of the first electrode 111 is the first gate electrode 124 , and the first source electrode 125 is electrically connected to the data line 130 . Therefore, the first transistor 122 can be obtained by the formation of a portion of the first electrode 111 (first gate electrode 124), the first gate insulating layer 113, the semiconductor layer 114, the first source electrode 125, and the first drain electrode 126.
  • the material of the first source electrode 125 and the first drain electrode 126 is, for example, Al, Ag, Cu, Mo, Cr, W, Ta, Ti, a metal nitride or an alloy of any combination thereof.
  • a second gate insulating layer 115 is formed on the semiconductor layer 114.
  • the second gate insulating layer 115 is opposite to the first electrode 111 located at the second electrode 112 and another portion.
  • the second gate insulating layer 115 is located above the first electrode 111 of the second electrode 112 and another portion.
  • a second gate electrode 127 is formed on the second gate insulating layer 115, wherein the second electrode 112 is the second source electrode 128, and the other portion of the first electrode 111 is the second drain electrode 129.
  • the second transistor 123 can be obtained by forming the (second source electrode 128) and the other portion of the first electrode 111 (second drain electrode 129).
  • the second gate electrode 127 is formed by a portion of the second gate line 150, and the material of the second gate electrode 127 may be, for example, Al, Ag, Cu, Mo, Cr, W, Ta, Ti, metal nitride or The alloy of any combination described above may be the same or different from the materials of the electrodes 111, 112.
  • a pixel electrode 116 is formed, wherein the pixel electrode 116 is electrically connected to the first drain electrode 126 of the first transistor 122.
  • the pixel electrode 116 can be formed on the protective layer 118.
  • the protective layer 118 can be formed on the source electrode 125 and the drain electrode 126.
  • the protective layer 118 may have at least one via hole (not shown) to expose a portion of the drain electrode 126.
  • the pixel electrode layer 116 may be over the via hole to electrically connect to the drain electrode 126. Therefore, the display panel of the embodiment is completed.
  • FIG. 6 is a schematic diagram showing an equivalent circuit diagram of a pixel structure of a display panel according to a second embodiment of the present invention
  • FIG. 7 is a schematic diagram showing a pixel structure according to a second embodiment of the present invention
  • Figure 8 is a cross-sectional view taken along line BB of Figure 7 in accordance with the present invention.
  • the pixel 220 of the second embodiment may include a pixel electrode 221, a first transistor 222, and a second transistor 223.
  • the first transistor 222 and the second transistor 223 are electrically connected to the data line 230 , the first gate line 240 , the second gate line 250 , and the pixel electrode 221 .
  • the first transistor 222 is for allowing the data line 230 to provide a data signal to the pixel electrode 221, and the second transistor 223 is for correcting the gate signal transmitted by the first gate line 240 and providing the corrected gate.
  • the signal is to the first transistor 222.
  • the second gate line 250 is parallel to the data line 230.
  • the first transistor 222 includes a first gate electrode 224 , a first source electrode 225 , and a first drain electrode 226 .
  • the first drain electrode 226 is electrically connected to the pixel electrode 221
  • the first source electrode 225 is Electrically connected to the data line 230.
  • the second transistor 223 includes a second gate electrode 227, a second source electrode 228, and a second drain electrode 229.
  • the second source electrode 228 is electrically connected to the first gate line 240, and the second drain electrode 229 is electrically connected.
  • the second gate electrode 227 is electrically connected to the second gate line 250.
  • first gate electrode 224 and a second gate electrode 227 are formed on the substrate 210, wherein the first gate electrode 224 and the second gate electrode are formed. There is a gap between 227.
  • the first gate electrode 224 and the second gate electrode 227 may be formed by a photolithography process, and the material thereof is, for example, Al, Ag, Cu, Mo, Cr, W, Ta, Ti, metal nitride or an alloy of any combination thereof, It may be a multilayer structure having a heat resistant metal film and a low resistivity film, such as a two-layer structure of a molybdenum nitride film and an aluminum film.
  • the gate electrodes 224, 227 and the first gate line 240 can be simultaneously formed on the substrate 210 by a photolithography process.
  • a gate insulating layer 213 is formed on the first gate electrode 224 and the second gate electrode 227, and the material of the gate insulating layer 213 is, for example, silicon nitride (SiNx) or silicon oxide (SiOx).
  • the first semiconductor layer 211 and the second semiconductor layer 212 are formed on the gate insulating layer 213, wherein the first semiconductor layer 211 is opposite to the first gate electrode 224, and the second semiconductor layer 212 is opposite to the second gate electrode 227. That is, the first semiconductor layer 211 is located on the first gate electrode 224, and the second semiconductor layer 212 is located on the second gate electrode 227.
  • the material of the semiconductor layers 211, 212 is, for example, formed of N+ amorphous silicon (a-Si) heavily doped with an N-type impurity such as arsenic or a silicide thereof.
  • the first source electrode 225 and the first drain electrode 226 are formed on the first semiconductor layer 211
  • the second source electrode 228 and the second drain electrode 229 are formed on the second semiconductor layer 212 . Therefore, through the formation of the first gate electrode 224, the gate insulating layer 213, the first semiconductor layer 211, the first source electrode 225, and the first drain electrode 226, the first transistor 222 can be obtained; through the second gate electrode 227, the gate
  • the second transistor 223 is obtained by forming the pole insulating layer 213, the second semiconductor layer 212, the second source electrode 228, and the second drain electrode 229.
  • the material of the source electrodes 225, 228 and the drain electrodes 226, 229 is, for example, Al, Ag, Cu, Mo, Cr, W, Ta, Ti, a metal nitride or an alloy of any combination thereof.
  • the source electrodes 225, 228, the drain electrodes 226, 229, and the second gate line 250 can be simultaneously formed by a photolithography process. Furthermore, in the second embodiment, the electrodes and signal lines located in different layers can pass through the contacts (contact Hole) to connect.
  • the second gate electrode 227 can be electrically connected to the second gate line 250 through the through hole 201.
  • the second source electrode 228 can be electrically connected to the first gate line 240 through the connection hole 202.
  • the second drain electrode 229 can be electrically connected to the first gate line 240. It is electrically connected to the first gate electrode 224 through the connection hole 203.
  • a pixel electrode 216 is formed, wherein the pixel electrode 216 is electrically connected to the first drain electrode 226 of the first transistor 222 .
  • the pixel electrode 216 can be formed on the protective layer 218.
  • the protective layer 218 can be formed on the source electrodes 225, 228 and the drain electrodes 226, 229.
  • the protective layer 218 may have at least one via hole (not shown) to expose a portion of the drain electrode 226.
  • the pixel electrode layer 216 may be overlying the via hole to electrically connect to the drain electrode 226, so that the display of the second embodiment is completed.
  • the pixel structure 220 of the panel is formed, wherein the pixel electrode 216 is electrically connected to the first drain electrode 226 of the first transistor 222 .
  • the pixel electrode 216 can be formed on the protective layer 218.
  • the protective layer 218 can be formed on the source electrodes 225, 228 and the drain electrodes 226, 229.
  • the protective layer 218 may have at least one via hole
  • the pixel structure of the display panel of the present invention and the manufacturing method thereof can correct the gate signal transmitted by the gate line by using the second transistor to improve the deformation problem caused by the delay of the signal waveform, and can ensure the data line.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
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Abstract

一种显示面板（100）的像素结构（120）及其制造方法。制造方法包括如下步骤：形成第一晶体管（122）及第二晶体管（123）于基板（110）上，其中第一晶体管（122）是连接于第二晶体管（123）与数据线（130）之间，第二晶体管（123）是连接于第一栅极线（140）与第二栅极线（150）；以及形成像素电极（121），其中像素电极（121）是连接于第一晶体管（122）。该显示面板（100）可改善信号波形因延迟而导致的变形问题。

Description

显示面板的像素结构及其制造方法 技术领域
本发明涉及一种显示技术领域，特别是涉及一种显示面板的像素结构及其制造方法。
 背景技术
液晶显示器(Liquid Crystal Display，LCD)已被广泛应用于各种电子产品中，液晶显示器大部分为背光型液晶显示器，其是由液晶显示面板及背光模块(backlight module)所组成。一般的液晶显示面板包含彩色滤光片(Color Filter，CF)基板及薄膜晶体管(Thin Film Transistor，TFT) 矩阵基板。CF基板上设有多个彩色滤光片和共同电极。TFT矩阵基板上设有多条彼此平行的扫描线、多条彼此平行的数据线、多个薄膜晶体管及像素电极，其中扫描线是垂直于数据线，且两相邻扫描线和两相邻数据线之间可界定像素(Pixel)区域。
然而，当显示面板的尺寸愈大时，容易造成显示面板上的扫描信号的延迟。因此，扫描信号波形容易变形，而严重影响数据线信号充电的正确性。
故，有必要提供一种显示面板的像素结构及其制造方法，以解决现有技术所存在的问题。
 技术问题
本发明提供一种显示面板的像素结构及其制造方法，以解决信号的延迟问题。
 技术解决方案
本发明的主要目的在于提供一种显示面板的像素结构，其形成于一基板上，所述像素结构包括：
像素电极；
第一晶体管，包括第一栅电极、第一源电极及第一漏电极，其中所述第一漏电极是电性连接于所述像素电极，所述第一源电极是电性连接于数据线；以及
第二晶体管，包括第二栅电极、第二源电极及第二漏电极，其中所述第二源电极是电性连接于第一栅极线，所述第二漏电极是电性连接于所述第一晶体管的所述第一栅电极，所述第二栅电极是电性连接于第二栅极线。
在本发明的一实施例中，所述第二栅极线是平行于所述第一栅极线。
在本发明的一实施例中，所述第二栅电极是由部分的所述第二栅极线所形成。
在本发明的一实施例中，所述第二源电极是由所述第一栅极线延伸出。
在本发明的一实施例中，所述第二栅极线是平行于所述数据线。
在本发明的一实施例中，所述第二栅电极通过第一接孔来电性连接于所述第二栅极线。
在本发明的一实施例中，所述第二源电极通过第二接孔来电性连接于所述第一栅极线。
在本发明的一实施例中，第二漏电极通过第三接孔来电性连接于第一栅电极。
本发明的另一目的在于提供一种像素结构的制造方法，所述制造方法包括如下步骤：
形成第一电极及第二电极于基板上；
形成第一栅极绝缘层于所述第一电极上；
形成半导体层于第一栅极绝缘层及所述第二电极上；
形成第一源电极及第一漏电极于所述半导体层上，其中所述第一源电极及所述第一漏电极是对位于所述第一电极，而部分所述第一电极是作为第一栅电极；
形成第二栅极绝缘层于所述半导体层上，其中所述第二栅极绝缘层是对位于所述第二电极及另一部分的所述第一电极；
形成第二栅电极于所述第二栅极绝缘层上，其中所述第二电极是作为第二源电极，所述另一部分的所述第一电极是作为第二漏电极；以及
形成像素电极，其中所述像素电极是电性连接于所述第一漏电极。
在本发明的一实施例中，所述第一电极、所述第二电极及所述第一栅极线是同时形成于所述基板上，所述第二电极是由所述第一栅极线延伸出。
本发明的又一目的在于提供一种像素结构的制造方法，所述制造方法包括如下步骤：
形成第一栅电极及第二栅电极于基板上；
形成栅极绝缘层于所述第一栅电极及所述第二栅电极上；
形成第一半导体层及第二半导体层于栅极绝缘层上，其中所述第一半导体层是对位于所述第一栅电极，所述第二半导体层是对位于所述第二栅电极；
形成第一源电极及第一漏电极于所述第一半导体层上；
形成第二源电极及第二漏电极于所述第二所述半导体层上，其中所述第二漏电极是通过接孔来电性连接于所述第一栅电极；以及
形成像素电极，其中所述像素电极是电性连接于所述第一漏电极。
在本发明的一实施例中，所述第一栅电极、所述第二栅电极及第一栅极线是同时形成于所述基板上。
在本发明的一实施例中，所述第一源电极、所述第二源电极、第一漏电极、所述第二漏电极及第二栅极线是同时形成，所述第二栅极线是平行于数据线。
在本发明的一实施例中，所述第二栅电极通过第一接孔来电性连接于所述第二栅极线，所述第二源电极通过第二接孔来电性连接于所述第一栅极线，第二漏电极通过第三接孔来电性连接于第一栅电极。
 有益效果
本发明的显示面板的像素结构及其制造方法可确保栅极线所传送的栅极信号的正确性，以改善信号波形因延迟而导致的变形问题，而可确保数据线信号充电的正确性。因此，通过本发明的显示面板的像素结构，可改善显示面板的像素充电效果。
 附图说明
图1显示依照本发明的实施例的显示面板与背光模块的剖面示意图；
图2显示依照本发明的第一实施例的显示面板的像素结构的等效电路图；
图3显示依照本发明的第一实施例的像素结构的示意图；
图4显示依照本发明图3沿A-A线的剖视图；
图5显示依照本发明的显示面板的栅极信号的波形图；
图6显示依照本发明的第一实施例的显示面板的像素结构的等效电路图；
图7显示依照本发明的第一实施例的像素结构的示意图；以及
图8显示依照本发明图7沿B-B线的剖视图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图1，其显示依照本发明的实施例的显示面板与背光模块的剖面示意图。本发明的显示面板100可为例如液晶显示(LCD)面板、有机发光二极管显示(OLED) 面板、等离子显示屏(PDP)或场致电子发射显示面板(Field Emission Display)面板。以LCD为例，当显示面板100例如为液晶显示面板时，显示面板100可组合背光模块101，而形成液晶显示装置。
请参照图2、图3及图4，图2显示依照本发明的第一实施例的显示面板的像素结构的等效电路图，图3显示依照本发明的第一实施例的像素结构的示意图，图4显示依照本发明图3沿A-A线的剖视图。本实施例的显示面板100包含基板110、多个像素120、多条数据线130、多条第一栅极线140及多条第二栅极线150。数据线130和第一栅极线140是相互交错地配置于基板110上，像素120是以矩阵形式来配置于基板110上，并位于数据线130和第一栅极线140之间，第二栅极线150是排列于像素120之间，其中第二栅极线150可平行于数据线130或第一栅极线140。在第一实施例中，第二栅极线150是平行于第一栅极线140。
如图2所示，基板110可例如为玻璃基板或可挠性塑料基板，在本实施例中，基板110可例如为薄膜晶体管(Thin Film Transistor，TFT)矩阵基板，当显示面板100例如为液晶显示面板时，显示面板100可更包含液晶层(未绘示)和另一基板(未绘示)，此另一基板例如为彩色滤光片(Color Filter，CF)基板，其相对于基板110设置，此时，液晶层是形成于TFT矩阵基板(基板110)和CF基板之间，此另一基板可设有公共电极(未绘示)，用以提供一公共电压(Vcom)。
如图2所示，每一像素120可包括像素电极121、第一晶体管122及第二晶体管123。像素电极121优选是以透光导电材料所制成，例如：氧化铟锡(ITO)、氧化铟锌(IZO)、氧化铟锡锌(ITZO)、铝掺杂氧化锌(AZO)、镓掺杂氧化锌(GZO)、氧化锌(ZnO)或聚乙撑二氧噻吩(PEDOT)。第一晶体管122及第二晶体管123例如为薄膜晶体管(TFT)，其电性连接于数据线130、第一栅极线140、第二栅极线150及像素电极121。第一晶体管122是用于允许数据线130提供数据信号至像素电极121，而第二晶体管123是用于修正由第一栅极线140所传来的栅极信号，并提供修正后的栅极信号至第一晶体管122。
如图2所示，第一晶体管122包括第一栅电极124、第一源电极125及第一漏电极126，其中第一漏电极126是电性连接于像素电极121，第一源电极125是电性连接于数据线130。第二晶体管123包括第二栅电极127、第二源电极128及第二漏电极129，其中第二源电极128是电性连接于第一栅极线140，第二漏电极129是电性连接于第一晶体管122的第一栅电极124，第二栅电极127是电性连接于第二栅极线150。
当本实施例的第一栅极线140传送栅极信号至第一晶体管122时，第一栅极线140所传送的栅极信号可通过第二晶体管123来进行修正，而修正后的栅极信号可通过第二晶体管123来提供至第一晶体管122。因此，当数据线130通过第一晶体管122来传送数据信号至像素电极121时，第一晶体管122可通过较正确的修正后栅极信号来开启，因而可确保数据线130信号充电的正确性，而大幅改善栅极信号的延迟问题。
请参照图5，其显示依照本发明的显示面板的栅极信号的波形图，线段102为现有技术的一显示面板的栅极信号波形，而线段103为本发明的显示面板100的修正后栅极信号波形。如图5所示，相较于线段102的变形波形，线段103的修正后栅极信号波形可改善栅极信号因信号延迟而导致的信号变形问题。因此，本发明的显示面板100的像素120可改善栅极信号的延迟问题，确保数据线130信号充电的正确性。
如图4所示，当制造本实施例的显示面板100的像素结构120时，首先，形成第一电极111及第二电极112于基板110上，第一电极111及第二电极112之间具有一间隙。第一电极111及第二电极112可通过光刻工艺来形成，其材料例如为Al、Ag、Cu、Mo、Cr、W、Ta、Ti、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构，例如氮化钼薄膜和铝薄膜的双层结构。在本实施例中，电极111、112及第一栅极线140可同时通过光刻工艺来形成于基板110上，第二电极112是由第一栅极线140延伸出。
如图4所示，接着，形成第一栅极绝缘层113于第一电极111上。第一栅极绝缘层113的材料例如为氮化硅(SiNx)或氧化硅(SiOx)，其例如是以等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition, PECVD)方式来沉积形成。接着，形成半导体层114于第一栅极绝缘层113及第二电极112上，半导体层114的材料例如是由重掺杂有N型杂质(例如砷)的N+非晶硅(a-Si)或其硅化物所形成。
如图4所示，接着，形成第一源电极125及第一漏电极126于半导体层114上，其中第一源电极125及第一漏电极126是对位于第一电极111，亦即第一源电极125及第一漏电极126是位于第一电极111的上方。其中，部分的第一电极111是作为第一栅电极124，第一源电极125是电性连接于数据线130。因此，通过部分的第一电极111(第一栅电极124)、第一栅极绝缘层113、半导体层114、第一源电极125及第一漏电极126的形成，可得到第一晶体管122。第一源电极125及第一漏电极126的材料例如Al、Ag、Cu、Mo、Cr、W、Ta、Ti、氮化金属或上述任意组合的合金。
如图4所示，接着，形成第二栅极绝缘层115于半导体层114上，其中此第二栅极绝缘层115是对位于第二电极112及另一部分的第一电极111，亦即第二栅极绝缘层115是位于第二电极112及另一部分的第一电极111的上方。接着，形成第二栅电极127于第二栅极绝缘层115上，其中第二电极112是作为第二源电极128，此另一部分的第一电极111是作为第二漏电极129。因此，通过第二栅电极127、第二栅极绝缘层115、半导体层114、第二电极112 (第二源电极128)及另一部分的第一电极111(第二漏电极129)的形成，可得到第二晶体管123。其中，第二栅电极127是由部分的第二栅极线150所形成，第二栅电极127的材料可例如为Al、Ag、Cu、Mo、Cr、W、Ta、Ti、氮化金属或上述任意组合的合金，并可相同或不同于电极111、112的材料。
如图4所示，接着，形成像素电极116，其中像素电极116是电性连接于第一晶体管122的第一漏电极126。且像素电极116可形成于保护层118上，此保护层118可形成于源电极125及漏电极126上。保护层118可具有至少一接孔(未显示)，以暴露出部分漏电极126，像素电极层116可覆盖于接孔上，以电性连接于漏电极126，故完成本实施例的显示面板100的像素结构120。
请参照图6、图7及图8，图6显示依照本发明的第二实施例的显示面板的像素结构的等效电路图，图7显示依照本发明的第二实施例的像素结构的示意图，图8显示依照本发明图7沿B-B线的剖视图。第二实施例的像素220可包括像素电极221、第一晶体管222及第二晶体管223。第一晶体管222及第二晶体管223电性连接于数据线230、第一栅极线240、第二栅极线250及像素电极221。第一晶体管222是用于允许数据线230提供数据信号至像素电极221，而第二晶体管223是用于修正由第一栅极线240所传来的栅极信号，并提供修正后的栅极信号至第一晶体管222。在第二实施例中，第二栅极线250是平行于数据线230。
如图8所示，第一晶体管222包括第一栅电极224、第一源电极225及第一漏电极226，其中第一漏电极226是电性连接于像素电极221，第一源电极225是电性连接于数据线230。第二晶体管223包括第二栅电极227、第二源电极228及第二漏电极229，其中第二源电极228是电性连接于第一栅极线240，第二漏电极229是电性连接于第一晶体管222的第一栅电极224，第二栅电极227是电性连接于第二栅极线250。
如图8所示，当制造本实施例的显示面板的像素结构220时，首先，形成第一栅电极224及第二栅电极227于基板210上，其中第一栅电极224及第二栅电极227之间具有一间隙。第一栅电极224及第二栅电极227可通过光刻工艺来形成，其材料例如为Al、Ag、Cu、Mo、Cr、W、Ta、Ti、氮化金属或上述任意组合的合金，亦可为具有耐热金属薄膜和低电阻率薄膜的多层结构，例如氮化钼薄膜和铝薄膜的双层结构。在本实施例中，栅电极224、227及第一栅极线240可同时通过光刻工艺来形成于基板210上。
如图8所示，接着，形成栅极绝缘层213于第一栅电极224及第二栅电极227上，栅极绝缘层213的材料例如为氮化硅(SiNx)或氧化硅(SiOx)。接着，形成第一半导体层211及第二半导体层212于栅极绝缘层213上，其中第一半导体层211是对位于第一栅电极224，第二半导体层212是对位于第二栅电极227，亦即第一半导体层211是位于第一栅电极224上，第二半导体层212是位于第二栅电极227上。半导体层211、212的材料例如是由重掺杂有N型杂质(例如砷)的N+非晶硅(a-Si)或其硅化物所形成。
如图8所示，接着，形成第一源电极225及第一漏电极226于第一半导体层211上，且形成第二源电极228及第二漏电极229于第二半导体层212上。因此，通过第一栅电极224、栅极绝缘层213、第一半导体层211、第一源电极225及第一漏电极226的形成，可得到第一晶体管222；通过第二栅电极227、栅极绝缘层213、第二半导体层212、第二源电极228及第二漏电极229的形成，可得到第二晶体管223。其中，源电极225、228及漏电极226、229的材料例如Al、Ag、Cu、Mo、Cr、W、Ta、Ti、氮化金属或上述任意组合的合金。
如图8所示，在第二实施例中，源电极225、228、漏电极226、229及第二栅极线250可同时通过光刻工艺来形成。再者，在第二实施例中，位于不同层的电极及信号线可通过接孔(contact hole)来连接。其中，第二栅电极227可通过接孔201来电性连接于第二栅极线250，第二源电极228可通过接孔202来电性连接于第一栅极线240，第二漏电极229可通过接孔203来电性连接于第一栅电极224。
如图8所示，接着，形成像素电极216，其中像素电极216是电性连接于第一晶体管222的第一漏电极226。且像素电极216可形成于保护层218上，此保护层218可形成于源电极225、228及漏电极226、229上。保护层218可具有至少一接孔(未显示)，以暴露出部分漏电极226，像素电极层216可覆盖于接孔上，以电性连接于漏电极226，故完成第二实施例的显示面板的像素结构220。
由上述可知，本发明的显示面板的像素结构及其制造方法可利用第二晶体管来修正栅极线所传送的栅极信号，以改善信号波形因延迟而导致的变形问题，而可确保数据线信号充电的正确性。因此，通过本发明的显示面板的像素结构，可改善显示面板的像素充电效果(充电率及均匀度)。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
工业实用性
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Claims (14)

  1. 一种显示面板的像素结构，其形成于一基板上，其中所述像素结构包括：
    像素电极；
    第一晶体管，包括第一栅电极、第一源电极及第一漏电极，其中所述第一漏电极是电性连接于所述像素电极，所述第一源电极是电性连接于数据线；以及
    第二晶体管，包括第二栅电极、第二源电极及第二漏电极，其中所述第二源电极是电性连接于第一栅极线，所述第二漏电极是电性连接于所述第一晶体管的所述第一栅电极，所述第二栅电极是电性连接于第二栅极线。
  2. 根据权利要求1所述的像素结构，其中所述第二栅极线是平行于所述第一栅极线。
  3. 根据权利要求2所述的像素结构，其中所述第二栅电极是由部分的所述第二栅极线所形成。
  4. 根据权利要求2所述的像素结构，其中所述第二源电极是由所述第一栅极线延伸出。
  5. 根据权利要求1所述的像素结构，其中所述第二栅极线是平行于所述数据线。
  6. 根据权利要求5所述的像素结构，其中所述第二栅电极通过第一接孔来电性连接于所述第二栅极线。
  7. 根据权利要求5所述的像素结构，其中所述第二源电极通过第二接孔来电性连接于所述第一栅极线。
  8. 根据权利要求5所述的像素结构，其中第二漏电极通过第三接孔来电性连接于第一栅电极。
  9. 一种像素结构的制造方法，包括如下步骤：
    形成第一电极及第二电极于基板上；
    形成第一栅极绝缘层于所述第一电极上；
    形成半导体层于所述第一栅极绝缘层及所述第二电极上；
    形成第一源电极及第一漏电极于所述半导体层上，其中所述第一源电极及所述第一漏电极是对位于所述第一电极，而部分所述第一电极是作为第一栅电极；
    形成第二栅极绝缘层于所述半导体层上，其中所述第二栅极绝缘层是对位于所述第二电极及另一部分的所述第一电极；
    形成第二栅电极于所述第二栅极绝缘层上，其中所述第二电极是作为第二源电极，所述另一部分的所述第一电极是作为第二漏电极；以及
    形成像素电极，其中所述像素电极是电性连接于所述第一漏电极。
  10. 根据权利要求9所述的制造方法，其中所述第一电极、所述第二电极及所述第一栅极线是同时形成于所述基板上，所述第二电极是由所述第一栅极线延伸出。
  11. 一种像素结构的制造方法，包括如下步骤：
    形成第一栅电极及第二栅电极于基板上；
    形成栅极绝缘层于所述第一栅电极及所述第二栅电极上；
    形成第一半导体层及第二半导体层于栅极绝缘层上，其中所述第一半导体层是对位于所述第一栅电极，所述第二半导体层是对位于所述第二栅电极；
    形成第一源电极及第一漏电极于所述第一半导体层上；
    形成第二源电极及第二漏电极于所述第二所述半导体层上，其中所述第二漏电极是通过接孔来电性连接于所述第一栅电极；以及
    形成像素电极，其中所述像素电极是电性连接于所述第一漏电极。
  12. 根据权利要求11所述的制造方法，其中所述第一栅电极、所述第二栅电极及第一栅极线是同时形成于所述基板上。
  13. 根据权利要求12所述的制造方法，其中所述第一源电极、所述第二源电极、第一漏电极、所述第二漏电极及第二栅极线是同时形成，所述第二栅极线是平行于数据线。
  14. 根据权利要求13所述的制造方法，其中所述第二栅电极通过第一接孔来电性连接于所述第二栅极线，所述第二源电极通过第二接孔来电性连接于所述第一栅极线，第二漏电极通过第三接孔来电性连接于第一栅电极。
PCT/CN2011/081773 2011-11-03 2011-11-04 显示面板的像素结构及其制造方法 Ceased WO2013063788A1 (zh)

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