WO2013059457A1 - Direct formation of graphene on semiconductor substrates - Google Patents
Direct formation of graphene on semiconductor substrates Download PDFInfo
- Publication number
- WO2013059457A1 WO2013059457A1 PCT/US2012/060810 US2012060810W WO2013059457A1 WO 2013059457 A1 WO2013059457 A1 WO 2013059457A1 US 2012060810 W US2012060810 W US 2012060810W WO 2013059457 A1 WO2013059457 A1 WO 2013059457A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal film
- semiconductor substrate
- layer
- carbon
- graphene
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/881—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being a two-dimensional material
- H10D62/882—Graphene
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02491—Conductive materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02494—Structure
- H01L21/02496—Layer structure
- H01L21/02502—Layer structure consisting of two layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02527—Carbon, e.g. diamond-like carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
- H01L21/02645—Seed materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y40/00—Manufacture or treatment of nanostructures
Definitions
- the field of the invention relates generally to a method for producing graphene and other atomically thick sheets on a semiconductor substrate.
- Graphene is the hexagonal arrangement of carbon atoms forming a one- atom thick planar sheet.
- Graphene is a promising electronic material. It has the potential to significantly impact the semiconductor industry due to its superior electrical, thermal, mechanical, and optical properties while at the same time offering compatibility with existing semiconductor processing techniques.
- Current processes require graphene to be transferred from a metal base to the desired substrate. This transfer process of an atomically-thick sheet is challenging and leads to low yield and a significant density of folds and tears.
- the transfer process generally uses a material like PMMA on graphene followed by dissolution of the metal foil, then graphene is bonded to the silicon dioxide layer, and finally the PMMA is removed leaving graphene on S1O2 on Silicon.
- the present invention is directed to a method of preparing a semiconductor substrate.
- the semiconductor substrate comprises two major, generally parallel surfaces, one of which is the front surface of the semiconductor substrate and the other of which is a back surface of the semiconductor substrate, and a
- the method comprises forming a metal film on the front surface of the semiconductor substrate, the metal film comprising a front metal film surface, a back metal film surface, and a bulk metal region between the front and back metal film surfaces, wherein the back metal film surface is in contact with the front semiconductor substrate surface.
- the method further comprises contacting the front metal film surface with a carbon-containing gas in a reducing atmosphere at a temperature sufficient to in-diffuse carbon atoms into the bulk metal region of the metal film.
- the method still further comprises precipitating carbon atoms to thereby form a layer of graphene between the front semiconductor substrate surface and the back metal film surface.
- the carbon atoms are precipitated into a layer or multi-layer of graphene by forming a temperature gradient profile in the semiconductor substrate having the metal film thereon, the temperature gradient profile being such that temperatures at the front metal film surface and the back metal film surface are less than a temperature near a central plane within the bulk metal region.
- the carbon atoms are precipitated into a layer or multi-layer of graphene by rapid cooling of the semiconductor substrate having the metal film thereon.
- the invention is further directed to a method of preparing a
- the semiconductor substrate comprising two major, generally parallel surfaces, one of which is the front surface of the semiconductor substrate and the other of which is a back surface of the semiconductor substrate, a circumferential edge joining the front and back semiconductor substrate surfaces, and a central plane between the front and back semiconductor substrate surfaces.
- the method comprises depositing a layer comprising a carbon-rich polymer on the front surface layer of the semiconductor substrate.
- the method further comprises forming a metal film on the carbon-rich polymer layer, the metal film comprising a front metal film surface, a back metal film surface, and a bulk metal region between the front and back metal film surfaces, wherein the back metal film surface is in contact with the layer comprising the carbon-rich polymer.
- the method still further comprises heating the semiconductor substrate comprising the layer comprising the carbon-rich polymer and the metal film thereon to a temperature sufficient to degrade the carbon-rich polymer layer in the presence of hydrogen.
- the method still further comprises precipitating carbon atoms to thereby form a layer of graphene between the front semiconductor substrate surface and the back metal film surface.
- the carbon atoms are precipitated into a layer or multi-layer of graphene between the front semiconductor substrate surface and the back metal film surface by forming a temperature gradient profile in the semiconductor substrate having the carbon-rich polymer layer and metal film thereon, the temperature gradient profile being such that temperatures at the front metal film surface and the back metal film surface are less than a temperature near a central plane within the bulk metal region.
- the carbon atoms are precipitated into a layer or multi-layer of graphene between the front semiconductor substrate surface and the back metal film surface by rapidly cooling the semiconductor substrate having the carbon- rich polymer layer and metal film thereon.
- the invention is still further directed to a multilayer article comprising a semiconductor substrate comprising two major, generally parallel surfaces, one of which is the front surface of the donor substrate and the other of which is a back surface of the donor substrate, a circumferential edge joining the front and back surfaces, and a central plane between the front and back surfaces; a layer of graphene in contact with the front surface of the semiconductor substrate; and a metal film in contact with the layer of graphene, the metal film comprising a front metal film surface, a back metal film surface, and a bulk metal region between the front and back metal film surfaces.
- the present invention is directed to a method for forming graphene directly on a semiconductor substrate, e.g., a semiconductor wafer.
- the method of the present invention enables coating at least a portion of a large diameter semiconductor wafer, e.g., a silicon wafer coated with silicon dioxide, with at least a layer of graphene.
- the method of the present invention enables coating at least a portion of a large diameter semiconductor wafer, e.g., a silicon wafer coated with silicon dioxide, with a single mono-atomic layer of graphene. Stated another way, at least a portion of the major surface of the wafer is coated with a single layer of graphene, the single layer having mono-atomic thickness.
- the method of the present invention enables coating at least a portion of a large diameter semiconductor wafer, e.g., a silicon wafer coated with silicon dioxide, with a bi-layer of graphene, each layer of the bi-layer comprising a layer of graphene of mono-atomic thickness.
- the method of the present invention enables coating at least a portion of a large diameter semiconductor wafer, e.g., a silicon wafer coated with silicon dioxide, with a multi-layer of graphene having three or more layers, each layer of the multi-layer comprising a layer of graphene of mono- atomic thickness.
- the entire major surface of the wafer may be coated with a layer or a multi-layer of graphene.
- a portion of the major surface of the wafer may be coated with a layer or a multi-layer of graphene.
- the method of the present invention relies on deposition of a metal film on the major surface of a semiconductor substrate and exposing the multilayer structure to a carbon source whereby carbon is absorbed into the metal film.
- the carbon source may be a hydrocarbon-containing self assembled monolayer or a carbon-rich polymer that is deposited on a surface of the semiconductor substrate prior to deposition of the metal film.
- the carbon source may be a combination of a hydrocarbon-containing self assembled monolayer and a carbon-rich polymer, both of which are deposited on a surface of the semiconductor substrate prior to deposition of the metal film.
- the carbon source may be a carbon-rich gas, e.g., methane, in which carbon is absorbed into the metal film during a vapor deposition process.
- a solid carbon source e.g., self-assembled monolayer and/or polymer, may be placed between the semiconductor substrate and the metal film, and the method further includes carbon absorption from a carbon-containing gas.
- the metal deposited on the major surface of the semiconductor substrate has a high carbon solubility at the temperature of carbon deposition, e.g., nickel.
- the carbon may be absorbed into the metal film from the solid or gaseous carbon source. When the multilayer structure is cooled, carbon segregates and precipitates from the metal film thereby depositing at least one layer of graphene between the semiconductor substrate and the metal film.
- the metal deposited on the major surface of the semiconductor substrate has a low or substantially zero carbon solubility at the temperature of carbon deposition.
- Such metals include, e.g., copper.
- elevated temperatures degrade the carbon source, e.g., a gaseous carbon or a carbon containing polymer, and the metal surface catalyzes the growth of at least one layer of graphene between the semiconductor substrate and the metal film.
- the metal layer may be deposited over the entire major surface of the semiconductor substrate. In some embodiments, the metal layer may be deposited over a portion of the substrate, such as at least about 10% of the total area of the major surface, or at least about 25% of the total area, or at least about 50% of the total area, or at least about 75% of the total area. In some embodiments, the metal layer may be deposited over the entire major surface of the semiconductor substrate and thereafter metal may be removed, using conventional lithography techniques, to thereby leave a desired pattern of metal deposition on the major surface of the substrate.
- the metal film may be removed, e.g., by etching, thereby yielding a multilayer semiconductor structure comprising a semiconductor substrate and a mono- atomic layer of graphene.
- the graphene layer has the same dimensions as the metal layer deposited on the major surface of the semiconductor substrate.
- the method enables preparation of graphene layers having desired patterns, e.g., by lithography of the metal layer, on the major surface of the semiconductor substrate.
- the graphene is deposited without any layer transfer steps.
- the graphene layer or layers is/are deposited on a semiconductor substrate.
- a semiconductor substrate may comprise two major, generally parallel surfaces, one of which is a front surface of the substrate and the other of which is a back surface of the substrate.
- a circumferential edge joins the front and back surfaces, and a central plane lies between the front and back surfaces.
- the front surface and the back surface of the substrate may be substantially identical.
- a surface is referred to as a "front surface” or a "back surface” merely for convenience and generally to distinguish the surface upon which the operations of method of the present invention are performed.
- the operations of the invention are performed on the front surface of the semiconductor substrate.
- the operations of the present invention are performed on both the front surface and the back surface of the semiconductor substrate.
- the semiconductor substrate comprises a semiconductor wafer.
- the semiconductor wafer comprises a material selected from among silicon, silicon carbide, silicon germanium, silicon nitride, silicon dioxide, gallium arsenic, gallium nitride, indium phosphide, indium gallium arsenide, and germanium.
- the semiconductor wafer may comprise
- the semiconductor wafer has a diameter of at least about 20 mm, more typically between about 20 mm and about 500 mm. In some embodiments, the diameter is about 20 mm, about 45 mm, about 90 mm, about 100 mm, about 150 mm, about 200 mm, about 300 mm or even about 450 mm.
- the semiconductor wafer may have a thickness between about 100 micrometers and about 5000 micrometers, such as between about 100 micrometers and about 1500 micrometers.
- the semiconductor wafer comprises a wafer sliced from a single crystal silicon wafer which has been sliced from a single crystal ingot grown in accordance with conventional Czochralski crystal growing methods. Such methods, as well as standard silicon slicing, lapping, etching, and polishing techniques are disclosed, for example, in F. Shimura, Semiconductor Silicon Crystal Technology, Academic Press, 1989, and Silicon Chemical Etching, (J. Grabmaier ed.) Springer-Verlag, N.Y., 1982 (incorporated herein by reference).
- the semiconductor silicon substrate is a polished silicon wafer grown by the CZ method.
- the silicon substrate may have any crystal orientation, e.g., (100), (1 10), and (1 11).
- one or more of the major surfaces of the semiconductor substrate may be modified with a dielectric layer.
- the semiconductor substrate comprises a silicon wafer, the front surface layer of which is oxidized prior to ion implantation.
- the front surface layer i.e., the layer upon which the metal film is deposited, is oxidized.
- the front surface of the silicon wafer is preferably oxidized such that the front surface layer of the silicon wafer comprises a silicon dioxide (S1O 2 ) layer having a thickness between about 30 nm and about 1000 nm, between about 50 nm and about 500 nm, preferably between about 50 nm and about 300 nm, such as between about 90 nm and about 300 nanometers thick, or between about 90 nm and about 200 nanometers thick.
- the front surface of the silicon wafer may be thermally oxidized via wet or dry oxidation, as is known in the art. Oxidation generally occurs at temperatures between about 800°C and about 1200°C using water vapor and/or oxygen.
- a self- assembled monolayer comprising a hydrocarbon-containing silane and/or a hydrocarbon-containing silicate (i.e., organosilane, organosilicates) may be deposited on the silicon oxide layer prior to forming the metal film.
- the hydrocarbon- containing moiety acts as a source of carbon, which will in-diffuse into the subsequently applied metal film during a heating cycle or degrade into graphene wherein the metal film comprises a metal having low or substantially zero carbon solubility.
- the hydrocarbon-containing silane and/or a hydrocarbon-containing silicate provide a carbon source for graphene formation on the front surface layer of the semiconductor substrate.
- the silane or silicate for forming the self- assembled monolayer has the structure:
- each X is independently a halide atom, an alkyl group, or an alkoxy group; and n is an integer between one and 25, preferably between about 3 and about 15.
- the alkyl group may comprise from 1 to 4 carbon atoms, such as methyl, ethyl, n-propyl, isopropyl, n-butyl, isobutyl, or tert-butyl.
- X is alkyl
- each X is methyl.
- the alkoxy group may comprise from 1 to 4 carbon atoms, such as methoxy, ethoxy, n-propoxy, isopropoxy, n-butoxy, isobutoxy, or tert-butoxy.
- X is alkoxy, preferably, each X is methoxy or each X is ethoxy.
- the halide atom may be, e.g., chloride or bromide.
- the semiconductor e.g., silica
- the semiconductor e.g., silica
- oxygen plasma suitable conditions include 100 W, 600 mTorr, 2 min.
- the oxygen plasma also introduces hydroxyl groups on silica surface.
- the substrate is then treated with the silane or silicate generally by immersion in a solution containing the silane or silicate.
- a suitable composition may be 1 wt.% in ethanol.
- the substrate may be immersed in this solution for 10 minutes. After deposition, the substrate is washed, for example, 3 times with 99% ethanol, followed by baking. Suitable baking conditions are 120°C for 4 minutes.
- Suitable hydrocarbon-containing materials that may be used to form self-assembled monolayers include hexamethyldisilazane and aluminum alkyls. Aluminum alkyls are less preferred since the aluminum may dope the graphene product.
- a carbon- rich polymer is deposited on the semiconductor substrate, e.g., a semiconductor wafer having a dielectric layer thereon, prior to forming the metal film.
- the carbon-rich polymer is deposited on a metal layer that has been deposited on the major surface of the semiconductor wafer.
- a carbon-rich polymer is deposited on the semiconductor substrate, e.g., a semiconductor wafer having a dielectric layer thereon, prior to forming the metal film, and a second carbon-rich polymer layer is deposited on the surface of the metal film.
- the carbon-rich polymer acts as the source of carbon, which will in-diffuse into the subsequently applied metal film during a heating cycle or degrade into graphene wherein the metal film comprises a metal having low or substantially zero carbon solubility.
- a wide variety of carbon-containing polymers are suitable.
- the carbon-rich polymer may be selected from the group consisting of polymethylmethacrylate (PMMA), polybutadiene, polystyrene, poly(acrylonitrile-co-butadiene-co-styrene) (ABS), polyethylene, polypropylene, poly(4'-vinylhexaphenylbenzene)s, and combinations thereof.
- PMMA polymethylmethacrylate
- ABS polystyrene
- ABS poly(acrylonitrile-co-butadiene-co-styrene)
- polyethylene polypropylene
- poly(4'-vinylhexaphenylbenzene)s and combinations thereof.
- the polymer or carbon-containing film may contain nitrogen or boron in order to produce nitrogen-doped or boron-doped graphene sheets.
- Nitrogen-containing polymers suitable for the present invention include melamine formaldehyde, polyacrylonitrile, poly(2,5 pyridine), polypyrrole, polycarbazole, polyaniline, and combinations thereof. Boron doping may be achieved by preparing a carbon-containing layer comprising boron alcohols (non-polymeric) or by depositing BoramerTM.
- the carbon-rich polymer may be deposited by spin coating the substrate with a polymer film from a polymer-containing solution.
- suitable deposition methods include spray coating and electrochemical deposition.
- Suitable solvents for the spin-coating solution include toluene, hexane, xylene, pentane, cyclohexane, benzene, chloroform.
- the polymer concentration is generally between about 0.01 wt.% and about 1 wt.%, between about 0.05 wt.% and about 0.5 wt.%, such as about 0.1 wt.%.
- the carbon-rich polymer layer may be deposited to a thickness between about 1 nanometer and about 100 nanometers thick, such as between about 5 nanometer and about 100 nanometers thick, preferably between about 10 nanometers and about 50 nanometers thick. In some embodiments, the carbon-rich polymer layer may be deposited to a thickness between about 1 nanometer and about 10 nanometers.
- the major surface of the semiconductor substrate is coated with a metal film.
- the metal layer may be deposited over the entire major surface of the semiconductor substrate.
- the metal layer may be deposited over a portion of the substrate, such as at least about 10% of the total area of the major surface, or at least about 25% of the total area, or at least about 50% of the total area, or at least about 75% of the total area.
- the metal layer may be deposited over the entire major surface of the semiconductor substrate and thereafter metal may be removed selectively, using conventional lithography techniques, to thereby leave a desired pattern of metal deposition on the major surface of the substrate.
- the front surface layer of the semiconductor substrate is coated with a metal film. The front surface layer may be completely coated with metal, partially coated with metal, or coated with a metal pattern by lithography. In some
- the semiconductor substrate comprises a semiconductor wafer having a dielectric layer thereon.
- the semiconductor substrate comprises a silicon wafer having a silicon dioxide front surface layer, and the metal film is deposited onto the silicon dioxide front surface layer.
- the silicon dioxide layer may be completely coated with metal, partially coated with metal, or coated with a metal pattern by lithography.
- the semiconductor substrate comprises a silicon wafer having a silicon dioxide front surface layer, which is further modified with a hydrocarbon-containing self-assembled monolayer, e.g., a hydrocarbon-containing silane self-assembled monolayer, or a carbon-rich polymer, and the metal film is deposited onto the self-assembled monolayer or the carbon-rich polymer.
- a multilayer structure comprising a semiconductor substrate, a dielectric layer, a carbon-containing layer comprising a hydrocarbon- containing silane self-assembled monolayer or a carbon-rich polymer, and a metal film.
- the surfaces of the metal film may be referred to as a "front metal film surface” and "a back metal film surface.”
- the back metal film surface is in contact with the front semiconductor substrate surface layer, which may comprise a dielectric layer and optionally a hydrocarbon-containing silane self- assembled monolayer or a carbon-rich polymer.
- a bulk metal region is between the front and back metal film surfaces.
- Metals suitable for the present invention include nickel, copper, iron, platinum, palladium, ruthenium, cobalt, and alloys thereof.
- the metal film comprises nickel.
- the metal film may be deposited by techniques known in the art, including sputtering, evaporation, electrolytic plating, and metal foil bonding.
- the metal film is deposited by sputtering or evaporation using, e.g., a Sputtering and Metal evaporation Unit.
- Electrolytic metal plating may occur according to the methods described by Supriya, L.; Claus, R. O. Solution-Based Assembly of Conductive Gold Film on Flexible Polymer Substrates: Langmuir 2004, 20, 8870-8876.
- the metal film is between about 50 nanometers and about 20 micrometers thick, such as between about 50 nanometers and about 10 micrometers thick, such as between about 50 nanometers and about 1000 nanometers, such as about 300 nanometers.
- the metal film may comprise metal that has relatively high solubility for carbon at elevated temperatures (i.e., generally greater than 500°C, or greater than 800°C, such as about 1000°C), which enables in-diffusion of carbon.
- the metal also has low or substantially zero carbon solubility at cooler temperatures to thereby enable carbon segregation and precipitation into graphene in a subsequent cooling step.
- High carbon solubility metal films at the temperature of carbon in-diffusion include nickel, iron, palladium, and cobalt.
- the metal film comprises metal having carbon solubility of at least about 0.05 atomic % at 1000°C, preferably at least about 0.10 atomic % at 1000°C, ever more preferably at least about 0.15 atomic % at 1000°C. In some embodiments, the metal film comprises metal having carbon solubility less than about 3 atomic % at 1000°C, preferably less than about 2 atomic % at 1000°C.
- the metal film comprises nickel, which has a carbon solubility of about 0.2 atomic % at 1000°C, which is the chamber temperature for carbon in-diffusion when nickel is the metal film.
- the metal film comprises iron, which has a carbon solubility of about 0.02 atomic % at 800°C, which is the chamber temperature for carbon in-diffusion when iron is the metal film.
- the metal film may comprise metal that has low or substantially zero carbon solubility even at elevated temperatures (i.e., generally greater than 500°C, or greater than 800°C, such as about 1000°C).
- Low carbon solubility metal films include copper, platinum, ruthenium, and cobalt.
- carbon solubility is virtually zero in copper at temperatures greater than 500°C, or greater than 800°C, such as about 1000°C.
- copper is selected as the metal for the metal film, the carbon containing gas or the carbon containing polymer is degraded by hydrogen on copper. Carbon-carbon bond formation into graphene is catalyzed by on the copper surface.
- the multilayer structure may be cleaned.
- the multilayer structure comprises the semiconductor substrate, optional surface dielectric layer, a polymer film (in those embodiments wherein a polymer film is deposited prior to deposition of the metal film), and metal film.
- the multilayer structure may be cleaned by heating the structure in a vacuum furnace in a reducing atmosphere.
- a chemical vapor deposition system may be used where only baking under high vacuum is performed.
- the reducing atmosphere comprises hydrogen gas or other reducing gas.
- An inert carrier gas may be used, such as argon or helium.
- the temperature during exposure to the reducing atmosphere is preferably between about 800°C and about 1200°C, such as about 1000°C.
- the pressure is preferably sub- atmospheric, such as less than about 100 Pa (less than 1 Torr), preferably less than about 1 Pa (less than 0.01 Torr), even more preferably less than about 0.1 Pa (less than 0.001 Torr), and even more preferably less than about 0.01 Pa (less than 0.0001 Torr).
- the cleaning anneal may adjust the grain size of the metal film, e.g., increase the grain size at elevated temperatures.
- the multilayer structure comprises the semiconductor substrate, optional surface dielectric layer, the polymer film, and the metal film comprising a metal that has high carbon solubility
- the multilayer structure undergoes a heating and cooling cycle to bring about carbon absorption via in-diffusion into the metal film during heating, followed by carbon segregation and precipitation as graphene during cooling.
- a layer or multi-layer of graphene is precipitated between the front semiconductor substrate surface and the back metal film surface.
- carbon atoms precipitate into a layer or multi-layer of graphene by optionally forming a temperature gradient profile in the semiconductor substrate having the metal film thereon.
- the temperature gradient profile is achieved by cooling the front and back surfaces of the multilayer substrate. Such cooling creates a temperature gradient in which the front metal film surface and the back metal film surface are less than the temperature near a central plane within the bulk metal region.
- carbon atoms precipitate into a layer or multi-layer of graphene by rapidly cooling the multilayer structure.
- the method of the present invention is useful for preparing a multilayer article comprising the semiconductor substrate, which is optionally modified with a dielectric layer on the front surface thereof, a layer of graphene in contact with the front surface of the semiconductor substrate; and a metal film in contact with the layer of graphene.
- the temperature during carbon in-diffusion may range from about 500°C to about 1000°C, such as from about 700°C to about 1000°C, such as from about 800°C for iron or about 1000°C for nickel.
- the cooling rate is preferably controlled to a rate of about 5°C/second to about 50°C/second, such as about 10°C/second to about 30°C/second, for example about 10°C/second or about 30°C/second.
- the pressure of the chamber may vary from about 0.1 Pascals (about 1 mTorr) to about 70 Pascals (about 500 mTorr).
- the atmosphere is preferably a reducing atmosphere, which may comprise between about 70% and about 99% hydrogen, preferably about 95% hydrogen, balance inert gas.
- the multilayer structure comprises the semiconductor substrate, optional surface dielectric layer, the carbon-rich polymer film, and the metal film comprising a metal that has low carbon solubility
- the multilayer structure undergoes a heating and cooling cycle to bring about degradation of the carbon-containing polymer at elevated temperature, the degraded carbon forming graphene catalyzed by the surface of the metal film.
- the temperature to bring about degradation of the carbon-containing polymer may range from about from about 500°C to about 1000°C, such as from 700°C to about 1000°C.
- the multilayer structure is cooled at a cooling rate such as between about 5°C/second to about 50°C/second, such as about 10°C/second to about 30°C/second, for example about 10°C/second or about 30°C/second.
- the pressure of the chamber may vary from about 0.1 Pascals (about 1 mTorr) to about 70 Pascals (about 500 mTorr).
- the atmosphere is preferably a reducing atmosphere, which may comprise between about 70% and about 99% hydrogen, preferably about 95% hydrogen, balance inert gas.
- the multilayer structure comprising the semiconductor substrate, optionally a dielectric layer, and the metal film may be exposed to a carbon-containing gas to thereby in- diffuse atomic carbon into the bulk region of the metal film.
- a carbon-containing gas flow may be added to the reducing gas flow.
- the carbon- containing gas may be selected from among volatile hydrocarbons, for example, methane, ethane, ethylene, acetylene, propane, propylene, propyne, butanes, butylenes, butynes, and the like.
- the carbon-containing gas e.g., methane
- the minimum temperature during carbon in-diffusion and absorption is generally at least about 500°C.
- the maximum temperature during carbon in-diffusion and absorption is generally no more than about 1 100°C.
- the temperature is preferably between about 700°C and about 1000°C.
- the pressure inside the reaction chamber during hydrogen gas/methane flow is between about 600 Pa (about 5 Torr) and about 8000 Pa (about 60 Torr), preferably between about 1300 Pa (about 10 Torr) and about 7000 Pa (about 50 Torr).
- the multilayer structure is cooled at a cooling rate such as between about 5°C/second to about 50°C/second, such as about 10°C/second to about 30°C/second, for example about 10°C/second or about
- the flow of gases is stopped and the multilayer is held at the temperature of in-diffusion for a sufficient duration to allow the carbon to distribute throughout the bulk region of the metal film.
- the proper duration for carbon in-diffusion to yield a product having the desired number of graphene layers may be determined by creating a calibration curve in which the number of layers of the segregated graphene in the final product is a function of the carbon in-diffusion duration.
- the calibration curve may be used to determine ideal carbon in-diffusion durations sufficient to yield a graphene layer or multiple graphene layers.
- the duration of equilibration after the flow of carbon-containing gas is stopped may range from about 5 seconds to about 3600 seconds, such as about 600 seconds to about 1800 seconds. In some embodiments, the duration of carbon in diffusion is very short, such as about 10 seconds. Thereafter, the multilayer structure is rapidly cooled, as described above.
- the method of the present invention advantageously yields a monolayer of graphene.
- graphene formation depends upon solubilization of carbon into the metal film followed by segregation and precipitation of graphene (e.g., Nickel)
- the method of the present invention requires control of the amount of carbon absorbed and precipitated to control the number of graphene layers produced. In either embodiment, conditions can be controlled so that at least a layer of graphene precipitates between the front surface of the semiconductor substrate and the back surface of the metal film.
- the method of the present invention enables deposition of a single mono-atomic layer of graphene between the front surface of the semiconductor substrate and the back surface of the metal film. In some embodiments, the method of the present invention enables deposition of a bi- layer of graphene between the front surface of the semiconductor substrate and the back surface of the metal film, each layer of the bi-layer comprising a layer of graphene of mono-atomic thickness. In some embodiments, the method of the present invention enables deposition of a multi-layer of graphene having three or more layers between the front surface of the semiconductor substrate and the back surface of the metal film, each layer of the mult-layer comprising a layer of graphene of mono-atomic thickness. A second layer, bi-layer, or multi-layer of graphene may precipitate at the front metal film surface. Current results to date have shown that nickel layers in particular are suitable for preparing multi-layer grapheme films.
- this exterior layer or layers of graphene may be removed.
- the exterior graphene layer or layers may be removed by etching, for example, wet etching, plasma etching, or oxidation in ozone/UV light.
- the exterior layer or layers of graphene may be removed by oxygen plasma etching.
- the metal film is removed to thereby expose the graphene layer in contact with the front surface of the semiconductor substrate.
- the metal film may be removed by techniques known in the art adequate to dissolve the metal of the metal film, e.g., dissolution of nickel, copper, iron, or alloys thereof.
- the metal film is contacted with an aqueous metal etchant.
- Metal etchants useful for removing the metal film include ferric chloride, iron (III) nitrate, aqua-regia, and nitric acid.
- these metal etchants will not remove graphene.
- a multilayer substrate comprising a semiconductor substrate and a single layer of graphene of mono-atomic thickness.
- the graphene layer may be characterized to confirm the number of layers by techniques known in the art, for example, Raman spectroscopy.
- a multilayer substrate comprising a semiconductor substrate and a bi-layer of graphene, each layer of the bi-layer of mono-atomic thickness.
- graphene on an oxidized silicon wafer opens up many potential applications, including single molecule detection, ultrafast FETs, hydrogen visualization-template for TEM, and tunable spintronic devices. Furthermore, graphene exhibits high thermal conductivity (25 X silicon), high mechanical strength (strongest nanomaterial), high optical transparency (97%), carrier controlled interband/optical- transition and flexible structure. Graphene's high density of ⁇ -electrons from the sp 2 carbon atoms and carrier-confinement in an open crystallographic structure imparts it with the highest mobility measured to date.
- graphene exhibits several superior and atypical properties, including weakly-scattered ( scat t e ring > 300 nm), ballistic transport of its charge carriers at room temperature; gate-tunable band gap in bilayers; quantum Hall effect at room temperature; quantum interference; magneto-sensitive-transport; tunable optical transmitions; megahertz characteristic frequency; and a chemically and geometrically controllable band gap.
- Other applications include bio-electronic-devices, tunable spintronics, ultra-capacitors, and nano-mechanical devices. It is anticipated that the direct graphene formation on oxidized silicon will provide a unique graphene- structure on silicon-based platform for a wide variety of electronic and sensing applications.
- An approximately 5 centimeter (two inch) diameter silicon dioxide layer having a thickness of 90 nanometers was formed on an n-type silicon substrate.
- the substrate was cleaned by using oxygen plasma (100 W, 600 mTorr, 2 min).
- a layer of PMMA was spin-coated (1% in acetone, 4000 rpm (as an example)) on the silica substrate.
- a 500 nm thick metal layer was deposited on the PMMA layer in a metal evaporator system.
- the metal layer comprised nickel.
- the metal layer comprised copper.
- the metal-on-PMMA-on- silica-on-silicon substrate was put inside a CVD chamber.
- the sample was baked at 1000°C for 30 min (as an example) to anneal the film. Finally, the temperature of the CVD was brought to 1000°C and hydrogen gas was inflown at a pressure of 100 mTorr for 30 min. Finally, the sample was rapidly cooled at 10°C/second to room
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Carbon And Carbon Compounds (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020147013105A KR101899629B1 (ko) | 2011-10-19 | 2012-10-18 | 반도체 기판 상에의 그래핀의 직접 형성 |
| JP2014537240A JP6291413B2 (ja) | 2011-10-19 | 2012-10-18 | 半導体基板上におけるグラフェンの直接形成方法 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161548899P | 2011-10-19 | 2011-10-19 | |
| US61/548,899 | 2011-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2013059457A1 true WO2013059457A1 (en) | 2013-04-25 |
Family
ID=47258065
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2012/060810 Ceased WO2013059457A1 (en) | 2011-10-19 | 2012-10-18 | Direct formation of graphene on semiconductor substrates |
Country Status (5)
| Country | Link |
|---|---|
| US (3) | US8884310B2 (enExample) |
| JP (2) | JP6291413B2 (enExample) |
| KR (1) | KR101899629B1 (enExample) |
| TW (1) | TWI544527B (enExample) |
| WO (1) | WO2013059457A1 (enExample) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103482622A (zh) * | 2013-09-18 | 2014-01-01 | 武汉理工大学 | 一种稳定性强且电导率高的单层石墨烯薄膜的制备方法 |
| JP2015183046A (ja) * | 2014-03-20 | 2015-10-22 | Jsr株式会社 | 膜形成用組成物、レジスト下層膜及びその形成方法並びにパターン形成方法 |
| JP2018050052A (ja) * | 2013-05-09 | 2018-03-29 | サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited | 基板上の窒化ホウ素およびグラフェンの直接および連続形成 |
| US10157338B2 (en) | 2016-05-04 | 2018-12-18 | International Business Machines Corporation | Graphene-based micro-scale identification system |
| WO2022146953A1 (en) * | 2020-12-30 | 2022-07-07 | Texas Instruments Incorporated | Thermally conductive wafer layer |
Families Citing this family (50)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8501531B2 (en) * | 2011-04-07 | 2013-08-06 | The United States Of America, As Represented By The Secretary Of The Navy | Method of forming graphene on a surface |
| US8884310B2 (en) * | 2011-10-19 | 2014-11-11 | Sunedison Semiconductor Limited (Uen201334164H) | Direct formation of graphene on semiconductor substrates |
| US9029228B2 (en) * | 2011-10-19 | 2015-05-12 | SunEdision Semiconductor Limited (UEN201334164H) | Direct and sequential formation of monolayers of boron nitride and graphene on substrates |
| TWI434949B (zh) * | 2012-03-14 | 2014-04-21 | Nat Univ Tsing Hua | 化學氣相沈積生成石墨烯之方法 |
| TWI526559B (zh) * | 2012-04-06 | 2016-03-21 | 中央研究院 | 藉由物理氣相沉積法在基板上成長碳薄膜或無機材料薄膜的方法 |
| TW201341310A (zh) * | 2012-04-12 | 2013-10-16 | Nat Univ Tsing Hua | 利用雷射誘發石墨烯之製備方法 |
| KR101427818B1 (ko) * | 2012-10-29 | 2014-08-08 | 한국과학기술연구원 | 열 증착을 이용한 유기나노필름 기반 탄소재료 및 그 제조방법 |
| KR101425376B1 (ko) | 2013-02-12 | 2014-08-01 | 한국과학기술연구원 | 고분자 기반의 대면적 탄소 나노그물 및 그 제조방법 |
| US20140272309A1 (en) * | 2013-03-15 | 2014-09-18 | Solan, LLC | Non-Planar Graphite Based Devices and Fabrication Methods |
| US9593019B2 (en) * | 2013-03-15 | 2017-03-14 | Guardian Industries Corp. | Methods for low-temperature graphene precipitation onto glass, and associated articles/devices |
| US10431354B2 (en) | 2013-03-15 | 2019-10-01 | Guardian Glass, LLC | Methods for direct production of graphene on dielectric substrates, and associated articles/devices |
| WO2015020610A1 (en) | 2013-08-05 | 2015-02-12 | National University Of Singapore | Method to transfer two dimensional film grown on metal-coated wafer to the wafer itself in a face-to-face manner |
| JP6241318B2 (ja) * | 2014-02-28 | 2017-12-06 | 富士通株式会社 | グラフェン膜の製造方法及び半導体装置の製造方法 |
| US9324804B2 (en) | 2014-03-21 | 2016-04-26 | Wisconsin Alumni Research Foundation | Graphene-on-semiconductor substrates for analog electronics |
| WO2015184473A1 (en) * | 2014-05-30 | 2015-12-03 | Advanced Green Innovations, LLC | Hybrid graphene materials and methods of fabrication |
| US9287359B1 (en) | 2014-09-15 | 2016-03-15 | Wisconsin Alumni Research Foundation | Oriented bottom-up growth of armchair graphene nanoribbons on germanium |
| ES2575711B2 (es) * | 2014-12-31 | 2016-11-03 | Universidade De Santiago De Compostela | Método para la obtención de láminas de grafeno |
| CN105990091B (zh) * | 2015-01-29 | 2019-01-01 | 中国科学院微电子研究所 | 石墨烯的生长方法 |
| US10145005B2 (en) | 2015-08-19 | 2018-12-04 | Guardian Glass, LLC | Techniques for low temperature direct graphene growth on glass |
| WO2017052572A1 (en) * | 2015-09-25 | 2017-03-30 | Intel Corporation | Graphene barrier for electrical interconnects |
| WO2017058928A1 (en) | 2015-10-01 | 2017-04-06 | Sunedison Semiconductor Limited | Epitaxial growth of defect-free, wafer-scale single-layer graphene on thin films of cobalt |
| US9679972B1 (en) * | 2016-04-20 | 2017-06-13 | Globalfoundries Inc. | Thin strain relaxed buffers with multilayer film stacks |
| US10658472B2 (en) | 2016-05-12 | 2020-05-19 | Globalwafers Co., Ltd. | Direct formation of hexagonal boron nitride on silicon based dielectrics |
| US9923142B2 (en) | 2016-05-31 | 2018-03-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Methods of graphene growth and related structures |
| US10903319B2 (en) | 2016-06-15 | 2021-01-26 | Nanomedical Diagnostics, Inc. | Patterning graphene with a hard mask coating |
| US11056343B2 (en) * | 2016-06-15 | 2021-07-06 | Cardea Bio, Inc. | Providing a temporary protective layer on a graphene sheet |
| US10759157B2 (en) | 2016-06-15 | 2020-09-01 | Nanomedical Diagnostics, Inc. | Systems and methods for transferring graphene |
| EP3472340B1 (en) | 2016-06-15 | 2023-08-16 | Eastman Chemical Company | Physical vapor deposited biosensor components |
| US9761669B1 (en) | 2016-07-18 | 2017-09-12 | Wisconsin Alumni Research Foundation | Seed-mediated growth of patterned graphene nanoribbon arrays |
| TWI586849B (zh) | 2016-08-04 | 2017-06-11 | 國立中興大學 | A method of reducing the graphene layer of the oxidized graphene layer on the surface of the substrate and the hole wall of the aspect ratio hole and the adjusting liquid used in the method |
| EP3512957B1 (en) | 2016-09-16 | 2022-03-09 | Eastman Chemical Company | Biosensor electrodes prepared by physical vapor deposition |
| JP7111698B2 (ja) | 2016-09-16 | 2022-08-02 | イーストマン ケミカル カンパニー | 物理蒸着によって製造されるバイオセンサー電極 |
| TWI642804B (zh) * | 2016-10-04 | 2018-12-01 | 長庚大學 | 一種具有石墨烯層之半導體結構及其製造方法 |
| CN110167876B (zh) | 2017-01-06 | 2022-08-30 | 国立研究开发法人科学技术振兴机构 | 六方晶氮化硼薄膜及其制造方法 |
| CN108396377B (zh) * | 2017-02-06 | 2020-05-15 | 中国科学院金属研究所 | 一种高质量单层多晶石墨烯薄膜的制备方法 |
| US20180254318A1 (en) * | 2017-03-02 | 2018-09-06 | William B Pohlman, III | Graphene based in-plane micro-supercapacitors |
| US20180308696A1 (en) * | 2017-04-25 | 2018-10-25 | Texas Instruments Incorporated | Low contact resistance graphene device integration |
| CN110770575A (zh) | 2017-06-22 | 2020-02-07 | 伊士曼化工公司 | 用于电化学传感器的物理气相沉积电极 |
| CN108133885A (zh) * | 2017-11-07 | 2018-06-08 | 宁波大学 | 一种制备石墨烯肖特基结的方法 |
| WO2019183044A1 (en) * | 2018-03-19 | 2019-09-26 | Nanotek Instruments, Inc. | Graphene-mediated metallization of polymer films |
| US10604844B2 (en) * | 2018-05-14 | 2020-03-31 | Purdue Research Foundation | Graphene production using plasma-enhanced chemical vapor deposition |
| CN110683532B (zh) * | 2018-07-04 | 2021-01-01 | 中国科学院宁波材料技术与工程研究所 | 一种提高cvd石墨烯薄膜耐蚀性的方法 |
| US11760636B2 (en) * | 2018-10-26 | 2023-09-19 | The University Of Tulsa | Vacuum-free, hydrogen-free catalytic synthesis of graphene from solid hydrocarbons |
| PL241895B1 (pl) * | 2019-09-23 | 2022-12-19 | Univ Jagiellonski | Sposób otrzymywania powierzchniowego kompozytu węglikowo- grafenowego o kontrolowanej morfologii powierzchni |
| CN110759334B (zh) * | 2019-12-06 | 2023-07-28 | 上海集成电路研发中心有限公司 | 一种石墨烯沟道结构及其制作方法 |
| MX2023009588A (es) * | 2021-02-17 | 2023-09-04 | Praxair Technology Inc | Paquete de suministro de fluido de acetileno, sistema que comprende el mismo y método para fabricar un dispositivo semiconductor usando el mismo. |
| GB2604377B (en) * | 2021-03-04 | 2024-02-21 | Paragraf Ltd | A method for manufacturing graphene |
| US11618681B2 (en) | 2021-06-28 | 2023-04-04 | Wisconsin Alumni Research Foundation | Graphene nanoribbons grown from aromatic molecular seeds |
| US20250022967A1 (en) * | 2023-07-11 | 2025-01-16 | Stmicroelectronics International N.V. | A method for graphene layer growth and simultaneous molybdenum silicide formation on a semiconductor device |
| KR102732548B1 (ko) * | 2023-07-12 | 2024-11-22 | 한국지질자원연구원 | 바이오매스를 줄 히팅 공정을 통해 그래핀을 제조하는 방법 및 이에 의해 제조된 그래핀 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100923304B1 (ko) * | 2007-10-29 | 2009-10-23 | 삼성전자주식회사 | 그라펜 시트 및 그의 제조방법 |
| KR101344493B1 (ko) * | 2007-12-17 | 2013-12-24 | 삼성전자주식회사 | 단결정 그라펜 시트 및 그의 제조방법 |
| CN102448879B (zh) * | 2009-06-16 | 2014-10-22 | 富士通株式会社 | 石墨结构体、电子部件及电子部件的制造方法 |
| KR101622304B1 (ko) * | 2009-08-05 | 2016-05-19 | 삼성전자주식회사 | 그라펜 기재 및 그의 제조방법 |
| US8158200B2 (en) | 2009-08-18 | 2012-04-17 | University Of North Texas | Methods of forming graphene/(multilayer) boron nitride for electronic device applications |
| US8187955B2 (en) | 2009-08-24 | 2012-05-29 | International Business Machines Corporation | Graphene growth on a carbon-containing semiconductor layer |
| KR101736462B1 (ko) * | 2009-09-21 | 2017-05-16 | 한화테크윈 주식회사 | 그래핀의 제조 방법 |
| US8808810B2 (en) * | 2009-12-15 | 2014-08-19 | Guardian Industries Corp. | Large area deposition of graphene on substrates, and products including the same |
| US9096437B2 (en) | 2010-03-08 | 2015-08-04 | William Marsh Rice University | Growth of graphene films from non-gaseous carbon sources |
| CN102064189A (zh) | 2010-12-06 | 2011-05-18 | 苏州纳维科技有限公司 | 金属-半导体电极结构及其制备方法 |
| US20140120270A1 (en) | 2011-04-25 | 2014-05-01 | James M. Tour | Direct growth of graphene films on non-catalyst surfaces |
| US8884310B2 (en) * | 2011-10-19 | 2014-11-11 | Sunedison Semiconductor Limited (Uen201334164H) | Direct formation of graphene on semiconductor substrates |
| KR20130043063A (ko) * | 2011-10-19 | 2013-04-29 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치 및 반도체 장치의 제작 방법 |
| US9029228B2 (en) * | 2011-10-19 | 2015-05-12 | SunEdision Semiconductor Limited (UEN201334164H) | Direct and sequential formation of monolayers of boron nitride and graphene on substrates |
| US9059219B2 (en) * | 2012-06-27 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing semiconductor device |
| US9029226B2 (en) * | 2013-03-13 | 2015-05-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for doping lightly-doped-drain (LDD) regions of finFET devices |
-
2012
- 2012-10-16 US US13/652,665 patent/US8884310B2/en active Active
- 2012-10-18 KR KR1020147013105A patent/KR101899629B1/ko active Active
- 2012-10-18 WO PCT/US2012/060810 patent/WO2013059457A1/en not_active Ceased
- 2012-10-18 JP JP2014537240A patent/JP6291413B2/ja active Active
- 2012-10-19 TW TW101138780A patent/TWI544527B/zh active
-
2014
- 2014-10-08 US US14/509,209 patent/US9343533B2/en active Active
-
2016
- 2016-04-19 US US15/132,666 patent/US20160233305A1/en not_active Abandoned
-
2017
- 2017-12-27 JP JP2017251320A patent/JP6615853B2/ja active Active
Non-Patent Citations (9)
| Title |
|---|
| "Silicon Chemical Etching", 1982, SPRINGER-VERLAG |
| A. K. GEIM; K.S. NOVOVSELOV: "The Rise of Graphene", NATURE MATERIALS, vol. 6, 2007, pages 183 - 191, XP002661854, DOI: doi:10.1038/nmat1849 |
| CHING-YUAN SU ET AL: "Direct formation of wafer scale graphene thin layers on insulating substrates by chemical vapor deposition", NANO LETTERS, ACS, US, vol. 11, no. 9, 14 September 2011 (2011-09-14), pages 3612 - 3616, XP002677569, ISSN: 1530-6984, Retrieved from the Internet <URL:http://pubs.acs.org/doi/abs/10.1021/nl201362n> [retrieved on 20110811], DOI: 10.1021/NL201362N * |
| F. SHIMURA: "Semiconductor Silicon Crystal Technology", 1989, ACADEMIC PRESS |
| P. FIRST; W. DEHEER ET AL.: "Epitaxial Graphenes on Silicon Carbide", MRS BULLETIN, vol. 35, 2010, pages 296 - 305 |
| S. BAE ET AL.: "Roll-to Roll Production of 30 inch Graphene Films for Transparent Electrodes", NATURE NANOTECHNOLOGY, vol. 5, 2010, pages 574 - 578, XP055157874, DOI: doi:10.1038/nnano.2010.132 |
| SUPRIYA, L.; CLAUS, R. O.: "Solution-Based Assembly of Conductive Gold Film on Flexible Polymer Substrates", LANGMUIR, vol. 20, 2004, pages 8870 - 8876 |
| X. LI ET AL.: "Synthesis, Characterization, and Properties of Large-Area Graphene Films", ECS TRANSACTIONS, vol. 19, no. 5, 2005, pages 41 - 52 |
| ZHIWEI PENG ET AL: "Direct growth of Bilayer graphene on SiO2 substrates by carbon diffusion through nickel", ACS NANO, AMERICAN CHEMICAL SOCIETY, UNITED STATES, vol. 5, no. 10, 1 January 2011 (2011-01-01), pages 8241 - 8247, XP002677568, ISSN: 1936-0851, Retrieved from the Internet <URL:http://pubs.acs.org/doi/abs/10.1021/nn202923y> [retrieved on 20110903], DOI: 10.1021/NN202923Y * |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018050052A (ja) * | 2013-05-09 | 2018-03-29 | サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited | 基板上の窒化ホウ素およびグラフェンの直接および連続形成 |
| JP2019125793A (ja) * | 2013-05-09 | 2019-07-25 | サンエディソン・セミコンダクター・リミテッドSunEdison Semiconductor Limited | 基板上の窒化ホウ素およびグラフェンの直接および連続形成 |
| CN103482622A (zh) * | 2013-09-18 | 2014-01-01 | 武汉理工大学 | 一种稳定性强且电导率高的单层石墨烯薄膜的制备方法 |
| JP2015183046A (ja) * | 2014-03-20 | 2015-10-22 | Jsr株式会社 | 膜形成用組成物、レジスト下層膜及びその形成方法並びにパターン形成方法 |
| US10157338B2 (en) | 2016-05-04 | 2018-12-18 | International Business Machines Corporation | Graphene-based micro-scale identification system |
| US10430700B1 (en) | 2016-05-04 | 2019-10-01 | International Business Machines Corporation | Graphene-based micro-scale identification system |
| WO2022146953A1 (en) * | 2020-12-30 | 2022-07-07 | Texas Instruments Incorporated | Thermally conductive wafer layer |
| US11854933B2 (en) | 2020-12-30 | 2023-12-26 | Texas Instruments Incorporated | Thermally conductive wafer layer |
Also Published As
| Publication number | Publication date |
|---|---|
| US20130099195A1 (en) | 2013-04-25 |
| KR20140082811A (ko) | 2014-07-02 |
| JP2018070445A (ja) | 2018-05-10 |
| US20160233305A1 (en) | 2016-08-11 |
| US9343533B2 (en) | 2016-05-17 |
| JP2015501277A (ja) | 2015-01-15 |
| US8884310B2 (en) | 2014-11-11 |
| JP6615853B2 (ja) | 2019-12-04 |
| US20150021554A1 (en) | 2015-01-22 |
| JP6291413B2 (ja) | 2018-03-14 |
| KR101899629B1 (ko) | 2018-09-17 |
| TWI544527B (zh) | 2016-08-01 |
| TW201320165A (zh) | 2013-05-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9343533B2 (en) | Direct formation of graphene on semiconductor substrates | |
| US9029228B2 (en) | Direct and sequential formation of monolayers of boron nitride and graphene on substrates | |
| KR102202991B1 (ko) | 기판 상의 질화붕소 및 그래핀의 단층의 직접적 및 순차적 형성 | |
| US9023220B2 (en) | Method of manufacturing a graphene monolayer on insulating substrates | |
| EP3356582B1 (en) | Epitaxial growth of defect-free, wafer-scale single-layer graphene on thin films of cobalt | |
| EP3455874A1 (en) | Direct formation of hexagonal boron nitride on silicon based dielectrics | |
| JP2015501277A5 (enExample) | ||
| KR20200040169A (ko) | 단결정 이종 2차원 물질의 애피택셜 성장 방법 및 적층 구조체 | |
| WO2013038622A1 (ja) | グラフェンの製造方法およびグラフェン | |
| NL2010216C2 (en) | Synthesizing and transferring at least one large layer of graphene. | |
| Barin et al. | Pre-Patterned CVD Graphene: Insights on ALD deposition parameters and their influence on Al2O3 and graphene layers | |
| Kambara | Super high rate deposition of homo-and hetero-epitaxial silicon thick films by meso-plasma CVD |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12791878 Country of ref document: EP Kind code of ref document: A1 |
|
| ENP | Entry into the national phase |
Ref document number: 2014537240 Country of ref document: JP Kind code of ref document: A |
|
| NENP | Non-entry into the national phase |
Ref country code: DE |
|
| ENP | Entry into the national phase |
Ref document number: 20147013105 Country of ref document: KR Kind code of ref document: A |
|
| 122 | Ep: pct application non-entry in european phase |
Ref document number: 12791878 Country of ref document: EP Kind code of ref document: A1 |