WO2013057920A1 - Élément de stockage non volatil et son procédé de fabrication - Google Patents

Élément de stockage non volatil et son procédé de fabrication Download PDF

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Publication number
WO2013057920A1
WO2013057920A1 PCT/JP2012/006601 JP2012006601W WO2013057920A1 WO 2013057920 A1 WO2013057920 A1 WO 2013057920A1 JP 2012006601 W JP2012006601 W JP 2012006601W WO 2013057920 A1 WO2013057920 A1 WO 2013057920A1
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WIPO (PCT)
Prior art keywords
layer
plug
nonvolatile memory
memory element
preventing layer
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PCT/JP2012/006601
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English (en)
Japanese (ja)
Inventor
敦史 姫野
英昭 村瀬
伊藤　理
三河　巧
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パナソニック株式会社
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Publication of WO2013057920A1 publication Critical patent/WO2013057920A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of switching materials, e.g. deposition of layers
    • H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to a variable resistance nonvolatile memory element having a variable resistance element whose resistance value changes by application of an electric pulse, and a method for manufacturing the variable resistance nonvolatile memory element.
  • the resistance change element refers to an element having a property that the resistance value reversibly changes by an electric signal (electric pulse) and can store information corresponding to the resistance value in a nonvolatile manner.
  • variable resistance nonvolatile memory a variable resistance layer is used.
  • an electric pulse for example, a voltage pulse
  • the resistance value of the variable resistance layer changes from the high resistance state to the low resistance state, or from the low resistance state to the high resistance state.
  • the variable resistance nonvolatile memory element stores information corresponding to the resistance value as data.
  • 1) the two values of the low resistance state and the high resistance state are clearly distinguished, 2) the low resistance state and the high resistance state are stably changed at high speed, and 3) these two values are nonvolatile. 4) It is necessary to adapt to copper damascene technology and to achieve miniaturization and high integration.
  • Patent Documents 1 and 2 disclose, as examples of nonvolatile memory elements equipped with variable resistance elements, electrical devices that are compatible with copper damascene technology and can be manufactured by a less complicated method. This electric device is configured by electrically connecting a punch-through diode and a programmable resistor in series.
  • FIG. 13 is a cross-sectional view showing a conventional variable resistance nonvolatile memory element described in Patent Document 1.
  • the nonvolatile memory element 50 shown in FIG. 13 is manufactured as follows. First, after the copper metallization layer 201 and the corresponding plug 202 are formed, the first stacked body 207 is formed on the plug 202.
  • the first stacked body 207 includes a barrier layer 208 (eg, tantalum (Ta)), a contact layer 209 (eg, gold germanium nickel (AuGeNi)), a semiconductor 210 (eg, n-type gallium arsenide (GaAs)),
  • the contact layer 211 and the barrier layer 212 are formed by depositing in this order. Thus, a punch-through diode is formed.
  • the second stacked body 213 is formed on the first stacked body 207.
  • the second stacked body 213 is formed by depositing a barrier layer 214, an electrode layer 215, a PMC (Programmable Metallization Cell) material 216, a contact layer 217, and a barrier layer 218 in this order by sputtering.
  • an intermetal dielectric layer (not shown) is deposited.
  • the surface of the intermetal dielectric layer is planarized by a dielectric film CMP (Chemical Mechanical Polishing). In this way, a programmable resistor is formed.
  • CMP Chemical Mechanical Polishing
  • an IMD (Inter Metal Dielectric) layer 203 is deposited, and a groove 204 is formed on the upper surface of the IMD layer 203 by etching. After the trench 204 is filled with the barrier layer 205 and copper, copper CMP is performed. In this way, a copper interconnect layer 206 is formed.
  • IMD Inter Metal Dielectric
  • the manufacturing process described above can be repeated multiple times. This allows the manufacture of electrical devices having multiple layers of individually accessible memory elements. That is, a three-dimensional array of memory elements can be configured.
  • the present inventor in a conventional nonvolatile memory element, a portion of the upper surface of the plug formed under the nonvolatile memory element that is not covered with the stack of nonvolatile memory elements is plug-formed. It was found that there was a problem in that it was oxidized or deteriorated by exposure to gas or plasma used in a later process. This problem causes a problem that the electrical characteristics of the plug are impaired.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a nonvolatile memory element that can maintain good electrical characteristics of a plug and a method for manufacturing the same.
  • a nonvolatile memory element includes a first wiring and a plug that is disposed over the first wiring and electrically connected to the first wiring. And a whole of the upper surface of the plug, covering the entire surface of the anti-altering layer, covering a part of the upper surface of the anti-altering layer, and electrically connected to the plug via the anti-altering layer. And a second wiring that is disposed on the stacked body and electrically connected to the stacked body, the resistance state of the stacked body reversibly changes based on an applied electrical signal.
  • the resistance change layer is included, the horizontal cross-sectional area of the lower surface of the alteration preventing layer is equal to the horizontal sectional area of the upper surface of the plug, and a part of the upper surface of the alteration preventing layer is not covered with the laminate.
  • the nonvolatile memory element of the present invention since the entire upper surface of the plug formed under the nonvolatile memory element is covered with the alteration preventing layer, the gas or plasma used in the plug forming process is used. Etc., the upper surface of the plug is not exposed. Therefore, oxidation or alteration on the upper surface of the plug can be prevented, and the electrical characteristics of the plug can be kept good. Thereby, in the nonvolatile memory element including the resistance change element, it is possible to provide a nonvolatile memory element having a device structure capable of obtaining good electrical characteristics and a method for manufacturing the nonvolatile memory element.
  • FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 2A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 2B is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 2C is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 3A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 3A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 3B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 4A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 4B is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 5A is a cross-sectional view showing the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 5B is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 1 of the present invention.
  • FIG. 6 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 2 of the present invention.
  • FIG. 7 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 3 of the present invention.
  • FIG. 8 is a cross-sectional view showing the configuration of the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 9A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 9B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 9A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 9B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embod
  • FIG. 9C is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 10A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 10B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 10C is a cross-sectional view for explaining the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 11A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 11B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 12A is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 12B is a cross-sectional view illustrating the method for manufacturing the nonvolatile memory element according to Embodiment 4 of the present invention.
  • FIG. 13 is a cross-sectional view showing a configuration of a conventional nonvolatile memory element.
  • FIG. 14 is an electron micrograph of a cross section of a nonvolatile memory element showing an example of a defect of a conventional nonvolatile memory element.
  • FIG. 14 is an electron micrograph of a cross section of a conventional nonvolatile memory element produced by the present inventors.
  • the resistance change element 302 is disposed on the lower layer plug 301
  • the upper layer plug 303 is disposed on the resistance change element 302.
  • the horizontal cross-sectional area of the upper surface of the lower layer plug 301 and the horizontal cross-sectional area of the lower surface of the variable resistance element 302 are substantially equal, and the central axis of the variable resistance element 302 is relative to the central axis of the lower layer plug 301.
  • the position is shifted in the horizontal direction (right direction in FIG. 14). Therefore, an exposed portion that is not covered with the resistance change element 302 is generated on the upper surface of the lower layer plug 301.
  • a defective area 304 occurs in a part of the lower layer plug 301.
  • the defect region 304 is formed by an active area (that is, a resistance change element) by insulating a side wall surface of the resistance change element 302 by a dry etching process and a resist ashing process in which the resistance change element 302 is processed into a dot shape. It is considered that this is caused by oxidation or alteration occurring in the exposed portion of the upper surface of the lower layer plug 301 when the step of reducing the effective area that affects the electrical characteristics of the lower layer plug 301 is performed. Note that the defect area 304 can be easily identified by the difference in contrast of the electron micrograph as shown in FIG.
  • the horizontal sectional area of the lower surface of the resistance change element was sufficiently larger than the horizontal sectional area of the upper surface of the lower layer plug. Therefore, even when the horizontal displacement between the multilayer body and the lower layer plug occurs, the entire upper surface of the lower layer plug is covered with the multilayer body. Therefore, it is difficult to think that a part of the upper surface of the lower layer plug exposed by the misalignment is exposed to an etching gas or plasma used for dry etching when processing the laminated body. There were no concerns about alteration.
  • the horizontal cross-sectional area of the resistance change element tends to be miniaturized in order to improve the integration degree of the memory element.
  • the horizontal cross-sectional area of the lower surface of the laminated body tends to be equal to or smaller than the horizontal cross-sectional area of the upper surface of the lower layer plug.
  • the occurrence of the defect area 304 as shown in FIG. 14 becomes a more serious problem. If a part of the lower layer plug is oxidized or deteriorated, an electrical characteristic failure such as an increase in resistance of the lower layer plug occurs, and as a result, a problem such as an unstable write voltage applied to the variable resistance element occurs. .
  • the present inventor has devised a nonvolatile memory element that can eliminate the above-described problems by adopting a structure including an alteration preventing layer.
  • a nonvolatile memory element includes a first wiring, a plug disposed over the first wiring and electrically connected to the first wiring, and the entire upper surface of the plug.
  • An anti-altering layer having electrical conductivity, a laminate covering a part of the upper surface of the anti-altering layer, and electrically connected to the plug via the anti-altering layer, and disposed on the laminate
  • a second wiring electrically connected to the laminate, the laminate including a resistance change layer whose resistance state reversibly changes based on an applied electric signal, and the alteration
  • the horizontal sectional area of the lower surface of the prevention layer is equal to the horizontal sectional area of the upper surface of the plug, and a part of the upper surface of the alteration preventing layer is not covered with the laminate.
  • the upper surface of the plug is not exposed to gas or plasma used in the process after the plug is formed. Therefore, oxidation or alteration on the upper surface of the plug can be prevented, and the electrical characteristics of the plug can be kept good. Further, even in the step of oxidizing the side wall surface of the stacked body in order to reduce the active area of the stacked body, it is possible to prevent oxidation or degeneration on the upper surface of the plug. By maintaining good electrical characteristics of the plug, the write voltage applied to the variable resistance layer can be stabilized.
  • the stacked body further includes a first electrode electrically connected to the plug through the alteration preventing layer, and an electrical connection to the second wiring.
  • the variable resistance layer may be configured to be disposed between the first electrode and the second electrode.
  • the laminate is configured by laminating the first electrode, the resistance change layer, and the second electrode in this order.
  • a resistance change element can be comprised by such a laminated body.
  • the horizontal cross-sectional area of the lower surface of the first electrode may be configured to be smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer.
  • the horizontal sectional area of the lower surface of the first electrode is smaller than the horizontal sectional area of the upper surface of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the first electrode.
  • the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
  • the horizontal cross-sectional area of the lower surface of the first electrode is equal to the horizontal cross-sectional area of the upper surface of the alteration preventing layer or the horizontal sectional area of the upper surface of the alteration preventing layer.
  • the center axis of the laminate is deviated from the center axis of the alteration preventing layer, and a part of the upper surface of the alteration preventing layer is not covered with the first electrode. Also good.
  • the central axis of the laminate is deviated from the central axis of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the first electrode. Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
  • the alteration preventing layer functions as a first electrode that is electrically connected to the plug, and the stacked body is further electrically connected to the second wiring.
  • the resistance change layer may be arranged between the alteration preventing layer as the first electrode and the second electrode.
  • the alteration preventing layer also functions as the first electrode, the number of steps can be reduced as compared with the case where the alteration preventing layer and the first electrode are formed of separate layers.
  • the horizontal cross-sectional area of the lower surface of the variable resistance layer may be configured to be smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer.
  • the horizontal cross-sectional area of the lower surface of the resistance change layer is smaller than the horizontal cross-sectional area of the upper surface of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the resistance change layer. The Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
  • the horizontal cross-sectional area of the lower surface of the resistance change layer is equal to the horizontal cross-sectional area of the upper surface of the alteration preventing layer or the horizontal sectional area of the upper surface of the alteration preventing layer.
  • the center axis of the laminate is deviated from the center axis of the alteration preventing layer, and a part of the upper surface of the alteration preventing layer is not covered with the resistance change layer. Also good.
  • the central axis of the laminate is deviated from the central axis of the alteration preventing layer, a part of the upper surface of the alteration preventing layer is exposed without being covered by the resistance change layer. Even in such a case, since the entire upper surface of the plug is covered with the alteration preventing layer, it is possible to prevent the upper surface of the plug from being exposed to a gas or plasma used in a process after the plug is formed. it can.
  • the nonvolatile memory element further includes an interlayer insulating layer disposed on the first wiring and having a contact hole.
  • the plug and the alteration preventing layer are both the contact hole. You may comprise so that it may be embedded in.
  • the plug and the alteration preventing layer are both embedded in the contact hole of the interlayer insulating layer, adjacent plugs are short-circuited when a plurality of nonvolatile memory elements are arranged at intervals. Can be surely prevented.
  • the alteration preventing layer may be configured to be composed of a metal nitride that forms the plug.
  • the alteration preventing layer can be easily formed on the upper surface of the plug by nitriding.
  • the nonvolatile memory element further includes an interlayer insulating layer disposed on the first wiring and having a contact hole.
  • the plug is embedded in the contact hole, and the alteration prevention is performed.
  • the layer may be configured to protrude outside the contact hole.
  • the plug is embedded in the contact hole of the interlayer insulating layer and the alteration preventing layer protrudes outside the contact hole, for example, when the upper surface of the alteration preventing layer is planarized, Loss that the upper surface is scraped can be suppressed.
  • the plug may be formed of tungsten or copper.
  • the plug can be made of tungsten or copper.
  • the alteration preventing layer may be configured to have an oxygen barrier property and an etching resistance.
  • the alteration preventing layer has an oxygen barrier property and etching resistance, it is possible to suppress the alteration preventing layer from being affected by the etching gas, for example, in an etching process after forming the plug.
  • the alteration preventing layer is formed of any one of tungsten nitride, cobalt-tungsten-phosphorus alloy, cobalt-tungsten-boron alloy, and palladium. It may be configured.
  • the alteration preventing layer is composed of any one of tungsten nitride, cobalt tungsten phosphorous alloy, cobalt tungsten tungsten boron alloy and palladium, the alteration preventing layer is affected by the etching gas. Can be effectively suppressed.
  • the resistance change layer may be configured of a transition metal oxide or an aluminum oxide.
  • variable resistance layer can be composed of a transition metal oxide or an aluminum oxide.
  • variable resistance layer includes at least one transition metal selected from oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, and oxygen-deficient zirconium oxide. You may comprise so that it may be comprised with the oxide.
  • the resistance change layer is composed of one or more transition metal oxides of oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, and oxygen-deficient zirconium oxide.
  • the variable resistance layer is made of an oxygen-deficient tantalum oxide
  • the nonvolatile memory element can be manufactured by a manufacturing process having a high affinity for a normal Si semiconductor process.
  • the resistance change layer includes a first resistance change layer including a first metal oxide, and a degree of oxygen deficiency higher than that of the first metal oxide. And a second variable resistance layer composed of a second metal oxide having a small thickness.
  • the resistance change layer is formed by stacking two types of metal oxides having different degrees of oxygen deficiency, so that the polarity of resistance change is always stable and the operation characteristics of the nonvolatile memory element are stabilized. be able to.
  • the method for manufacturing a nonvolatile memory element includes a step of forming a first wiring, and a plug electrically connected to the first wiring over the first wiring.
  • the alteration preventing layer is formed so as to cover the entire area of the upper surface of the plug, the upper surface of the plug is not exposed to gas or plasma used in the process after the plug is formed. Therefore, oxidation or alteration can be prevented from occurring on the upper surface of the plug, and a nonvolatile memory element having a plug with good electrical characteristics can be manufactured.
  • the step of forming the stacked body further includes forming a first electrode electrically connected to the plug through the alteration preventing layer. Including the steps of: forming the resistance change layer on the first electrode; forming the second electrode on the resistance change layer; and forming the second wiring, The second wiring electrically connected to the second electrode may be formed.
  • the laminate is formed by laminating the first electrode, the resistance change layer, and the second electrode in this order.
  • a resistance change element can be formed by such a laminated body.
  • the alteration preventing layer that functions as a first electrode electrically connected to the plug is formed.
  • the step of forming the laminated body includes a step of forming the resistance change layer on the alteration preventing layer and a step of forming a second electrode on the resistance change layer, and the second wiring is formed.
  • the second wiring electrically connected to the second electrode may be formed.
  • the manufacturing process of the nonvolatile memory element can be simplified as compared with the case where the alteration preventing layer and the first electrode are formed as separate layers.
  • the alteration preventing layer is formed by nitriding the entire upper surface of the plug. May be.
  • the alteration preventing layer can be easily formed on the upper surface of the plug by nitriding.
  • the alteration preventing layer in the step of forming the alteration preventing layer, may be formed by electroless plating.
  • the alteration preventing layer can be easily formed on the upper surface of the plug by electroless plating.
  • nonvolatile memory element a variable resistance nonvolatile memory element (hereinafter also simply referred to as “nonvolatile memory element”) and a manufacturing method thereof according to one embodiment of the present invention will be described with reference to the drawings.
  • FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory element 10 according to Embodiment 1 of the present invention.
  • a nonvolatile memory element 10 shown in FIG. 1 includes a first interlayer insulating layer 101, a first wiring 102, a second interlayer insulating layer 103, a first plug 104, an alteration preventing layer 105, a resistance change element 109 (laminated layer).
  • Such a nonvolatile memory element 10 constitutes a part of a region called a memory cell array or a memory main body in a general semiconductor memory device.
  • the semiconductor memory device may include a drive circuit for driving the memory cell array in addition to the memory cell array including the nonvolatile memory element 10.
  • the drive circuit applies an electric pulse (electric signal) to the nonvolatile memory element 10 in the memory cell array.
  • the resistance state of the resistance change element 109 of the nonvolatile memory element 10 is reversibly changed by an electric pulse for data writing. Further, the resistance state of the variable resistance element 109 of the nonvolatile memory element 10 is read by an electric pulse for reading data.
  • the first interlayer insulating layer 101 is formed on a semiconductor substrate (not shown) on which transistors and the like are formed.
  • the first interlayer insulating layer 101 is made of, for example, silicon oxide.
  • the first wiring 102 is formed on the first interlayer insulating layer 101.
  • the first wiring 102 is made of, for example, copper or aluminum.
  • the second interlayer insulating layer 103 is formed on the first wiring 102.
  • the second interlayer insulating layer 103 is made of, for example, silicon oxide having a thickness of 100 to 500 nm.
  • the first plug 104 is formed inside the second interlayer insulating layer 103.
  • the first plug 104 is electrically connected to the first wiring 102.
  • the first plug 104 is made of, for example, tungsten or copper.
  • the diameter of the first plug 104 is, for example, 70 to 240 nm.
  • the alteration preventing layer 105 is formed so as to cover the entire upper surface of the first plug 104.
  • the “upper surface” and the “lower surface” are defined such that the direction from the first wiring 102 to the stacked body is the top and the direction from the stacked body to the first wiring 102 is the bottom.
  • “A whole area of the upper surface of the first plug 104” means a surface exposed to the upper side immediately after the first plug 104 is formed.
  • the alteration preventing layer 105 is made of a material having conductivity, oxygen barrier properties and etching resistance, such as tungsten nitride.
  • the horizontal sectional area of the lower surface of the alteration preventing layer 105 is configured to be equal to the horizontal sectional area of the upper surface of the plug 104.
  • the horizontal cross-sectional area means an area of a cross section cut by a horizontal plane perpendicular to the vertical direction (vertical direction) in a state where the resistance change element 109 is disposed on the upper side and the first plug 104 is disposed on the lower side. .
  • the alteration preventing layer 105 Since the alteration preventing layer 105 has an oxygen barrier property, as will be described later, when the resistance change element 109 is formed into a dot shape by etching, the upper surface of the alteration preventing layer 105 is oxidized by the etching gas. It is suppressed. Further, since the alteration preventing layer 105 has etching resistance, as will be described later, when the resistance change element 109 is formed into a dot shape by etching, the upper surface of the alteration preventing layer 105 is suppressed from being etched by etching. The
  • the resistance change element 109 is formed on the second interlayer insulating layer 103 and is electrically connected to the first plug 104 via the alteration preventing layer 105.
  • the resistance change element 109 is formed as a dot-shaped laminate.
  • the dot shape refers to the shape of a laminate having a rectangular horizontal cross section with a side of 100 to 400 nm.
  • the horizontal cross-sectional area of the lower surface of the resistance change element 109 (that is, the lower surface of the first electrode 106) is the upper surface of the alteration preventing layer 105 that covers the upper surface of the first plug 104. It is configured to be smaller than the horizontal cross sectional area.
  • the diameter of the first plug 104 including the alteration preventing layer 105 may be 240 nm
  • the horizontal cross section of the resistance change element 109 may be a rectangular shape having a side of 200 nm.
  • the resistance change element 109 includes the first electrode 106, the resistance change layer 107, and the second electrode 108.
  • the first electrode 106 and the second electrode 108 are disposed to face each other.
  • the first electrode 106 is electrically connected to the first plug 104 through the alteration preventing layer 105.
  • the resistance change layer 107 is interposed between the first electrode 106 and the second electrode 108, and the resistance value reversibly changes based on an electrical signal applied between the first electrode 106 and the second electrode 108. It is a layer to do.
  • the resistance change layer 107 is, for example, a layer that reversibly transitions between a high resistance state and a low resistance state according to the polarity of the voltage applied between the first electrode 106 and the second electrode 108.
  • the resistance change layer 107 is configured by stacking at least two layers of a first resistance change layer 107 a connected to the first electrode 106 and a second resistance change layer 107 b connected to the second electrode 108. The The material constituting the resistance change layer 107 will be described later.
  • the third interlayer insulating layer 110 is formed on the second interlayer insulating layer 103.
  • a variable resistance element 109 is formed inside the third interlayer insulating layer 110.
  • the second plug 111 is formed inside the third interlayer insulating layer 110.
  • the second plug 111 is electrically connected to the second electrode 108 of the variable resistance element 109.
  • the second wiring 112 is formed on the third interlayer insulating layer 110 and on the upper surface of the second plug 111.
  • the second wiring 112 is electrically connected to the second plug 111.
  • the first resistance change layer 107a is composed of an oxygen-deficient first metal oxide
  • the second resistance change layer 107b is a second metal oxide having a lower degree of oxygen deficiency than the first metal oxide. It consists of things.
  • a minute local region in which the degree of oxygen deficiency reversibly changes according to the application of the electric pulse is formed.
  • the local region is considered to include a filament composed of oxygen defect sites.
  • the resistance change layer 107 can be made of a transition metal oxide such as tantalum oxide, for example.
  • the first resistance change layer 107a is made of an oxygen-deficient transition metal oxide
  • the second resistance change layer 107b is oxygen having a lower oxygen deficiency than the first resistance change layer 107a. It is composed of a deficient transition metal oxide.
  • the oxygen-deficient transition metal oxide has an oxygen content (atomic ratio: the ratio of the number of oxygen atoms to the total number of atoms) compared to a transition metal oxide having a stoichiometric composition. It refers to less oxide.
  • Oxygen deficiency means the stoichiometric composition of metal oxide (if there are multiple stoichiometric compositions, the stoichiometric composition having the highest resistance value among them). This refers to the proportion of oxygen that is deficient with respect to the amount of oxygen that forms the oxide. Stoichiometric metal oxides are more stable and have higher resistance values than other metal oxides.
  • the oxide having the stoichiometric composition according to the above definition is Ta 2 O 5 , and can be expressed as TaO 2.5 .
  • the oxygen excess metal oxide has a negative oxygen deficiency.
  • the oxygen deficiency is described as including a positive value, 0, and a negative value.
  • An oxide with a low degree of oxygen deficiency has a high resistance value because it is closer to a stoichiometric oxide, and an oxide with a high degree of oxygen deficiency has a low resistance value because it is closer to the metal constituting the oxide.
  • the “oxygen content” is the ratio of oxygen atoms to the total number of atoms.
  • the oxygen content of Ta 2 O 5 is the ratio of oxygen atoms to the total number of atoms (O / (Ta + O)), which is 71.4 atm%. Therefore, the oxygen-deficient tantalum oxide has an oxygen content greater than 0 and less than 71.4 atm%.
  • the oxygen content has a corresponding relationship with the degree of oxygen deficiency. That is, when the oxygen content of the second metal oxide is greater than the oxygen content of the first metal oxide, the oxygen deficiency of the second metal oxide is greater than the oxygen deficiency of the first metal oxide. small.
  • the metal constituting the resistance change layer 107 may be a metal other than tantalum.
  • a metal constituting the resistance change layer 107 a transition metal or aluminum (Al) can be used. That is, the resistance change layer 107 can be made of a transition metal oxide or aluminum oxide.
  • the transition metal tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), niobium (Nb), tungsten (W), nickel (Ni), or the like can be used. Since transition metals can take a plurality of oxidation states, different resistance states can be realized by oxidation-reduction reactions.
  • the composition of the first metal oxide is HfO x
  • x is 0.9 or more and 1.6 or less
  • the composition of the second metal oxide is HfO x.
  • the resistance value of the resistance change layer 107 can be stably changed at high speed.
  • the thickness of the second metal oxide may be 3 to 4 nm.
  • the composition of the first metal oxide is ZrO x
  • x is 0.9 or more and 1.4 or less
  • the composition of the second metal oxide is ZrO x.
  • the thickness of the second metal oxide may be 1 to 5 nm.
  • the first resistance change layer 107a when the first resistance change layer 107a is composed of oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, or oxygen-deficient zirconium oxide, the first resistance change layer 107a includes tantalum, It can be formed by a so-called reactive sputtering method in which hafnium or zirconium is used as a target and sputtering is performed in argon gas and oxygen gas.
  • the degree of oxygen deficiency of the first resistance change layer 107a can be easily adjusted by changing the flow ratio of oxygen gas to argon gas during reactive sputtering. This treatment can be performed at room temperature without particularly heating the semiconductor substrate.
  • the second resistance change layer 107b can be formed by exposing the surface of the first resistance change layer 107a formed by a reactive sputtering method to plasma of argon gas and oxygen gas.
  • the resistance change layer 107 is made of, for example, oxygen-deficient tantalum oxide, oxygen-deficient hafnium oxide, or oxygen-deficient zirconium oxide, in addition to high-speed operation, reversibly stable rewriting characteristics and good
  • the nonvolatile memory element 10 having a retention characteristic with a satisfactory resistance value can be realized.
  • the resistance change layer 107 is made of an oxygen-deficient tantalum oxide
  • the nonvolatile memory element 10 can be manufactured by a manufacturing process having a high affinity for a normal Si semiconductor process.
  • the second metal oxide may have a lower degree of oxygen deficiency than the first metal oxide, that is, may have a higher resistance.
  • a first metal constituting the first metal oxide to be the first resistance change layer 107a, a second metal constituting the second metal oxide to be the second resistance change layer 107b, are made of different materials, the standard electrode potential of the second metal may be lower than the standard electrode potential of the first metal.
  • the standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize. Thereby, an oxidation-reduction reaction easily occurs in the second metal oxide having a relatively low standard electrode potential.
  • the resistance change phenomenon is caused by a change in the filament (conducting path) caused by an oxidation-reduction reaction in a minute local region formed in the second metal oxide having a high resistance. Degree) is considered to change.
  • metal oxide Al 2 O 3
  • Al 2 O 3 aluminum oxide
  • oxygen-deficient tantalum oxide (TaO x ) may be used for the first metal oxide
  • aluminum oxide (Al 2 O 3 ) may be used for the second metal oxide.
  • the resistance change phenomenon in the resistance change layer 107 having the laminated structure is caused by a redox reaction in a minute local region formed in the second metal oxide having a high resistance, and a filament (conducting path) in the local region.
  • Changes the resistance value is considered to change. That is, when a positive voltage is applied to the second electrode 108 connected to the second metal oxide with reference to the first electrode 106, oxygen ions in the resistance change layer 107 are moved to the second metal oxide side. Gravitate. As a result, an oxidation reaction occurs in a small local region formed in the second metal oxide, and the degree of oxygen deficiency is reduced. As a result, it is considered that the filaments in the local region are not easily connected and the resistance value is increased.
  • the second electrode 108 connected to the second metal oxide having a lower oxygen deficiency constitutes the second metal oxide such as platinum (Pt), iridium (Ir), palladium (Pd), etc.
  • the metal and the material constituting the first electrode 106 are made of a material having a higher standard electrode potential.
  • the first electrode 106 connected to the first metal oxide having a higher degree of oxygen deficiency is, for example, tungsten (W), nickel (Ni), tantalum (Ta), titanium (Ti), aluminum (Al ), Tantalum nitride (TaN), titanium nitride (TiN), or the like, a material having a lower standard electrode potential than the metal constituting the first metal oxide may be used.
  • the standard electrode potential represents a characteristic that the higher the value is, the more difficult it is to oxidize.
  • the standard electrode potential V2 of the second electrode 108, the standard electrode potential Vr2 of the metal constituting the second metal oxide, the standard electrode potential Vr1 of the metal constituting the first metal oxide, the first electrode 106 The relationship of V r2 ⁇ V 2 and V 1 ⁇ V 2 may be satisfied with the standard electrode potential V1. Furthermore, V2> Vr2 and Vr1 ⁇ V1 may be satisfied.
  • a voltage is first applied to the resistance change element 109, and a part of the second resistance change layer 107b having a low oxygen deficiency is locally applied. An initial break to short circuit is performed. What is important at this time is that a sufficient voltage is applied to the resistance change element 109 without applying an unnecessary voltage to transistors other than the resistance change element 109 and parasitic resistance components.
  • a voltage satisfying a predetermined condition is applied between the first electrode 106 and the second electrode 108 by an external power source (not shown) and a drive circuit. Apply between.
  • 2A to 5B are cross-sectional views illustrating a method for manufacturing the nonvolatile memory element 10 according to the present embodiment.
  • the process, material, film thickness, etc. which are demonstrated below are an illustration to the last, and the manufacturing method of the non-volatile memory element 10 which concerns on this invention is not limited to this Embodiment.
  • the order of each process etc. can be changed as needed, or another well-known process can be added.
  • a first interlayer insulating layer 101 made of silicon oxide is formed on a semiconductor substrate (not shown) on which transistors and the like are formed in advance by using plasma CVD or the like. To do. Thereafter, the first wiring 102 is formed over the first interlayer insulating layer 101.
  • the first wiring 102 can be formed by a general semiconductor process, for example, film formation by sputtering, shape processing by photolithography, and dry etching. it can.
  • copper (Cu) is used as the material for the first wiring 102
  • the first wiring 102 can be embedded in the first interlayer insulating layer 101 by using a damascene method.
  • a first plug 104 that is electrically connected to the first wiring 102 is formed on the first wiring 102.
  • a second interlayer insulating layer 103 is further deposited on the first wiring 102. Note that, if necessary, step relaxation is performed on the upper surface of the second interlayer insulating layer 103 by CMP.
  • a contact hole 113 for embedding the first plug 104 is formed in a portion of the second interlayer insulating layer 103 corresponding to a predetermined position on the first wiring 102 by photolithography and dry etching. .
  • a barrier metal layer composed of titanium nitride (for example, a film thickness of 5 to 40 nm) and titanium (for example, a film thickness of 5 to 40 nm) is formed on the second interlayer insulating layer 103 including the formed contact hole 113. Is deposited by sputtering or the like. Further, tungsten (for example, a film thickness of 50 to 300 nm) as a conductive material is deposited by CVD or the like.
  • the first plug 104 is formed in the contact hole 113 by filling the contact hole 113 with the barrier metal layer and tungsten. Thereafter, the excess tungsten and barrier metal layer on the upper surface of the first plug 104 are removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104 are formed flat.
  • the upper surface of the first plug 104 is overpolished by CMP to form a recess (concave portion) 114 having a depth of about 10 to 50 nm on the upper side of the first plug 104.
  • etch back by dry etching can be performed.
  • a cap metal film 105 ′ made of, for example, tungsten nitride is deposited on the second interlayer insulating layer 103 including the recess 114 by CVD or the like. By filling the recess 114 with tungsten nitride, the alteration preventing layer 105 is formed in the recess 114.
  • the excess cap metal film 105 ′ on the upper surface of the second interlayer insulating layer 103 is removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the alteration preventing layer 105 are removed. Are formed flat.
  • the first plug 104 and the alteration preventing layer 105 are both embedded in the contact hole 113, when a plurality of the nonvolatile memory elements 10 are arranged at intervals, the adjacent first plugs 104 are arranged. It is possible to reliably prevent the 104 from being short-circuited.
  • tungsten nitride can be used as the alteration preventing layer 105 covering only the upper surface of the first plug 104 made of tungsten.
  • the first plug 104 made of tungsten is formed, and then the first plug 104 is subjected to plasma of argon gas and nitrogen gas. There are ways to expose the surface.
  • the alteration preventing layer 105 that covers only the upper surface of the first plug 104 and is made of tungsten nitride can be formed in a self-forming manner.
  • a resistance change element 109 as a stacked body is formed on the first plug 104 via the alteration preventing layer 105.
  • a first electrode layer 106 ′ (for example, a film thickness of 30 nm) made of tantalum nitride, an oxygen-deficient type is formed on the second interlayer insulating layer 103 including the alteration preventing layer 105.
  • a resistance change thin film 107 ′ (for example, a film thickness of 50 nm) made of tantalum oxide and a second electrode layer 108 ′ (for example, a film thickness of 50 nm) made of iridium are deposited so as to be stacked horizontally in this order.
  • the resistance change thin film 107 ′ is configured by laminating a first resistance change thin film 107 a ′ and a second resistance change thin film 107 b ′ in this order.
  • the first resistance change thin film 107a ' is formed by using a so-called reactive sputtering method in which sputtering is performed in an argon and oxygen gas atmosphere using tantalum as a target.
  • the oxygen concentration in the deposition chamber is controlled to 44.6 to 65.5 atm% by adjusting the flow rate of oxygen.
  • the resistivity of the first resistance change thin film 107a ' can be adjusted to 0.5 to 20 m ⁇ ⁇ cm.
  • the first variable resistance thin film 107a' having a resistivity of about 2 m ⁇ ⁇ cm can be formed.
  • the first electrode layer 106 'and the second electrode layer 108' are formed by the reactive sputtering method as described above.
  • the second resistance change thin film 107b ′ may be formed on the outermost surface layer of the first resistance change thin film 107a ′ by oxidizing the surface of the first resistance change thin film 107a ′.
  • the second resistance change thin film 107b ′ is formed of a Ta 2 O 5 layer having a stoichiometric composition that has a lower degree of oxygen deficiency than that of the first resistance change thin film 107a ′ or is not deficient in oxygen.
  • the thickness may be in the range of 2 to 12 nm.
  • each side is 200 nm.
  • the dot-shaped resistance change element 109 is formed.
  • the upper surface of the first plug 104 is covered with the alteration preventing layer 105, when the resistance change element 109 is formed into a dot shape by etching, The upper surface of the plug 104 is not exposed to an etching gas containing chlorine, fluorine, oxygen, or the like used for dry etching.
  • an etching gas containing chlorine, fluorine, oxygen, or the like used for dry etching.
  • the top surface of the first plug 104 can be prevented from being oxidized or denatured, and a first plug with good electrical characteristics can be formed.
  • a conductive hard mask (on the second electrode layer 108a ′ is used to prevent the uppermost second electrode 108 from being etched away. (Not shown) may be deposited by sputtering or the like. As the material of the hard mask, for example, any one of tantalum nitride, titanium nitride, and titanium-aluminum nitride is used. After the variable resistance element 109 is formed in a dot shape, the hard mask remaining on the second electrode 108 may be removed by etching or the like.
  • the resistance change element 109 may be processed into a dot shape, and then annealed in an oxygen atmosphere (temperature: 300 to 450 ° C.) to oxidize the side wall surface of the first resistance change layer 107a and insulate it. .
  • an oxygen atmosphere temperature: 300 to 450 ° C.
  • the active area is reduced and the leakage current is reduced, so that the initial break voltage is lowered and the application time is shortened. be able to.
  • the oxidation of the first plug 104 is performed when the side wall surface of the variable resistance element 109 is oxidized. Can be prevented.
  • the nonvolatile memory element 10 that has a small parasitic resistance component other than the resistance change element 109 and operates stably can be realized.
  • a third interlayer insulating layer 110 for embedding and forming the second plug 111 is deposited on the second interlayer insulating layer 103 including the resistance change element 109 by plasma CVD or the like. To do.
  • the third interlayer insulating layer 110 is made of silicon oxide or the like. If necessary, the step is reduced on the upper surface of the third interlayer insulating layer 110 by CMP.
  • the second electrode 108 is electrically connected to the inside of the third interlayer insulating layer 110 and on the variable resistance element 109 by a method similar to the method of forming the first plug 104.
  • the second plug 111 to be formed is formed.
  • the second plug 111 is made of tungsten or the like.
  • a second wiring 112 electrically connected to the second plug 111 is formed on the third interlayer insulating layer 110 and the second plug 111. Similar to the first wiring 102, the second wiring 112 is made of aluminum, copper, or the like.
  • the nonvolatile memory element 10 shown in FIG. 1 is formed.
  • the dry etching and the active area of the resistance change element 109 are reduced by forming the alteration preventing layer 105 that covers the upper surface of the first plug 104.
  • the first plug 104 can be prevented from being oxidized or deteriorated, and the first plug 104 with good electrical characteristics can be formed.
  • the nonvolatile memory element 10 that has a small parasitic resistance component other than the resistance change element 109 and operates stably can be realized.
  • the second electrode 108 of the variable resistance element 109 is made of iridium, but the present invention is not limited to this.
  • the second electrode 108 may be made of any metal of platinum, copper, tungsten, iridium, and palladium, or a combination or alloy of these metals.
  • the initial break voltage refers to a voltage that can be applied to the resistance change element 109 to reduce the resistance value of the resistance change layer 107 from the initial resistance value to the normal operating range.
  • tantalum and titanium nitride may be used as the material for the first electrode 106.
  • the resistance change layer 107 may be formed by stacking two or more resistance change layers made of the same kind of transition metal oxide.
  • FIG. 6 is a cross-sectional view showing the configuration of the nonvolatile memory element 20 according to the present embodiment.
  • the horizontal cross-sectional area of the lower surface of the resistance change element 109A (that is, the lower surface of the first electrode 106) is horizontal with respect to the upper surface of the alteration preventing layer 105A.
  • the central axis 120a of the variable resistance element 109A is offset in the horizontal direction (right side in FIG. 6) with respect to the central axis 120b of the first plug 104A. Therefore, a part of the upper surface of the alteration preventing layer 105A is exposed without being covered by the lower surface of the resistance change element 109A.
  • the “center axis” is defined by a line that passes through the center of the horizontal section of the variable resistance element 109A and the first plug 104A and is perpendicular to the horizontal section when the horizontal section is circular.
  • the horizontal cross section of the resistance change element 109A and the first plug 104A is a polygon or the like, it is defined by a line that passes through the center of gravity and is perpendicular to the horizontal cross section.
  • the center axis of the first plug 104A and the center of the resistance change element 109A Misalignment with the shaft may occur. Therefore, especially when the horizontal cross-sectional area of the lower surface of the first electrode 106 is larger than the horizontal cross-sectional area of the upper surface of the first plug 104A, the above-described misalignment tends to occur as shown in FIG.
  • the alteration preventing layer 105A since the upper surface of the first plug 104A is covered with the alteration preventing layer 105A, dry etching for processing the resistance change element 109A into a dot shape and an active area for reducing the active area of the resistance change element 109A are reduced. Oxidation or alteration of the first plug 104A due to side wall surface oxidation can be prevented.
  • FIG. 7 is a cross-sectional view showing the configuration of the nonvolatile memory element 30 according to this embodiment.
  • the first electrode of the resistance change element 109B is omitted, and the alteration preventing layer 105B also functions as the first electrode of the resistance change element 109B.
  • the resistance change layer 107 is disposed between the alteration preventing layer 105 ⁇ / b> B and the second electrode 108.
  • the horizontal sectional area of the lower surface of the resistance change layer 107 is configured to be smaller than the horizontal sectional area of the upper surface of the alteration preventing layer 105B.
  • Other configurations of the nonvolatile memory element 30 according to the present embodiment are substantially the same as those of the nonvolatile memory element 10 according to the first embodiment.
  • the resistance change element 109B when the resistance change element 109B is formed in a dot shape by dry etching, a stacked body including the second electrode 108 and the resistance change layer 107 may be processed.
  • the type and thickness of the target film can be reduced. Thereby, the dimensional variation of the resistance change element 109B can be reduced, and the resistance change element 109B can be easily miniaturized.
  • the second electrode 108 As a material of the second electrode 108, a material having a higher standard electrode potential than the material constituting the transition metal constituting the resistance change layer 107B and the alteration preventing layer 105B, such as platinum (Pt) or iridium (Ir), is used. By using it, a redox reaction occurs selectively in the resistance change layer 107 in the vicinity of the interface between the second electrode 108 and the resistance change layer 107, and a stable resistance change phenomenon is obtained.
  • platinum platinum
  • Ir iridium
  • the horizontal cross-sectional area of the lower surface of the resistance change layer 107 is configured to be equal to or larger than the horizontal cross-sectional area of the upper surface of the alteration preventing layer 105B to change the resistance.
  • the central axis of the element 109B can be offset in the horizontal direction with respect to the central axis of the first plug 104.
  • FIG. 8 is a cross-sectional view showing a configuration of the nonvolatile memory element 40 according to the present embodiment.
  • the alteration preventing layer 105 ⁇ / b> C is formed so as to protrude upward from the upper surface of the second interlayer insulating layer 103.
  • the upper side of the upper surface of the second interlayer insulating layer 103 may be referred to as “outside of the contact hole 113”.
  • the first wiring 102C and the second wiring 112C are embedded in the first interlayer insulating layer 101C and the third interlayer insulating layer 110C, respectively.
  • the second plug is not provided.
  • Other configurations of the nonvolatile memory element 40 according to the present embodiment are substantially the same as those of the nonvolatile memory element 10 according to the first embodiment.
  • 9A to 12B are cross-sectional views showing a method for manufacturing the nonvolatile memory element 40 according to the present embodiment.
  • a first interlayer insulating layer 101C is formed on a semiconductor substrate (not shown) on which transistors and the like are formed in advance. Thereafter, a wiring groove 115 for embedding and forming the first wiring 102C is formed in the first interlayer insulating layer 101C by photolithography and dry etching.
  • a wiring material 102C ′ is deposited on the first interlayer insulating layer 101C including the wiring trench 115 by a sputtering method or the like.
  • the wiring material 102C ′ includes, for example, a barrier metal layer in which tantalum nitride (film thickness 5 to 40 nm) and tantalum (5 to 40 nm) are stacked, copper (50 to 300 nm) serving as a seed layer for electrolytic plating, and Consists of.
  • copper is further deposited on the copper seed layer by electrolytic plating to fill the wiring trench 102 ⁇ / b> C ′ with copper.
  • the second interlayer insulating layer 103 made of silicon nitride or silicon oxide is formed on the first interlayer insulating layer 101C including the first wiring 102C by plasma CVD or the like. Is further deposited. Note that, if necessary, step relaxation is performed on the upper surface of the second interlayer insulating layer 103 by CMP. Thereafter, a contact hole 113 for embedding the first plug 104 is formed at a predetermined position on the first wiring 102C by photolithography and dry etching.
  • a barrier metal layer made of tantalum nitride and tantalum and copper as a conductive material are deposited on the second interlayer insulating layer 103 including the formed contact hole 113 by sputtering or the like.
  • copper is further deposited by electrolytic plating using copper as a seed to fill the contact hole 113 with the barrier metal layer and copper.
  • the first plug 104 is formed.
  • excess copper and the barrier metal layer on the upper surface of the first plug 104 are removed by CMP, and the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104 are formed flat. As a result, the first plug 104 is completely embedded in the contact hole 113.
  • an alteration preventing layer 105C covering the upper surface of the first plug 104 is formed by an electroless plating method.
  • the alteration preventing layer 105 ⁇ / b> C is formed so as to protrude upward with respect to a flat surface constituted by the upper surface of the second interlayer insulating layer 103 and the upper surface of the first plug 104.
  • the alteration preventing layer 105C is made of a cobalt-tungsten-phosphorus (CoWP) alloy.
  • CoWP cobalt-tungsten-phosphorus
  • the alteration preventing layer 105C is selectively deposited only on the upper surface of the first plug 104 made of a conductive material, and on the second interlayer insulating layer 103 made of an insulating material. Therefore, the alteration preventing layer 105C that covers only the upper surface of the first plug 104 can be formed selectively. Further, by using the electroless plating method, it is not necessary to perform shape processing by CMP, dry etching, or the like, which is convenient for miniaturization. Furthermore, since copper has a resistivity lower than that of tungsten, the resistivity of the first plug 104 can be lowered by configuring the first plug 104 with copper, and the influence of wiring delay is small and high-speed operation is possible. A nonvolatile memory element 40 can be realized.
  • a plating bath containing hypophosphite such as sodium hypophosphite
  • hypophosphite such as sodium hypophosphite
  • the surface of the first plug 104 made of copper may be preliminarily immersed in an aqueous palladium chloride solution for several seconds to provide a palladium catalyst layer. This is because the surface of the metal is catalyzed by impregnating iron group elements such as iron (Fe), nickel (Ni), cobalt (Co) and palladium (Pa), and metals of platinum group elements. This is because an oxidation reaction of hypophosphite ions occurs.
  • a cap layer made of silicon nitride is deposited in order to prevent copper from diffusing into the interlayer insulating layer from the upper surface of the wiring and the plug.
  • depositing a cap layer made of silicon nitride, which is an insulator increases the charge capacity between the wiring layers and causes a problem of RC delay of the circuit.
  • the alteration preventing layer 105C made of a conductive material is used, the charge capacity between the wiring layers can be reduced as compared with the case where the alteration preventing layer made of an insulating material is used. Since the RC delay can be suppressed, the nonvolatile memory element 40 capable of high-speed operation can be realized.
  • variable resistance element 109 is formed on the first plug 104 including the alteration preventing layer 105C by a method similar to the method for manufacturing the nonvolatile memory element 10 according to Embodiment 1. .
  • a third interlayer insulating layer 110C is deposited on the second interlayer insulating layer 103 including the resistance change element 109 by plasma CVD or the like.
  • the third interlayer insulating layer 110C is made of silicon oxide or the like. Note that, if necessary, the step is relaxed on the upper surface of the third interlayer insulating layer 110C by CMP.
  • a wiring trench 116 for embedding the second wiring 112C is formed in the third interlayer insulating layer 110C by photolithography and dry etching.
  • a wiring material 112C ' is deposited on the third interlayer insulating layer 110C including the wiring trench 116 by sputtering or the like.
  • the wiring material 112C ′ includes, for example, a barrier metal layer in which tantalum nitride (for example, a film thickness of 5 to 40 nm) and tantalum (for example, 5 to 40 nm) are laminated, and copper (for example, a seed layer for electrolytic plating) (for example, , 50 to 300 nm). Thereafter, copper is further deposited on the copper seed layer by electrolytic plating to fill the wiring trench 112C 'with copper.
  • tantalum nitride for example, a film thickness of 5 to 40 nm
  • tantalum for example, 5 to 40 nm
  • copper for example, a seed layer for electrolytic plating
  • excess copper on the upper surface of the third interlayer insulating layer 110C is removed by CMP from the deposited barrier metal layer and copper, and the upper surface of the third interlayer insulating layer 110C and the first copper are removed.
  • the upper surface of the second wiring 112C is formed flat. Thereby, the second wiring 112C is formed.
  • the nonvolatile memory element 40 shown in FIG. 8 is formed.
  • the horizontal cross-sectional area of the lower surface of the first electrode 106 is configured to be equal to or larger than the horizontal cross-sectional area of the upper surface of the alteration preventing layer 105C to change the resistance.
  • the central axis of the element 109 can be offset in the horizontal direction with respect to the central axis of the first plug 104.
  • the first electrode of the resistance change element 109 may be omitted, and the alteration preventing layer 105C may also function as the first electrode of the resistance change element 109.
  • non-volatile memory element which concerns on the one or several aspect of this invention, and its manufacturing method were demonstrated based on embodiment, this invention is not limited to this embodiment. Unless it deviates from the gist of the present invention, one or more of the present invention may be applied to various modifications that can be conceived by those skilled in the art, or forms constructed by combining components in different embodiments. It may be included within the scope of the embodiments.
  • the transition metal oxide constituting the resistance change layer has been described.
  • the transition metal oxide layer sandwiched between them it is only necessary to include an oxide layer such as tantalum, hafnium, and zirconium as the main resistance change layer that exhibits resistance change. It may be included. It is possible to intentionally include a small amount of other elements by fine adjustment of the resistance value, and such a case is also included in the scope of the present invention. For example, when nitrogen is added to the resistance change layer, the resistance value of the resistance change layer increases and the resistance change resistance can be improved.
  • variable resistance thin film when a variable resistance thin film is formed by sputtering, an unintended trace amount of elements may be mixed into the variable resistance thin film due to residual gas and gas release from the vacuum vessel wall. Naturally, such a trace amount of elements mixed in the resistance change thin film is also included in the scope of the present invention.
  • variable resistance element of the present invention is not limited to this shape.
  • the alteration preventing layer can also prevent alteration with respect to other steps. For example, alteration (oxidation, nitridation, fluorination, etc.) when forming an interlayer insulating layer after plug formation can be prevented.
  • alteration preventing layer of the present invention has an effect of preventing alteration caused by gas or plasma used in the process after plug formation.
  • the variable resistance element is configured by the ReRAM including the variable resistance layer including the oxygen-deficient transition metal oxide.
  • the variable resistance element is used as an electrical signal. Any element that reversibly changes between a high resistance state and a low resistance state having a resistance value lower than that of the high resistance state may be used. Therefore, the resistance change element includes, for example, a phase change memory (PCRAM: Phase-Change RAM) using a phase change material, a magnetic substance as a storage element, and a magnetoresistive memory (MRAM) adopting spin injection magnetization reversal as a writing method. : Magnetoretic RAM) or the like.
  • PCRAM Phase-Change RAM
  • MRAM magnetoresistive memory
  • FeRAM Ferroelectric RAM
  • the nonvolatile memory elements according to the first to fourth embodiments described above are typically realized as an LSI that is an integrated circuit. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.
  • the numerical values that define the dimensions of the constituent elements of the nonvolatile memory elements used in the first to fourth embodiments and the process conditions for manufacturing are all examples for specifically explaining the present invention.
  • the present invention is not limited to the exemplified numerical values.
  • all the materials of the constituent elements shown in the above-described Embodiments 1 to 4 are exemplified for specifically explaining the present invention, and the present invention is not limited to the exemplified materials.
  • tungsten nitride or cobalt / tungsten / phosphorous alloy is used as the material for the alteration preventing layer.
  • cobalt / tungsten / boron alloy or palladium is used in addition to these. You can also.
  • variable resistance layer of the variable resistance element has a two-layer structure.
  • a single-layer structure may be used.
  • the present invention can be applied to a variable resistance nonvolatile memory element and a manufacturing method thereof. Further, the present invention is useful for various electronic devices using a nonvolatile memory element.
  • Nonvolatile memory element 101 101C First interlayer insulating layer 102, 102C First wiring 102C 'Wiring material 103 Second interlayer insulating layer 104, 104A First plug 105, 105A 105B, 105C Anti-altering layer 105 ′
  • Cap metal film 106 First electrode 106 ′ First electrode thin film 107 Resistance change layer 107a First resistance change layer 107b Second resistance change layer 107 ′ Resistance change thin film 107a ′ First Resistance change thin film 107b ′ Second resistance change thin film 108 Second electrode 108 ′ Second electrode thin film 109, 109A, 109B Resistance change element 110, 110C Third interlayer insulating layer 111 Second plug 112, 112C Second wiring 112C 'wiring material 113 contact hole 114 recess 115 wiring groove 116 wiring groove 1 0a, 120b Central axis 201 Copper metallization layer 202 Plug 203 IMD layer 204 Groove 205 Barrier layer 206 Copper interconnect layer 207

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  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un élément de stockage non volatil qui comprend un premier conducteur (102), un premier bouchon (104) qui est disposé sur le premier conducteur (102) et qui lui est électriquement connecté, une couche de prévention d'altération (105) qui recouvre la totalité de la région d'une surface supérieure du premier bouchon (104) et qui possède une conductivité électrique, un élément à résistance variable (109) qui recouvre une partie d'une surface supérieure de la couche de prévention d'altération (105) et qui est couplé électriquement au premier bouchon (104), via la couche de prévention d'altération (105), et un second conducteur (112) qui est placé sur l'élément à résistance variable (109) et lui est connecté électriquement. L'élément à résistance variable (109) comprend une couche à résistance variable (107) dont l'état de résistance varie de manière réversible en fonction d'un signal électrique qui lui est appliqué et l'aire de la section transversale horizontale d'une surface inférieure de la couche de prévention d'altération (105) est égale à l'aire de la section transversale horizontale de la surface supérieure du premier bouchon (104).
PCT/JP2012/006601 2011-10-21 2012-10-16 Élément de stockage non volatil et son procédé de fabrication WO2013057920A1 (fr)

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TWI552316B (zh) * 2014-06-16 2016-10-01 華邦電子股份有限公司 電阻式非揮發性記憶體裝置及其製造方法
US9478584B2 (en) 2013-12-16 2016-10-25 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile memory device and method for manufacturing the same
US9773842B2 (en) 2015-12-23 2017-09-26 Winbond Electronics Corp. Memory devices
TWI711196B (zh) * 2016-03-24 2020-11-21 台灣積體電路製造股份有限公司 磁阻隨機存取記憶體元件及其形成方法

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WO2011024455A1 (fr) * 2009-08-28 2011-03-03 パナソニック株式会社 Dispositif de mémoire à semi-conducteur et procédé de fabrication de celui-ci
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JP2007157942A (ja) * 2005-12-02 2007-06-21 Sony Corp 記憶素子及び記憶装置
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Publication number Priority date Publication date Assignee Title
US9478584B2 (en) 2013-12-16 2016-10-25 Panasonic Intellectual Property Management Co., Ltd. Nonvolatile memory device and method for manufacturing the same
TWI552316B (zh) * 2014-06-16 2016-10-01 華邦電子股份有限公司 電阻式非揮發性記憶體裝置及其製造方法
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TWI711196B (zh) * 2016-03-24 2020-11-21 台灣積體電路製造股份有限公司 磁阻隨機存取記憶體元件及其形成方法

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