WO2013023561A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
WO2013023561A1
WO2013023561A1 PCT/CN2012/080020 CN2012080020W WO2013023561A1 WO 2013023561 A1 WO2013023561 A1 WO 2013023561A1 CN 2012080020 W CN2012080020 W CN 2012080020W WO 2013023561 A1 WO2013023561 A1 WO 2013023561A1
Authority
WO
WIPO (PCT)
Prior art keywords
transparent electrode
photoresist
layer
array substrate
pattern
Prior art date
Application number
PCT/CN2012/080020
Other languages
English (en)
French (fr)
Inventor
秦纬
董云
Original Assignee
北京京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 北京京东方光电科技有限公司 filed Critical 北京京东方光电科技有限公司
Priority to US13/699,659 priority Critical patent/US9019462B2/en
Publication of WO2013023561A1 publication Critical patent/WO2013023561A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device. Background technique
  • TFT-LCD Thin film Transis-Liquid Crystal Display
  • ⁇ Twist Nematic
  • wide viewing angle mode includes a lateral electric field display technology, such as an In Panel Switching (IPS) mode, which can form a more reasonable planar electric field through the combination of transparent finger electrodes, optimize the arrangement of liquid crystal molecules, and at the same time, use transparent
  • IPS In Panel Switching
  • the array substrate includes: a plurality of gate lines 1, a plurality of data lines 2, and at least one common electrode line 15.
  • the common electrode line 15 is parallel to the data line 2.
  • the plurality of gate lines 1 and the plurality of data lines 2 cross each other to define a plurality of pixel units, each of which includes a thin film transistor as a switching element, a pixel electrode 5, and a common electrode 6, and the thin film transistor is connected to the pixel electrode 5.
  • the thin film transistor includes a gate 11, a source 12, a drain 13, and a semiconductor channel 3.
  • the end of the common electrode 6 of one row of pixel units is electrically connected to the common electrode line 15 through a via 41 above the common electrode 15.
  • a via hole 4 is formed in the insulating layer above the end of the gate line 1 for electrical connection with a driving circuit or the like.
  • the pixel electrode 5 and the common electrode 6 are comb electrodes, and their finger portions are cross-combined, and when they are energized with each other, an electric field is formed for driving the liquid crystal.
  • FIG. 2 is a schematic view showing the structure of an array substrate in which the conventional IPS wide viewing angle mode array substrate pixel electrode 5 and the common electrode 6 are misaligned. As shown in Figure 2, among one pixel unit, the common electrode The finger portion of 6 is offset to the right with respect to the finger portion of the pixel electrode 5. Summary of the invention
  • Embodiments of the present invention are directed to an array substrate, a method of fabricating the same, and a display device to avoid the Mura problem caused by the misalignment of the pixel electrode and the common electrode.
  • An embodiment of the present invention provides a method of fabricating an array substrate, the method comprising: depositing a first transparent electrode layer on a base substrate, and coating a first photoresist on the transparent electrode layer, a photoresist is exposed and developed, the first photoresist is retained at a position where the first transparent electrode is to be formed, thereby forming a first photoresist pattern; and the first photoresist pattern is used to Etching a transparent electrode layer to form a first transparent electrode; depositing a second transparent electrode layer on the etched base substrate, and then performing photoresist stripping on the first photoresist pattern, thereby removing the A portion of the second transparent electrode layer on the first photoresist pattern forms a second transparent electrode.
  • Another embodiment of the present invention provides an array substrate which is an array substrate fabricated by the method described above.
  • Still another embodiment of the present invention provides a display device including the array substrate as described above.
  • FIG. 1 is a schematic structural view of a conventional IPS wide viewing angle mode array substrate
  • FIG. 2 is a schematic diagram showing a structure when a pixel electrode and a common electrode of a conventional IPS wide viewing angle mode array substrate are misaligned;
  • FIG. 3 is a schematic view showing the formation of a gate pattern in the process of fabricating the array substrate of Embodiment 1.
  • FIG. 4 is a diagram showing the formation of a semiconductor channel and a source-drain pattern on the basis of the array substrate shown in FIG. 3 in the process of fabricating the array substrate of Embodiment 1. Rear schematic diagram;
  • FIG. 5 is a schematic view showing a photoresist pattern formed in the method for fabricating an array substrate of Embodiment 1;
  • FIG. 6 is a schematic cross-sectional structural view of the array substrate shown in FIG. 5 after A-A etching;
  • FIG. 7 is an AA position after deposition of the protective layer and the ITO layer after etching the array substrate shown in FIG. Schematic diagram of the sectional structure
  • FIG. 8 is a schematic structural view of the array substrate shown in FIG. 7 after photoresist stripping
  • FIG. 9 is a schematic view showing the structure of the array substrate shown in FIG. 8 for removing the transparent electrode layer in the peripheral region.
  • 10 is a schematic structural view of an array substrate finally obtained by the method for fabricating an array substrate of Embodiment 1;
  • FIG. 11 is a schematic view showing the formation of a gate pattern in the process of fabricating an array substrate of Embodiment 2
  • FIG. 12 is a diagram showing the formation of a semiconductor channel and a source-drain pattern on the basis of the array substrate shown in FIG. 11 in the process of fabricating the array substrate of Embodiment 2.
  • FIG. 13 is a schematic view showing a photoresist pattern formed in the array substrate manufacturing method of Embodiment 2;
  • FIG. 14 is a schematic structural view of the array substrate shown in FIG. 13 after photoresist stripping;
  • FIG. 15 is a schematic view showing the structure of the array substrate shown in FIG. 14 for removing the transparent electrode layer in the peripheral region.
  • Fig. 16 is a view showing the structure of an array substrate finally obtained by the method for fabricating the array substrate of the second embodiment. detailed description
  • the array substrate of the embodiment of the present invention includes a plurality of gate lines and a plurality of data lines, the gate lines and the data lines crossing each other thereby defining pixel units arranged in a matrix, each of the pixel units including a thin film transistor as a switching element and The pixel electrode and the common electrode that control the arrangement of the liquid crystals.
  • the gate of the thin film transistor of each pixel is electrically connected or integrally formed with the corresponding gate line
  • the source is electrically connected or integrally formed with the corresponding data line
  • the drain is electrically connected or integrally formed with the corresponding pixel electrode. In the following description, it is mainly performed for a single or a plurality of pixel units, but other pixel units may be identically formed.
  • Embodiment 1 of the method of manufacturing an array substrate of the present invention comprises the following steps.
  • Step 301 sequentially performing a photolithography process on the base substrate to form a gate pattern and a semiconductor channel And a source drain pattern, after which a first transparent electrode layer is deposited.
  • a process of forming a gate pattern on the base substrate is as follows, for example.
  • a gate metal film (not shown) having a thickness of, for example, 500 A to 4000 A is deposited on the base substrate 10 by sputtering or thermal evaporation.
  • a metal such as Cr, W, Ti, Ta, Mo, Al, Cu, an alloy, or a gate metal layer composed of a plurality of layers of metal may be used.
  • the base substrate 10 may be a glass or plastic substrate.
  • a photoresist (not shown) is coated on the gate metal film, and the photoresist is exposed and developed by using a mask to obtain a photoresist pattern, and then the obtained photoresist pattern is used as a pattern.
  • the etch mask etches the gate metal film. After the gate metal film having no photoresist region is etched away, the photoresist is removed to obtain a gate pattern as shown in FIG. 3 shows upper and lower rows of gate lines 1 formed on a base substrate, and a gate electrode 11 is formed on each gate line 1; at this time, the gate electrode 11 is formed integrally with the corresponding gate line 1.
  • the fabrication of the semiconductor channel and source and drain patterns includes the following steps.
  • the source drain pattern in this embodiment includes a pattern of data lines and source and drain of the thin film transistor.
  • a gate insulating layer film, a semiconductor layer film, a doped semiconductor layer film, and a source/drain metal film (not shown) are successively deposited on the base substrate 10 on which the gate pattern shown in Fig. 3 is formed, thereby obtaining a laminate of these films. Coating the photoresist on the source/drain metal film on the top of the laminate, and exposing and developing the photoresist by using a two-tone mask, and then etching to etch away the semiconductor layer film without the photoresist region. , doped semiconductor layer film and source and drain metal film.
  • the photoresist is subjected to ashing and thinning, and then the semiconductor layer at the channel position of the thin film transistor is etched by dry etching, followed by photoresist removal to form a semiconductor channel and a source/drain pattern.
  • the structure of the array substrate is as shown in FIG.
  • the data line 2 intersects the gate line 1 vertically; the source 12 and the drain 13 are formed over the active layer (not shown) and opposed to each other, and the active layer is at the source 12 and the drain 13 The portion between is a channel region 3 corresponding to the gate electrode 11; the active layer includes a patterned semiconductor layer film, a stack of doped semiconductor layer films; and the data line 2 is formed integrally with the source electrode 12.
  • a first transparent electrode layer (not shown) is deposited on the base substrate 10 on which the above structure is formed.
  • the step 301 may further be a sequential photolithography process on the base substrate to form a gate pattern, a semiconductor channel, and a source-drain pattern, and then deposit a layer of resin. a layer and a first transparent electrode layer. That is, before depositing the first transparent electrode layer, a resin layer of a certain thickness is deposited, for example, 1 to 3 ⁇ m, preferably 2 ⁇ m. In this example, by depositing the resin layer, the capacitance between the pixel electrode and the gate line can be reduced, and the area of the pixel electrode and the common electrode can be increased to increase the aperture ratio.
  • Step 302 exposing and developing the first transparent electrode layer and then the photoresist-coated base substrate by using a mask, and leaving a photoresist at a position where the pixel electrode is to be formed to form light for the pixel electrode Engraved graphics.
  • a first transparent electrode layer has been deposited on the entire base substrate.
  • the commonly used transparent conductive material is Indium Tin Oxides (ITO) or Indium Zinc Oxides (IZO).
  • the thickness is, for example, between 100 and 1000; for example, ITO is a nano ITO material.
  • the photoresist formed on the first transparent conductive layer is formed into a photoresist pattern by an exposure and development process using a mask, wherein a photoresist of a certain thickness is retained at a position of the transparent pixel electrode in the pixel unit, as shown in 5 is shown.
  • the position where the pixel electrode 5 is to be formed is covered with a photoresist 9, and the width of the photoresist 9 is slightly larger than the width of the pixel electrode 5 to be formed.
  • Step 303 etching a first transparent conductive layer on which a photoresist pattern is formed to form a pixel electrode.
  • the first transparent conductive layer on the base substrate may be chemically etched, and the acidic etching solution used may be a certain concentration of sulfuric acid, nitric acid, acetic acid, and mixed acid, and etched for the pixel electrode.
  • the pattern of the transparent electrode After etching, the sectional structure along the line A-A marked in Fig. 5 is as shown in Fig. 6.
  • the shape of the pixel electrode 5 is formed here.
  • the pixel electrode 5 is an example of the first transparent electrode of the present invention. A portion of the formed pixel electrode 5 is overlapped over the drain electrode 13, thereby achieving electrical connection therebetween.
  • a certain degree of over-etching is ensured by controlling factors such as etching time, temperature, etching solution concentration and the like, so that the pixel electrode 5 under the photoresist pattern 9 has a certain degree relative to the photoresist pattern 9 thereon.
  • the indentation R shown in Figure 6
  • the amount of indentation after the inscription is, for example, about 2 to 10 microns.
  • the obtained pixel electrode 5 is formed on the gate insulating layer 7.
  • the amount of overcut can be appropriately adjusted as needed to achieve the desired pitch.
  • This overetching process can further ensure that a gap is formed between the pixel electrode and the common electrode formed later, resulting in a uniform slit width. Thereby, a uniform parallel electric field can be formed between the pixel electrode and the common electrode, which avoids the display of the liquid crystal display The problem of uneven brightness and darkness.
  • Step 304 sequentially depositing a protective layer and a second transparent electrode layer on the etched base substrate, and then performing stripping of the photoresist.
  • a protective layer and a second transparent electrode layer are sequentially deposited on the glass substrate 10 having the sectional view shown in FIG. 6, that is, the protective layer and the second transparent are deposited without removing the photoresist pattern 9.
  • Electrode layer The transparent conductive material of the second transparent electrode layer is the same as or different from the first transparent electrode layer, and is, for example, an ITO material.
  • Fig. 7 is a view showing the sectional structure of the A-A position after deposition of the protective layer and the second transparent electrode layer on the structure shown in Fig. 5.
  • a photoresist pattern 9 is provided above the pixel electrode 5, and a protective layer 8 and a second transparent electrode layer are sequentially disposed above the photoresist pattern 9.
  • the second transparent electrode layer is used to form the common electrode 6; at the same time, the protective layer 8 and the second transparent electrode layer are also deposited at the gap between the two pixel electrodes 5.
  • the protective layer 8 is usually a silicon nitride layer which is an insulating and corrosion-resistant material, so that the gate metal layer and the source/drain metal layer can be effectively prevented from being corroded.
  • the protective layer 8 can also be omitted without affecting the uniformity of the electric field. Since ITO is a corrosion-resistant material, the protective layer above it can be omitted. In addition, since the silicon nitride layer is an insulating material, the surrounding electric field is not affected, so that the unprotected layer 8 has no influence on the deflection of the voltage-driven liquid crystal.
  • the array substrate having the sectional view shown in Fig. 7 was subjected to photoresist stripping.
  • the photoresist stripping is performed here, for example, the photoresist 9 and the protective layer 8 and the second transparent electrode layer deposited on the photoresist are simultaneously peeled off, and the structure on the base substrate 10 after peeling is as shown in the figure. 8 is shown.
  • the outer side of the gate line 1 and the data line 2 has a residual second transparent electrode layer 61 (shaded portion).
  • the shape of the common electrode 6 has been formed here.
  • This common electrode 6 is an example of the second transparent electrode of the present invention.
  • Both the pixel electrode 5 and the common electrode 6 are comb electrodes whose finger portions are staggered with each other with slits therebetween.
  • Step 305 exposing and etching again on the base substrate after stripping the photoresist to remove the second transparent electrode layer remaining in the outer peripheral region.
  • a photoresist is again coated on the base substrate 10, and a photoresist pattern is formed on the substrate by a exposure and development process using a mask.
  • a photoresist of a certain thickness is left in the pixel region, and the photoresist is not retained in the peripheral region.
  • the peripheral area refers to an area of the array substrate that is not used for effective display, and is usually wrapped around the display area.
  • Etching is performed using the formed photoresist pattern, such as wet etching.
  • Array substrate after etching The structure is shown in Figure 9.
  • Step 306 forming a via hole by etching using a via mask.
  • Vias i.e., vias, function to connect the gate metal layer, or the source/drain metal layer, to the peripheral lead regions.
  • the transparent electrode layer e.g., ITO layer
  • the connection is made by the connection between the transparent electrode layer and the gate metal layer, or the connection between the transparent electrode layer and the source/drain metal layer.
  • a photoresist is coated on the structure formed above, and then a photoresist pattern is formed on the base substrate by an exposure and development process using a via mask, wherein a photoresist of a certain thickness is retained in the display region. Then, for example, the transparent electrode layer of the peripheral region of the substrate is removed by wet etching, thereby forming a via hole, and the structure of the finally fabricated array substrate is as shown in FIG. 10; the via hole 4 is formed, for example, by the gate line 1 in the peripheral region. And at the end of the data line 2, a portion of the ends of the gate lines and the data lines can be connected to other leads.
  • the order of formation of the pixel electrode 5 and the common electrode 6 may be exchanged with each other; thus, in another example, the common electrode 6 is first formed as an example of the first transparent electrode of the present invention.
  • the pixel electrode 5 is thereafter formed as an example of the second transparent electrode of the present invention.
  • Embodiment 2 of the method of manufacturing an array substrate of the present invention comprises the following steps.
  • Step 401 sequentially perform a photolithography process on the base substrate to form a gate pattern, a semiconductor channel, and a source/drain pattern, and then deposit a first transparent electrode layer.
  • Fig. 11 shows the upper and lower rows of gate lines 1 formed on the base substrate 10, and each of the gate lines 1 is formed with a gate electrode 11; at this time, the gate electrode 11 is integrally formed with the corresponding gate line 1.
  • the source drain pattern includes a pattern of data lines, common electrode lines, and source and drain of the thin film transistor.
  • the data line 2 intersects the gate line 1 vertically; the common electrode line 15 is parallel to the data line 2, for example, a peripheral area outside the display area of the prepared array substrate.
  • the source 12 and the drain 13 of the thin film transistor are formed over the active layer (not shown) and opposed to each other, and the portion of the active layer between the source 12 and the drain 13 is a trench a track region 3 corresponding to the gate electrode 11; the active layer includes a patterned semiconductor layer film, a stack of doped semiconductor layer films; Line 2 is formed with the source 12 body.
  • a first transparent electrode layer (not shown) is deposited on the base substrate 10 on which the above structure is formed.
  • a layer of resin may be deposited prior to deposition of the first transparent electrode layer.
  • step 401 of the embodiment 2 are substantially the same as those of the step 301 of the embodiment 1 except for the formation of the common electrode line 15, and details are not described herein again.
  • Step 402 Exposing and developing the first transparent electrode layer and then the photoresist-coated base substrate by using a mask, and leaving a photoresist at a position where the pixel electrode is to be formed to form a photoresist pattern.
  • the steps, materials, parameters, and the like of the step 402 of the embodiment 2 are basically the same as the step 302 of the embodiment 1, and are not described herein again.
  • the position where the pixel electrode 5 is to be formed is covered with a photoresist 9, and the width of the photoresist 9 is slightly larger than the width of the pixel electrode 5 to be formed.
  • Step 403 etching a first transparent conductive layer on which a photoresist pattern is formed to form a pixel electrode.
  • step 403 of the embodiment 2 are substantially the same as those of the step 303 of the embodiment 1, and are not described herein again.
  • Step 404 sequentially depositing a protective layer and a second transparent electrode layer on the etched base substrate, and then performing stripping of the photoresist.
  • the steps, materials, parameters, and the like of the step 404 of the embodiment 2 are substantially the same as the step 304 of the embodiment 1, and are not described herein again.
  • the structure of the base substrate 10 on which the photoresist 9 and the protective layer deposited on the photoresist and the second transparent electrode layer are peeled off is as shown in FIG. A second transparent electrode layer 61 remaining in the peripheral region.
  • Step 405 exposing and etching again on the base substrate after stripping the photoresist to remove the second transparent electrode layer remaining in the outer peripheral region.
  • step 405 of the embodiment 2 are substantially the same as those of the step 305 of the embodiment 1, and are not described herein again.
  • Etching is performed using the formed photoresist pattern, such as wet etching.
  • the structure of the array substrate after etching is as shown in FIG. In a row of pixel units, the common electrodes 6 are connected to each other, and are directly overlapped with the common electrode line 15 at the position 42 in the peripheral region, thereby being electrically connected. That is, the common electrode 6 is not connected to the common electrode line 15 through the via hole.
  • the pixel electrode 5 is also directly connected to the drain 13 of the thin film transistor. Directly lap, thus electrically connected. That is, the pixel electrode 5 is not connected to the drain electrode 13 through the via hole. Step 406, forming a via hole by etching using a via mask.
  • the steps, materials, parameters, and the like of the step 406 of the embodiment 2 are substantially the same as those of the step 306 of the embodiment 1, and are not described herein again.
  • the structure of the finally fabricated array substrate is as shown in FIG. 16; the via 4 is formed, for example, over the ends of the gate lines 1 and the data lines 2 in the peripheral region, so that a part of the ends of the gate lines and the data lines can be combined with other The bow I line is connected.
  • the order of formation of the pixel electrode 5 and the common electrode 6 may be exchanged with each other; thus, in another example, the common electrode 6 is first formed as an example of the first transparent electrode, the pixel electrode An example of thus forming as the second transparent electrode is formed after 5.
  • Embodiments of the present invention also provide an array substrate, which is an array substrate fabricated by the above method.
  • the array substrate is, for example, an IPS type array substrate.
  • Embodiments of the present invention also provide a display device including the array substrate as described above.
  • the display device include a liquid crystal display device, an electronic paper display device, an organic light emitting display (OLED) device, etc., which can be used for any display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • OLED organic light emitting display
  • an example of the display device is a liquid crystal display device.
  • the liquid crystal display device may further include an opposite substrate disposed opposite to the array substrate to form a liquid crystal cell filled with a liquid crystal for display.
  • the liquid crystal layer is sandwiched between the array substrate and the opposite substrate.
  • the opposite substrate is, for example, a color filter substrate.
  • the method of the embodiment of the present invention forms the pattern of the pixel electrode and the common electrode of the array substrate display region in the same photolithography process, avoiding the Mura problem caused by the dislocation of the pixel electrode and the common electrode, and ensuring the array of the wide viewing angle mode.
  • the substrate displays the uniformity of the picture, especially the display picture uniformity of the large-sized panel.
  • the structures in the above embodiments of the present invention are merely exemplary, and the order of the film layers in the display region may be varied in many ways, as long as the necessary elements for panel driving (such as gate, source, drain, and pixel electrodes) are fabricated. , make sure the panel is driven normally. For example, first, a common electrode and a pixel electrode layer are fabricated, and then a gate electrode, a source/drain electrode, and the like are formed. As long as the pixel electrode can be connected to the drain electrode by a certain method, the via hole connection or the direct connection can be directly connected. The specific connection method is here. No longer.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板及其制作方法、显示装置，所述方法包括：利用掩模板对沉积有透明电极层和光刻胶的基板进行曝光，在所述透明电极的像素位置保留有光刻胶，形成光刻胶花样；对形成光刻胶花样的基板进行刻蚀；在刻蚀后的基板上沉积透明电极层，然后进行光刻胶的剥离。在阵列基板在制造过程中，通过将阵列基板显示区域的像素电极和公共电极的花样在同一次光刻中形成，避免了像素电极和公共电极错位引起的显示画面不均匀（Mura）问题，保证了广视角模式的阵列基板显示画面的均匀性，尤其是大尺寸面板的显示画面均匀性。

Description

阵列基板及其制作方法、 显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、 显示装置。 背景技术
薄膜场效应晶体管液晶显示（ TFT-LCD, Thin Film Transis-Liquid Crystal Display )技术， 主要分为扭曲向列（ Twist Nematic , ΤΝ )模式和广视角模式。 ΤΝ模式的 TFT-LCD中，在液晶层两侧的电极分别位于彩膜基板和阵列基板 上， 且都分别在一个平面中； ΤΝ模式的彩膜基板和阵列基板的结构也相对 简单。 广视角模式包括为横向电场显示技术， 例如面内切换 （ In Panel Switching, IPS )模式， 其通过透明指状电极的组合， 可以形成更合理的平面 电场， 优化液晶分子的排列； 同时由于使用透明电极代替了不透明的金属电 极， 明显提高了透光率。
一种传统的 IPS广视角模式的阵列基板的结构如图 1所示。 所述阵列基 板包括： 多条栅线 1、 多条数据线 2和至少一条公共电极线 15。 公共电极线 15平行于数据线 2。 多条栅线 1和多条数据线 2彼此交叉以界定了多个像素 单元， 每个像素单元包括作为开关元件的薄膜晶体管、 像素电极 5和公共电 极 6, 薄膜晶体管与像素电极 5连接。 薄膜晶体管包括栅极 11、 源极 12、 漏 极 13、 半导体沟道 3。 一行像素单元的公共电极 6的端部通过公共电极 15 上方的过孔 41与公共电极线 15电连接。 在栅线 1的端部上方的绝缘层中形 成有过孔 4, 用于与驱动电路等电连接。 每个像素单元之中， 像素电极 5和 公共电极 6都为梳状电极， 它们的指状部分交叉组合， 当它们彼此通电后形 成电场用于驱动液晶。
广视角模式的阵列基板由于像素电极和公共电极之间的间距太近， 两层 电极间微小的偏移就可能导致像素电极和公共电极之间的电容产生差异， 从 而引起显示画面不均匀 （Mura ) 的问题。
图 2示出了传统的 IPS广视角模式阵列基板像素电极 5和公共电极 6发 生错位的阵列基板结构示意。 如图 2所示， 在一个像素单元之中， 公共电极 6的指状部分相对于像素电极 5的指状部分向右偏移。 发明内容
本发明的实施例致力于提供一种阵列基板及其制作方法、 显示装置， 以 避免像素电极和公共电极错位引起的 Mura问题。
本发明的一个实施例提供了一种阵列基板制作方法， 所述方法包括： 在 基底基板上沉积第一透明电极层， 在所述透明电极层上涂覆第一光刻胶， 将 所述第一光刻胶进行曝光、 显影， 在将形成第一透明电极的位置保留所述第 一光刻胶， 由此形成第一光刻胶图形； 使用所述第一光刻胶图形对所述第一 透明电极层进行刻蚀， 形成第一透明电极； 在刻蚀后的基底基板上沉积第二 透明电极层， 然后对所述第一光刻胶图形进行光刻胶剥离， 由此除去所述第 一光刻胶图形上的所述第二透明电极层的部分， 形成第二透明电极。
本发明的另一个实施例提供了一种阵列基板， 所述阵列基板是利用如上 所述方法制作得到的阵列基板。
本发明的再一个实施例提供了一种显示装置， 所述显示装置包括如上所 述的阵列基板。 附图说明
为了更清楚地说明本发明实施例的技术方案， 下面将对实施例的附图作 简单地介绍，显而易见地，下面描述中的附图仅仅涉及本发明的一些实施例， 而非对本发明的限制。
图 1为传统的 IPS广视角模式阵列基板的结构示意图；
图 2为传统的 IPS广视角模式阵列基板像素电极和公共电极错位时的结 构示意图；
图 3为实施例 1的制造阵列基板过程中形成栅极图形后的示意图； 图 4为实施例 1的制造阵列基板过程中在图 3所示阵列基板基础上形成 半导体沟道和源漏极图形后的示意图；
图 5为实施例 1的阵列基板制造方法中形成光刻胶图形后的示意图； 图 6为图 5所示阵列基板刻蚀后 A-A位置的断面结构示意图；
图 7为图 5所示的阵列基板刻蚀后进行保护层和 ITO层沉积后 A-A位置 的断面结构示意图；
图 8为图 7所示阵列基板进行光刻胶剥离后的结构示意图；
图 9为图 8所示阵列基板进行去除外围区透明电极层的结构示意图。 图 10为实施例 1 的阵列基板制造方法最终制得的阵列基板的结构示意 图；
图 11为实施例 2的制造阵列基板过程中形成栅极图形后的示意图； 图 12为实施例 2的制造阵列基板过程中在图 11所示阵列基板基础上形 成半导体沟道和源漏极图形后的示意图；
图 13为实施例 2的阵列基板制造方法中形成光刻胶图形后的示意图； 图 14为图 13所示阵列基板进行光刻胶剥离后的结构示意图；
图 15为图 14所示阵列基板进行去除外围区透明电极层的结构示意图。 图 16为实施例 2的阵列基板制造方法最终制得的阵列基板的结构示意 图。 具体实施方式
为使本发明实施例的目的、 技术方案和优点更加清楚， 下面将结合本发 明实施例的附图，对本发明实施例的技术方案进行清楚、 完整地描述。显然， 所描述的实施例是本发明的一部分实施例， 而不是全部的实施例。 基于所描 述的本发明的实施例， 本领域普通技术人员在无需创造性劳动的前提下所获 得的所有其他实施例， 都属于本发明保护的范围。
本发明实施例的阵列基板包括多条栅线和多条数据线， 这些栅线和数据 线彼此交叉由此限定了排列为矩阵的像素单元， 每个像素单元包括作为开关 元件的薄膜晶体管和用于控制液晶的排列的像素电极和公共电极。 每个像素 的薄膜晶体管的栅极与相应的栅线电连接或一体形成， 源极与相应的数据线 电连接或一体形成， 漏极与相应的像素电极电连接或一体形成。 在下面的描 述中， 主要针对单个或多个像素单元进行， 但是其他像素单元可以相同地形 成。
实施例 1
本发明的阵列基板制造方法的实施例 1包括下述步骤。
步骤 301 , 对基底基板依次进行光刻工艺， 形成栅极图形、 半导体沟道 和源漏极图形， 之后沉积第一透明电极层。
本步骤中， 在基底基板上形成栅极图形的过程例如如下。
首先， 釆用溅射或者热蒸发的方法在基底基板 10 上沉积厚度例如为 500A ~ 4000A的栅金属薄膜（未示出 )。栅金属薄膜的材料可以选用 Cr、 W、 Ti、 Ta、 Mo、 Al、 Cu等金属、 合金或者由多层金属组成的栅金属层。 基底 基板 10可以选用玻璃或塑料基板。
然后， 在所述栅金属薄膜上涂覆光刻胶（未示出） ， 釆用掩模板对光刻 胶进行曝光后再显影以得到光刻胶图形， 接着使用得到的光刻胶图形作为刻 蚀掩模对栅金属薄膜进行刻蚀。 在刻蚀掉无光刻胶区域的栅金属薄膜后， 进 行光刻胶去除， 得到如图 3所示的栅极图形。 图 3示出了形成在基底基板上 的上、 下两行栅线 1 , 每条栅线 1上形成有栅极 11 ; 此时， 栅极 11与对应的 栅线 1一体形成。
形成栅极图形后， 进行半导体沟道和源漏极图形的制作例如包括如下步 骤。 本实施例中源漏极图形包括数据线和薄膜晶体管的源极与漏极的图形。
在形成图 3所示的栅极图形的基底基板 10上连续沉积栅绝缘层薄膜、半 导体层薄膜、 掺杂半导体层薄膜和源漏金属薄膜（未示出） ， 从而得到这些 薄膜的叠层。 在叠层顶部的所述源漏金属薄膜上涂覆光刻胶， 并釆用双色调 掩模板对光刻胶进行曝光显影， 接着进行刻蚀， 刻蚀掉无光刻胶区域的半导 体层薄膜、 掺杂半导体层薄膜和源漏金属薄膜。
然后对光刻胶进行灰化减薄， 接着用干法刻蚀的方法， 刻蚀掉薄膜晶体 管的沟道位置的半导体层， 之后进行光刻胶去除， 形成半导体沟道与源漏极 图形。 此时， 阵列基板的结构如图 4所示。 如图 4所示， 数据线 2与栅线 1 垂直相交； 源极 12和漏极 13形成在有源层（未示出）之上并且彼此相对， 有源层在源极 12和漏极 13之间的部分为沟道区域 3 , 与栅极 11相对应； 有 源层包括图案化的半导体层薄膜、 掺杂半导体层薄膜的叠层； 数据线 2与源 极 12—体形成。
然后， 在形成有上述结构的基底基板 10 上沉积第一透明电极层（未示 出） 。
或者， 在另一个示例中， 该步骤 301还可以为在所述基底基板上依次进 行光刻工艺， 形成栅极图形、 半导体沟道和源漏极图形， 然后沉积一层树脂 层和第一透明电极层。 即， 在沉积第一透明电极层之前， 先沉积一层一定厚 度的树脂层， 该厚度例如为 1~3微米， 较佳地， 可以设置为 2微米。 在该示 例中， 通过沉积树脂层， 可以减小像素电极与栅线之间的电容， 可以将像素 电极和公共电极的区域增大， 以增大开口率。
步骤 302, 利用掩模板对沉积有第一透明电极层和然后涂覆有光刻胶的 基底基板进行曝光和显影， 在待形成像素电极的位置保留有光刻胶， 形成用 于像素电极的光刻胶图形。
例如， 上一步骤中， 已在整个基底基板上沉积了第一透明电极层， 常用 的透明导电材料为铟锡金属氧化物（Indium Tin Oxides, ITO )或铟辞氧化物 ( Indium Zinc Oxides, IZO ) , 其厚度例如在 100人至 1000人之间； 例如 ITO 为纳米 ITO材料。 用掩模板通过曝光、 显影工艺， 将形成在第一透明导电层 上的光刻胶形成光刻胶图形， 其中， 在像素单元中透明的像素电极的位置保 留一定厚度的光刻胶， 如图 5所示。 在图 5中， 将要形成像素电极 5的位置 的上方覆盖有光刻胶 9, 且所述光刻胶 9的宽度要略大于将要形成的像素电 极 5的宽度。
步骤 303 , 对其上形成有光刻胶图形的第一透明导电层进行刻蚀， 形成 像素电极。
例如， 可以用化学方法对所述基底基板上的第一透明导电层进行刻蚀， 所使用的酸性蚀刻液可以是一定浓度的硫酸、 硝酸、 醋酸及混合酸， 刻蚀出 用于像素电极的透明电极的图形。 在刻蚀后， 沿图 5所标的线 A-A位置的断 面结构如图 6所示。 像素电极 5的形状在此形成。 像素电极 5为本发明的第 一透明电极的示例。所形成的像素电极 5的一部分搭接在漏极 13之上，从而 实现二者之间的电连接。
例如， 通过控制刻蚀的时间、 温度、 刻蚀液浓度等工艺参数等因素保证 一定的过刻， 使得光刻胶图形 9下方的像素电极 5相对于其上的光刻胶图形 9具有一定程度的缩进 R (如图 6所示），该过刻后的缩进量例如大约为 2~10 微米。 图 6中， 所得到的像素电极 5形成于栅极绝缘层 7上。 可以根据需要 适当调节过刻量以达到想要的间距。 该过刻工艺可以进一步保证在像素电极 和之后形成的公共电极之间形成缝隙， 得到均一的狭缝宽度。 由此， 在像素 电极和公共电极之间可形成均一的平行电场， 这避免了液晶显示器的显示画 面的亮暗不均的问题。
步骤 304, 在刻蚀后的基底基板上依次沉积保护层和第二透明电极层， 然后进行光刻胶的剥离。
在具有图 6所示断面图的玻璃基板 10上依次沉积保护层与第二层透明电 极层（未示出） ， 即在未去除光刻胶图形 9的情形下沉积保护层与该第二透 明电极层。 该第二透明电极层的透明导电材料与第一透明电极层的相同或不 同， 例如为 ITO材料。
图 7 示出了在图 5 所示的结构上进行保护层和第二透明电极层沉积后 A-A位置的断面结构示意。 由图 7可知， 在像素电极 5的上方为光刻胶图形 9,在光刻胶图形 9的上方依次为保护层 8和第二透明电极层。该第二透明电 极层用于形成公共电极 6; 同时， 保护层 8和第二透明电极层还沉积在了两 个像素电极 5之间的缝隙处。 保护层 8通常为氮化硅层， 为绝缘且耐腐蚀材 料， 所以可以有效的防止栅极金属层与源漏极金属层受到腐蚀。 在另一示例 中， 保护层 8也可以省去， 不影响电场的均一性。 由于 ITO为耐腐蚀材料， 所以其上方的保护层可以省去。 另外， 由于氮化硅层为绝缘材料所以不影响 其周围电场， 所以， 无保护层 8对电压驱动液晶的偏转无影响。
然后对具有图 7所示断面图的阵列基板进行光刻胶剥离。 应当理解， 此 处进行光刻胶剥离时，例如是将光刻胶 9以及沉积于光刻胶上面的保护层 8、 第二透明电极层同时进行剥离，剥离后基底基板 10上的结构如图 8所示。此 时， 在基底基板的外围， 如栅线 1和数据线 2的外侧具有残留的第二透明电 极层 61 (阴影部分）。 公共电极 6的形状在此已经形成。 该公共电极 6为本 发明的第二透明电极的示例。 像素电极 5和公共电极 6都为梳状电极， 它们 的指状部分彼此交错， 之间保留有狭缝。
步骤 305, 在剥离光刻胶后的基底基板上再次进行曝光、 刻蚀， 去除外 围区残留的第二透明电极层。
在基底基板 10上再次涂覆光刻胶， 用掩模板通过曝光、显影工艺， 在基 板上形成光刻胶图形。 在像素区域保留一定厚度的光刻胶， 在外围区域不保 留光刻胶。 这里， 外围区域是指阵列基板中非用于有效显示的区域， 通常围 绕在显示区域的周围。
使用所形成的光刻胶图形进行刻蚀， 例如湿法刻蚀。 刻蚀后阵列基板的 结构如图 9所示。
步骤 306, 利用过孔掩模板通过刻蚀形成过孔。
过孔， 即通孔， 起到将栅极金属层， 或者源漏极金属层连接到外围的引 线区的作用。 例如通过过孔使透明电极层（例如 ITO层）与下方的栅极金属 层， 或源漏极金属层连接在一起。 连接的方式为透明电极层与栅极金属层之 间的连接， 或者为透明电极层与源漏极金属层之间的连接。
在上述形成的结构上涂覆一层光刻胶， 然后用过孔掩模板通过曝光、 显 影工艺， 在基底基板上形成光刻胶图形， 其中， 在显示区域保留一定厚度的 光刻胶。 然后， 例如用湿法刻蚀去除基板外围区域的透明电极层， 由此形成 过孔，最终制造得到的阵列基板的结构如图 10所示； 过孔 4例如形成在外围 区域中的栅线 1和数据线 2的端部上， 使得栅线和数据线的端部的一部分可 与其他引线相连接。
在本实施例的上述方法之中， 像素电极 5和公共电极 6的形成顺序可以 彼此交换； 由此， 在另一个示例中， 公共电极 6先形成由此作为本发明的第 一透明电极的示例， 像素电极 5后形成由此作为本发明的第二透明电极的示 例。
实施例 2
本发明的阵列基板制造方法的实施例 2包括下述步骤。
步骤 401 , 对基底基板依次进行光刻工艺， 形成栅极图形、 半导体沟道 和源漏极图形， 之后沉积第一透明电极层。
图 11示出了形成基底基板 10上的上、 下两行栅线 1 , 每条栅线 1上形 成有栅极 11; 此时， 栅极 11与对应的栅线 1一体形成。
本步骤中， 在基底基板上形成栅极图形之后， 制备半导体沟道和源漏极 图形， 由此所得到的阵列基板的结构如图 12所示。本实施例之中， 源漏极图 形包括数据线、 公共电极线和薄膜晶体管的源极、 漏极的图形。
如图 12所示， 数据线 2与栅线 1垂直相交； 公共电极线 15平行于数据 线 2, 例如位于制备的阵列基板的显示区域之外的外围区域。 每个像素单元 之中， 薄膜晶体管的源极 12和漏极 13形成在有源层（未示出 )之上并且彼 此相对， 有源层在源极 12和漏极 13之间的部分为沟道区域 3, 与栅极 11相 对应； 有源层包括图案化的半导体层薄膜、 掺杂半导体层薄膜的叠层； 数据 线 2与源极 12—体形成。
然后， 在形成有上述结构的基底基板 10 上沉积第一透明电极层（未示 出） 。 或者， 在另一个示例中， 可以先沉积一层树脂层， 然后再沉积第一透 明电极层。
除了形成公共电极线 15之外， 实施例 2的步骤 401的步骤、材料、参数 等基本上与实施例 1的步骤 301相同， 在此不再赘述。
步骤 402, 利用掩模板对沉积有第一透明电极层和然后涂覆有光刻胶的 基底基板进行曝光和显影， 在待形成像素电极的位置保留有光刻胶， 形成光 刻胶图形。
实施例 2的步骤 402的步骤、材料、参数等基本上与实施例 1的步骤 302 相同，在此不再赘述。如图 13所示，将要形成像素电极 5的位置的上方覆盖 有光刻胶 9,且所述光刻胶 9的宽度要略大于将要形成的像素电极 5的宽度。
步骤 403 , 对其上形成有光刻胶图形的第一透明导电层进行刻蚀， 形成 像素电极。
实施例 2的步骤 403的步骤、材料、参数等基本上与实施例 1的步骤 303 相同， 在此不再赘述。
步骤 404, 在刻蚀后的基底基板上依次沉积保护层和第二透明电极层， 然后进行光刻胶的剥离。
实施例 2的步骤 404的步骤、材料、参数等基本上与实施例 1的步骤 304 相同， 在此不再赘述。 将光刻胶 9以及沉积于光刻胶上面的保护层、 第二透 明电极层进行剥离后的基底基板 10上的结构如图 14所示。 外围区域中残留 的第二透明电极层 61。
步骤 405 , 在剥离光刻胶后的基底基板上再次进行曝光、 刻蚀， 去除外 围区残留的第二透明电极层。
实施例 2的步骤 405的步骤、材料、参数等基本上与实施例 1的步骤 305 相同， 在此不再赘述。 使用所形成的光刻胶图形进行刻蚀， 例如湿法刻蚀。 刻蚀后阵列基板的结构如图 15所示。在一行像素单元中，公共电极 6彼此相 连， 并且在外围区域与公共电极线 15在位置 42直接搭接，从而电连接。 即， 公共电极 6没有通过过孔与公共电极线 15连接。
同样， 在每个像素单元之中， 像素电极 5也直接与薄膜晶体管的漏极 13 直接搭接， 从而电连接。 即， 像素电极 5没有通过过孔与漏极 13连接。 步骤 406, 利用过孔掩模板通过刻蚀形成过孔。
实施例 2的步骤 406的步骤、材料、参数等基本上与实施例 1的步骤 306 相同， 在此不再赘述。 最终制造得到的阵列基板的结构如图 16所示； 过孔 4 例如形成在外围区域中的栅线 1和数据线 2的端部上方， 使得栅线和数据线 的端部的一部分可与其他弓 I线相连接。
在本实施例的上述方法之中， 像素电极 5和公共电极 6的形成顺序可以 彼此交换； 由此， 在另一个示例中， 公共电极 6先形成由此作为第一透明电 极的示例， 像素电极 5后形成由此作为第二透明电极的示例。
本发明的实施例还提供了一种阵列基板， 所述阵列基板是利用上述方法 制作得到的阵列基板。 该阵列基板例如为 IPS型阵列基板。
本发明实施例还提供了一种显示装置， 该显示装置包括有如上所述的阵 列基板。 该显示装置的示例包括液晶显示装置、 电子纸显示装置、 有机发光 显示 （OLED )装置等， 可以用于手机、 平板电脑、 电视机、 显示器、 笔记 本电脑、 数码相框、 导航仪等任何需要显示功能的产品或部件。
例如， 该显示装置的一个示例为液晶显示装置， 该液晶显示装置还可以 包括对向基板， 与所述阵列基板相对设置以形成液晶盒（cell ) , 液晶盒中填 充有用于显示液晶， 由此液晶层夹置在阵列基板和对向基板之间。 该对向基 板例如为彩色滤光片基板。
本发明的实施例的方法通过将阵列基板显示区域的像素电极和公共电极 的图形在同一次光刻工艺中形成， 避免了像素电极和公共电极错位引起的 Mura问题，保证了广视角模式的阵列基板显示画面的均匀性，尤其是大尺寸 面板的显示画面均匀性。
本发明上述实施例中的结构仅仅是示例性的， 而显示区域的膜层顺序可 以有很多种变化， 只要制作出面板驱动必要的元素（比如栅极、 源极、 漏极 和像素电极等） ， 确保面板正常驱动即可。 比如先制作公共电极、 像素电极 层， 然后制作栅极、 源漏电极等， 只要可以将像素电极通过一定方法和漏电 极连接即可， 可以过孔连接也可以直接搭接， 具体连接方式在此不再赘述。
以上所述， 仅为本发明的较佳实施例而已， 并非用于限定本发明的保护 范围。 本发明的范围由所附的权利要求限定。

Claims

权利要求书
1、 一种阵列基板制作方法， 包括：
在基底基板上沉积第一透明电极层， 在所述透明电极层上涂覆第一光刻 胶， 将所述第一光刻胶进行曝光、 显影， 在将形成第一透明电极的位置保留 所述第一光刻胶， 由此形成第一光刻胶图形；
使用所述第一光刻胶图形对所述第一透明电极层进行刻蚀， 形成第一透 明电极；
在刻蚀后的基底基板上沉积第二透明电极层， 然后对所述第一光刻胶图 形进行光刻胶剥离， 由此除去所述第一光刻胶图形上的所述第二透明电极层 的部分， 形成第二透明电极。
2、根据权利要求 1所述的方法， 形成了所述第二透明电极之后， 所述方 法还包括：
在所述基底基板上再次涂覆第二光刻胶， 将所述第二光刻胶进行曝光、 显影， 形成第二光刻胶图形， 然后使用所述第二光刻胶图形进行刻蚀， 去除 像素区域之外的外围区中的第二透明电极层。
3、根据权利要求 2所述的方法，在去除所述外围区所述第二透明电极层 之后， 所述方法还包括：
在所述外围区域中通过刻蚀形成过孔。
4、根据权利要求 1所述的方法，在所述基底基板上沉积所述第二透明电 极层之前， 所述方法还包括： 在刻蚀以形成所述第一透明电极后的基底基板 上沉积保护层。
5、根据权利要求 1所述的方法，其中，在沉积所述第一透明电极层之前， 所述方法还包括：
在所述基底基板上依次形成栅极图形、 半导体沟道和源漏极图形。
6、根据权利要求 1所述的方法，其中，在沉积所述第一透明电极层之前， 所述方法还包括：
对所述基板依次进行光刻， 形成栅极图形、 半导体沟道和源漏极图形， 然后形成一树脂层， 在所述树脂层上沉积所述第一透明电极层。
7、根据权利要求 5所述的方法， 其中， 所述源漏极图形包括数据线、 公 共电极线、 以及薄膜晶体管的源极和漏极的图形。
8、根据权利要求 5所述的方法， 其中， 所述第一透明电极与所述第二透 明电极中之一为像素电极， 另一个为公共电极， 所述像素电极与所述薄膜晶 体管的漏极电连接。
9、根据权利要求 8所述的方法， 其中， 所述像素电极与所述薄膜晶体管 的漏极直接搭接。
10、 根据权利要求 8所述的方法， 其中， 所述公共电极与所述公共电极 线电连接。
11、根据权利要求 10所述的方法， 其中， 所述公共电极与所述公共电极 线直接搭接。
12、 根据权利要求 1所述的方法， 其中， 使用所述第一光刻胶图形对所 述第一透明导电层进行刻蚀为：
通过过刻使所述第一光刻胶图形下的第一透明电极缩进， 从而使所得到 的第一透明电极的宽度小于所述第一光刻胶图形的宽度。
13、 根据权利要求 12所述的方法， 其中， 所述缩进的量为 2~10微米。
14、根据权利要求 1所述的方法， 其中， 所述进行光刻胶剥离的方法为： 将所述第一光刻胶图形以及沉积于所述第一光刻胶上的第二透明电极层 同时剥离。
15、 一种阵列基板， 利用权利要求 1所述方法制作得到的阵列基板。
16、 一种显示装置， 包括阵列基板， 所述阵列基板为如权利要求 15所述 的阵列基板。
17、根据权利要求 16所述的显示装置，还包括： 对向基板和夹置在所述 阵列基板和所述对向基板之间的液晶层。
PCT/CN2012/080020 2011-08-12 2012-08-13 阵列基板及其制作方法、显示装置 WO2013023561A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/699,659 US9019462B2 (en) 2011-08-12 2012-08-13 Array substrate and method for manufacturing the same, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201110231958.8 2011-08-12
CN201110231958.8A CN102637634B (zh) 2011-08-12 2011-08-12 一种阵列基板及其制作方法、显示装置

Publications (1)

Publication Number Publication Date
WO2013023561A1 true WO2013023561A1 (zh) 2013-02-21

Family

ID=46621982

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2012/080020 WO2013023561A1 (zh) 2011-08-12 2012-08-13 阵列基板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US9019462B2 (zh)
CN (1) CN102637634B (zh)
WO (1) WO2013023561A1 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102629606B (zh) * 2011-09-26 2015-02-04 北京京东方光电科技有限公司 阵列基板及其制备方法和显示装置
CN102723308B (zh) * 2012-06-08 2014-09-24 京东方科技集团股份有限公司 一种阵列基板及其制作方法和显示装置
GB2521139B (en) * 2013-12-10 2017-11-08 Flexenable Ltd Reducing undesirable capacitive coupling in transistor devices
CN103676384A (zh) * 2013-12-26 2014-03-26 深圳市华星光电技术有限公司 Tft基板及用该tft基板的液晶显示面板
CN105511176B (zh) * 2016-01-29 2019-02-15 京东方科技集团股份有限公司 一种阵列基板的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655308A (zh) * 2004-12-30 2005-08-17 彩虹集团电子股份有限公司 一种平板显示屏的制作方法
CN101013240A (zh) * 2007-01-31 2007-08-08 友达光电股份有限公司 阵列基板的制作方法
CN101226316A (zh) * 2006-04-20 2008-07-23 友达光电股份有限公司 液晶显示器下基板的制作方法
US20100032672A1 (en) * 2008-08-11 2010-02-11 Chunghwa Picture Tubes, Ltd. Bonding pad, active device array substrate and liquid crystal display panel

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100807582B1 (ko) * 2001-07-30 2008-02-28 엘지.필립스 엘시디 주식회사 스토리지 커패시터 및 이를 구비한 액정 표시장치
JP4502575B2 (ja) * 2002-11-06 2010-07-14 奇美電子股▲ふん▼有限公司 表示装置の配線形成方法
KR100566816B1 (ko) * 2003-11-04 2006-04-03 엘지.필립스 엘시디 주식회사 수평 전계 인가형 박막 트랜지스터 기판 및 그 제조 방법
KR101085136B1 (ko) * 2004-12-04 2011-11-18 엘지디스플레이 주식회사 수평 전계 박막 트랜지스터 기판 및 그 제조 방법
KR101107245B1 (ko) * 2004-12-24 2012-01-25 엘지디스플레이 주식회사 수평 전계 박막 트랜지스터 기판 및 그 제조 방법
KR101288837B1 (ko) * 2006-06-29 2013-07-23 엘지디스플레이 주식회사 횡전계방식 액정표시소자 및 그 제조 방법
KR101201972B1 (ko) * 2006-06-30 2012-11-15 삼성디스플레이 주식회사 박막 트랜지스터 어레이 기판 및 이의 제조 방법
KR100920482B1 (ko) * 2006-11-28 2009-10-08 엘지디스플레이 주식회사 액정표시장치용 어레이 기판과 그 제조방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1655308A (zh) * 2004-12-30 2005-08-17 彩虹集团电子股份有限公司 一种平板显示屏的制作方法
CN101226316A (zh) * 2006-04-20 2008-07-23 友达光电股份有限公司 液晶显示器下基板的制作方法
CN101013240A (zh) * 2007-01-31 2007-08-08 友达光电股份有限公司 阵列基板的制作方法
US20100032672A1 (en) * 2008-08-11 2010-02-11 Chunghwa Picture Tubes, Ltd. Bonding pad, active device array substrate and liquid crystal display panel

Also Published As

Publication number Publication date
US20130114017A1 (en) 2013-05-09
CN102637634A (zh) 2012-08-15
US9019462B2 (en) 2015-04-28
CN102637634B (zh) 2014-02-26

Similar Documents

Publication Publication Date Title
KR101905757B1 (ko) 에프에프에스 방식 액정표시장치용 어레이기판 및 그 제조방법
JP5847061B2 (ja) アレイ基板及びその製造方法
US8933460B2 (en) Array substrate for fringe field switching mode liquid crystal display device
JP4619997B2 (ja) 液晶表示装置とその製造方法
JP4486554B2 (ja) 低分子有機半導体物質を利用する液晶表示装置及びその製造方法
JP4751305B2 (ja) 液晶表示装置用アレイ基板及びその製造方法
KR101217157B1 (ko) 액정표시장치용 어레이 기판 및 그 제조 방법
JP4932602B2 (ja) 多層薄膜パターン及び表示装置の製造方法
WO2017012306A1 (zh) 阵列基板的制备方法、阵列基板及显示装置
JP4238960B2 (ja) 薄膜トランジスタの製造方法
WO2013023561A1 (zh) 阵列基板及其制作方法、显示装置
US9268182B2 (en) Color filter substrate, TFT array substrate, manufacturing method of the same, and liquid crystal display panel
WO2014015617A1 (zh) 阵列基板及显示装置
WO2013143294A1 (zh) 阵列基板、其制作方法以及显示装置
US20070188682A1 (en) Method for manufacturing a display device
JP5525773B2 (ja) Ｔｆｔ基板及びその製造方法
KR101320651B1 (ko) 수평 전계 인가형 액정표시패널의 제조방법
KR20070072183A (ko) 액정표시소자 및 제조방법
KR101123452B1 (ko) 횡전계 방식 액정 표시 장치용 어레이 기판 및 그 제조 방법
KR101369571B1 (ko) 어레이 기판, 그 제조 방법 및 액정 디스플레이
KR101227408B1 (ko) 액정표시장치용 어레이 기판 및 그 제조방법
KR101490490B1 (ko) 박막 트랜지스터 표시판 및 그 제조 방법
KR20070072113A (ko) 액정표시소자 및 그 제조방법
JP6425676B2 (ja) 表示装置の製造方法
JP2024049705A (ja) アレイ基板の製造方法、アレイ基板、及び表示装置

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 13699659

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 12823822

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 12823822

Country of ref document: EP

Kind code of ref document: A1