WO2012176347A1 - 高耐圧集積回路装置 - Google Patents
高耐圧集積回路装置 Download PDFInfo
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- WO2012176347A1 WO2012176347A1 PCT/JP2011/070760 JP2011070760W WO2012176347A1 WO 2012176347 A1 WO2012176347 A1 WO 2012176347A1 JP 2011070760 W JP2011070760 W JP 2011070760W WO 2012176347 A1 WO2012176347 A1 WO 2012176347A1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Definitions
- the present invention relates to a high voltage integrated circuit device (HVIC) used when an on / off drive signal is transmitted to a gate of a switching power device, for example, in a PWM inverter, a switching power supply or the like. More particularly, the present invention relates to a high voltage integrated circuit device that prevents malfunction caused by an overcurrent that flows when a negative voltage surge is input into the circuit.
- HVIC high voltage integrated circuit device
- HVIC As a means for driving a switching power device that constitutes the upper arm of a bridge circuit for reverse power conversion (DC / AC conversion) such as a PWM inverter, an element isolation type HVIC using a high withstand voltage junction is used.
- HVIC has high function with overcurrent detection and temperature detection means when switching power device is abnormal, or downsizing and cost reduction of power supply system by not performing potential insulation by transformer, photocoupler, etc. Can be achieved.
- FIG. 9 is an explanatory diagram showing a connection example of a switching power device of a power conversion device such as an inverter and a conventional HVIC that drives the switching power device.
- FIG. 9 shows an example of a half bridge in which two switching power devices (in this case, IGBTs 114 and 115) are connected in series.
- the power conversion device shown in FIG. 9 alternately outputs a high potential or a low potential from the Vs terminal, which is the output terminal, by alternately turning on the IGBT 115 of the upper arm and the IGBT 114 of the lower arm, and AC to the L load 118 Electric power is supplied (AC current is flowing).
- the IGBT 114 and the IGBT 115 are operated so that the IGBT 115 of the upper arm is turned on and the IGBT 114 of the lower arm is turned off. Conversely, when outputting a low potential, the IGBT 114 and the IGBT 115 are operated so that the IGBT 115 of the upper arm is turned off and the IGBT 114 of the lower arm is turned on.
- the diodes connected in reverse parallel to the IGBTs 114 and 115 are FWD (Free Wheel Diode) 116 and 117.
- the gate signal to the IGBT 114 of the lower arm outputs a signal on the basis of GND
- the gate signal to the IGBT 115 of the upper arm outputs a signal on the basis of the Vs terminal.
- the HVIC 111 needs to have a level shift function.
- Vss is a high-potential side of a high-voltage power source that is a main circuit power source.
- GND is a ground (ground).
- Vs is an intermediate potential that varies from the Vss potential to the GND potential.
- H-VDD is the high potential side of the second low voltage power supply with Vs as a reference.
- L-VDD is the high potential side of the first low voltage power supply with respect to GND.
- the second low voltage power supply is made from the first low voltage power supply (L-VDD).
- Reference numeral 113 is a high-side power supply
- reference numeral 112 is a low-side power supply.
- H-IN is an input signal and an input terminal input to the gate of the low-side C-MOS circuit connected to the level-up circuit.
- L-IN is an input signal and an input terminal input to the gate of the low-side C-MOS circuit connected to the gate of the IGBT 114 of the lower arm.
- H-OUT is an output signal and output terminal of the high-side C-MOS circuit that outputs to the gate of the IGBT 115 of the upper arm.
- L-OUT is an output signal output to the gate of the lower arm IGBT 114 and an output terminal.
- ALM-IN is an input signal and an input terminal for the detection signal 119 when the temperature or overcurrent of the IGBT 115 of the upper arm is detected.
- ALM-OUT is an output signal and an output terminal of the detection signal leveled down.
- FIG. 10 and 11 are circuit diagrams showing the level shift circuit and its peripheral circuits inside the HVIC 111 shown in FIG.
- FIG. 10 is a circuit diagram including a level-up circuit
- FIG. 11 is a circuit diagram including a level-down circuit.
- reference numeral 120 denotes a terminal on the high potential side of the second low voltage power supply with Vs as a reference.
- p p-type
- n n-type.
- a peripheral circuit a low-side C-MOS circuit for transmitting an input signal of the level shift circuit and a high-side C-MOS circuit for transmitting an output signal of the level shift circuit to the IGBT 115 of the upper arm are shown. It was.
- the level-down circuit is composed of a p-channel MOSFET 43 and a level shift resistor 72.
- a diode 76 is connected in parallel to the level shift resistor.
- the ALM-IN signal is input to the gate of the C-MOS circuit of the high side circuit, and the output signal of the C-MOS circuit is input to the gate of the p-channel MOSFET 43 of the level down circuit.
- a low-side signal is output from the output unit 102 of the level-down circuit, and a signal level-down from the output of the C-MOS circuit of the low-side circuit is detected from the ALM-OUT as a detection signal. Output to the side.
- Switching power devices are widely used in many fields, such as inverters for motor control, large-capacity PDPs (plasma display panels), power supplies such as liquid crystal panels, and inverters for home appliances such as air conditioners and lighting.
- the HVIC Vs terminal and H-VDD terminal are affected by the parasitic inductance component and the like due to the wiring on the printed circuit board and the cable up to the load. Due to this parasitic inductance component, the Vs terminal and the H-VDD terminal of the HVIC 111 are on the negative potential side with respect to the ground (GND terminal in FIG. 9) when the upper arm IGBT 115 is turned off or when the lower arm IGBT 114 is turned on. Fluctuate. This variation causes a malfunction of the high-side circuit and element destruction due to latch-up.
- FIG. 12 is a detailed diagram of a level shift circuit diagram of a conventional HVIC.
- 12A is a level-up circuit diagram
- FIG. 12B is a level-down circuit diagram.
- the level-up circuit shown in FIG. 12A includes a level shift resistor 71 and an n-channel MOSFET 41 to which the level shift resistor 71 and the drain are connected, and the connection between the level shift resistor 71 and the n-channel MOSFET 41 is leveled up.
- the circuit is configured as an output unit 101.
- a diode 75 is connected to the resistor 71 in parallel.
- the diode 75 has a function of preventing an excessive voltage from being applied to the gate of the MOSFET of the C-MOS circuit of the high side circuit.
- a Zener diode is frequently used as the diode 75.
- the n-channel MOSFET 41 includes a body diode 42 in antiparallel.
- the level down circuit shown in FIG. 12B includes a drain of the p-channel MOSFET 43 and a level shift resistor 72 connected to the drain, and the connection between the level shift resistor 72 and the p-channel MOSFET 43 is connected to the level down circuit.
- the output unit 102 is configured.
- a diode 76 is connected in parallel to the level shift resistor 72 in order to prevent the level shift resistor 72 from being destroyed when the H-VDD becomes significantly lower than the GND potential. Further, when an overvoltage is applied to H-VDD when the p-channel MOSFET 43 is on, the diode 76 has a function of preventing an overvoltage from being applied to the gate of the MOSFET of the C-MOS circuit of the low side circuit.
- a body diode 44 is connected to the p-channel MOSFET 43 in antiparallel.
- FIG. 13 is a cross-sectional view showing a main part of a high-side circuit and a low-side circuit of a conventional self-isolation type high-voltage integrated circuit device 500, a level-up circuit part, and main parts of a high-voltage junction termination region (HVJT). is there.
- reference symbols a to j in FIG. 13 denote electrodes formed on each region.
- Reference numeral 21 denotes a p offset region.
- Reference numerals 22 to 24, 26 to 28, 32 to 34, and 36 to 38 are regions serving as a source, a drain, and a contact.
- Reference numerals 25, 29, 35 and 39 denote gate electrodes.
- an n-well region 2 and an n-well region 3 are formed in the surface layer of the p semiconductor substrate 1 connected to the GND potential.
- a low-side circuit C-MOS circuit or the like is formed in the n-well region 2.
- a level shift circuit, a C-MOS circuit of a high side circuit, and the like are formed in the n well region 3.
- the n-channel MOSFET 41 for level shift includes an n ⁇ well region 4, a p region 51 in contact with the n ⁇ well region 4, an n source region 53 and a p contact region 54 formed in the surface layer of the p region 51, n - with the n drain region 52 formed on the surface layer of the well region 4, and a gate electrode 55 formed via a gate oxide film on the n source region 53 and p region 51 sandwiched between the n drain region 52 ing.
- the drain region 52 of the n-channel MOSFET 41 is connected to H-VDD via a level shift resistor 71 by a surface metal wiring.
- the connection part between the drain region 52 of the n-channel MOSFET 41 and the level shift resistor 71 is used as the output part 101 of the level-up circuit.
- the output unit 101 outputs a low potential when the level-up n-channel MOSFET 41 is turned on, and outputs a high potential when the level-up n-channel MOSFET 41 is turned off. Therefore, the high voltage integrated circuit device 500 can perform a level shift operation that is signal transmission between different reference potentials.
- V S L ⁇ dI / dt (1)
- V supply is a battery voltage across the high-side power supply 113 or a bootstrap capacitor (not shown), and V f is a forward voltage drop of the parasitic diodes 45 and 46.
- FIG. 14 is a layout diagram showing the main parts such as the high-side circuit and level shifter of FIG.
- the n-well region 3 that is a high potential region, an H-VDD pad, an H-OUT pad, a Vs pad, and an intermediate potential region are formed.
- the intermediate potential region is the p offset region 31 and the p drain region 34.
- an n-contact region 62 is formed in a band shape. On the n-contact region 62, first pickup electrodes 81 are scattered.
- An n ⁇ well region 4 is formed surrounding the n well region 3.
- a p region 61 is formed surrounding the n ⁇ well region 4.
- a p contact region 56 is formed in a band shape on the surface layer of the p region 61. On the p contact region 56, the second pickup electrodes 82 are scattered.
- An n well region 2 that is a low potential region is formed surrounding the p region 61. In this n-well region 2, the low side circuit shown in FIG.
- a level shifter is formed on the surface layer of the p region 51 sandwiched between the n contact region 62 and the p region 61.
- the n contact region 62 and the p region 61 and the n ⁇ well region 4 and the p region 51 sandwiched between these regions are high breakdown voltage junction termination regions.
- the p region 51 where the level shifter is formed and the n ⁇ well region 4 are in contact with each other.
- the location E adjacent to the n contact region 62 is a location where the intermediate potential region and the high breakdown voltage junction termination region face each other, and the intermediate potential region and the high breakdown voltage junction termination region are opposed to each other. This is the place where the distance W is minimized (hereinafter referred to as the facing place E).
- a high-voltage integrated circuit chip As such a high-voltage integrated circuit, a high-voltage integrated circuit chip, more specifically, a circuit for protecting a high-voltage integrated circuit that drives a half-bridge power transistor, at an output node (point)
- a high voltage integrated circuit chip having a resistor between a substrate and a ground for limiting a current during a negative voltage spike is disclosed (for example, see Patent Document 1 below), which is intended for a circuit that expects an excessive negative swing. .)
- a device for reducing the influence of reverse bias by inserting a diode between the drain electrode of the switching element belonging to the level shifter and the gate electrode of the MOS transistor belonging to the amplifier (C-MOS circuit) Is disclosed (for example, see Patent Document 2 below).
- the drain of the switching element belonging to the level shifter, the level shift resistor, and the current limiting resistor are connected in series, and the level shift resistor and the current limiting resistor are connected to the output unit of the level up circuit.
- the level shift resistor and the current limiting resistor are connected to the output unit of the level up circuit.
- a high voltage diode (D3) is provided between the common ground node (COM) and the virtual ground node (VS) in the high voltage control circuit (HVIC) using a common substrate region.
- the conventional high voltage integrated circuit device described above has the following problems.
- Vss is about 1200 V and H-VDD is about 15 V higher than Vs will be described.
- the upper arm IGBT 115 is in operation and the lower arm IGBT 114 is in an off operation, a current flows from the upper arm IGBT 115 to the L load 118.
- the L load 118 tries to maintain the current, so that the current flows from the GND via the FWD 116 of the lower arm, the potential of the Vs terminal becomes lower than the GND potential, and ⁇ 30V It also becomes a degree.
- the potential of the Vs terminal becomes about ⁇ 30V
- the potential of the H-VDD terminal becomes about ⁇ 15V.
- the p semiconductor substrate 1 and the p region 61 are at the GND potential.
- a case will be described in which the potential of the Vs terminal is lowered until both the n well region 3 and the n ⁇ well region 4 become lower than the GND potential.
- the parasitic diode 45 composed of the p semiconductor substrate 1 and the n well region 3 and the parasitic diode 46 composed of the p region 61 and the n ⁇ well region 4 are forward biased and a large current flows. This current flows through the capacitance between the gate and source of the IGBT 115. Since there is no resistance component that limits the current in this path, a very large pulse current is generated. This pulse current destroys the HVIC or causes a malfunction.
- the holes that have entered the n ⁇ well region 4 pass under the n contact region 62, and the p offset region 31 and the p drain region 36 (the gate electrode 39 has an ON signal) that are negative Vs potential regions. When it flows).
- the holes flowing into the p offset region 31 are extracted from the p contact region 38 to the Vs terminal.
- part of this hole also penetrates under the n source region 37 and becomes a gate current of a parasitic npn transistor composed of the n source region 37, the p offset region 31, and the n well region 3, and this parasitic npn transistor May turn on and cause the logic part of the high side circuit to malfunction.
- the holes that have also penetrated under the n source region 37 turn on (latched up) a parasitic thyristor composed of the n source region 37, the p offset region 31, the n well region 3 and the p semiconductor substrate 1, thereby causing a high side circuit. May be destroyed. Further, if some of the holes flow through the n-well region 3 to the p drain region 34, the logic part of the high side circuit may also malfunction.
- the resistor for limiting the current is connected between the GND (ground) terminal and the substrate, and the connection at other points is not mentioned. Since this resistor is formed of a polysilicon layer, when a pulse current having a large negative voltage (several A to several tens of A) flows transiently to a parasitic diode between the Vs terminal and the GND terminal, the polysilicon layer However, there is a risk of overmelting due to overcurrent and destruction.
- a current limiting resistor is connected to the path between the high potential side (H-VDD) and the low potential side (ground) of the Vs reference low voltage power supply of the level shift circuit.
- the present invention provides a high voltage integrated circuit device capable of preventing malfunction and destruction of a high side circuit when a negative voltage surge is applied to an H-VDD terminal or a Vs terminal in order to eliminate the above-mentioned problems caused by the prior art.
- the purpose is to do.
- a high voltage integrated circuit device is a high voltage semiconductor integrated circuit that drives a high potential side power transistor of two power transistors connected in series.
- the apparatus has the following characteristics.
- a second conductivity type high potential region formed in the surface layer of the first conductivity type semiconductor substrate, and a surface layer of the semiconductor substrate formed in contact with the high potential region and along the outer periphery of the high potential region A breakdown voltage region of a second conductivity type having an impurity concentration lower than that of the high potential region, and a ground layer formed on the surface layer of the semiconductor substrate in contact with the breakdown voltage region and along an outer periphery of the breakdown voltage region
- An intermediate potential region of the first conductivity type that is separated from the high potential region, a first contact region of the second conductivity type formed along the high potential region side end of the breakdown voltage region, and the ground The first contact is formed on the surface layer of the potential region.
- the intermediate potential region is a region to which an intermediate potential between the high potential side potential of the high voltage power source that is the main circuit power source of the two power transistors connected in series and the ground potential is applied.
- the low potential region is a region to which a high potential side potential of a first low voltage power supply with the ground potential as a reference is applied.
- the high potential region is a region to which a high potential side potential of a second low voltage power supply with the intermediate potential as a reference is applied.
- a high breakdown voltage junction termination region composed of the breakdown voltage region, the ground potential region, the first contact region, and the second contact region is formed.
- the resistance of the current path between the first pickup electrode and the second pickup electrode at the location of the high voltage junction termination region where the facing distance to the intermediate potential region is shorter than the other location is higher than at other locations.
- FIG. 15 is a diagram illustrating the relationship between the negative voltage surge and the distance from the contact region to the intermediate potential region.
- FIG. 15 shows the distance between the contact region 62 and the p-offset region 31 that is the intermediate potential region with respect to the guaranteed voltage when a negative voltage surge is applied in the configuration of the high voltage integrated circuit device shown in FIGS.
- the distance between the contact region 62 and the p offset region 31 needs to be 100 ⁇ m or more.
- a high voltage integrated circuit device is a high-voltage power transistor for driving a high-potential side power transistor of two power transistors connected in series.
- a breakdown voltage semiconductor integrated circuit device having the following characteristics.
- a second conductivity type high potential region formed in a surface layer of the first conductivity type semiconductor substrate; a first conductivity type isolation region that separates a part of the outer periphery of the high potential region; and a surface of the semiconductor substrate
- a second conductive type withstand voltage region having an impurity concentration lower than that of the high potential region formed in contact with the high potential region and along an outer periphery of the high potential region; and a surface layer of the semiconductor substrate.
- the second conductivity type low potential region, the first conductivity type intermediate potential region formed in the high potential region and separated from the high potential region, and the end portion of the breakdown voltage region on the high potential region side A first contact region formed along the line, and Comprising a second contact region formed on the surface layer of the land potential region, and a first pickup electrode in contact with the first contact region, and a second pickup electrode in contact with the second contact region.
- the intermediate potential region is a region to which an intermediate potential between the high potential side potential of the high voltage power source that is the main circuit power source of the two power transistors connected in series and the ground potential is applied.
- the low potential region is a region to which a high potential side potential of a first low voltage power supply with the ground potential as a reference is applied.
- the high potential region is a region to which a high potential side potential of a second low voltage power supply with the intermediate potential as a reference is applied.
- a high breakdown voltage junction termination region composed of the breakdown voltage region, the ground potential region, the first contact region, and the second contact region is formed. The resistance of the current path between the first pickup electrode and the second pickup electrode at the location of the high voltage junction termination region where the facing distance to the intermediate potential region is shorter than the other location is higher than at other locations.
- the first pickup electrode is formed except for the portion of the high voltage junction termination region in which the facing distance to the intermediate potential region is shorter than other portions.
- the resistance is higher than other portions.
- the second pickup electrode is formed except for the portion of the high voltage junction termination region where the facing distance to the intermediate potential region is shorter than other portions. By forming, the resistance is higher than other portions.
- the first contact region and the above in the location of the high voltage junction termination region where the facing distance to the intermediate potential region is shorter than other locations.
- Any one of the first pickup electrode or the second contact region and the second pickup electrode is electrically insulated so that the resistance is higher than that of other portions.
- the surface of the high voltage junction termination region is located at a location of the high voltage junction termination region where the facing distance to the intermediate potential region is shorter than other locations.
- the high voltage junction region is located in the low voltage region at the location of the high voltage junction termination region where the facing distance to the intermediate potential region is shorter than other locations. It is characterized in that the resistance is higher than the other parts by extending to the side.
- the high-voltage junction termination region having a short opposing distance with respect to the intermediate potential region is made to have a higher resistance than other portions, so that the injection of holes is locally reduced when a negative voltage surge is input. can do.
- the high voltage integrated circuit device of the present invention it is possible to prevent malfunction and destruction of the logic part of the high side circuit.
- FIG. 1 is a plan view showing a main part of a high voltage integrated circuit device according to a first embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing the main part of the whole when cut in a direction parallel to the cutting line AA in FIG.
- FIG. 3 is a plan view of the main part showing the flow of holes and electrons in the enlarged view of the F part in FIG.
- FIG. 4 is a cross-sectional view of the main part of the high voltage junction termination structure of FIG. 1 and its periphery.
- FIG. 5 is a plan view showing a main part of a high voltage integrated circuit device according to Embodiment 2 of the present invention.
- FIG. 6 is a cross-sectional view showing the main part of the high voltage integrated circuit device according to Embodiment 2 of the present invention.
- FIG. 7 is a plan view showing the main part of the high voltage integrated circuit device according to Embodiment 3 of the present invention.
- FIG. 8 is a cross-sectional view showing a main part of the high voltage integrated circuit device according to Embodiment 3 of the present invention.
- FIG. 9 is an explanatory diagram showing a connection example of a switching power device of a power conversion device such as an inverter and a conventional HVIC that drives the switching power device.
- FIG. 10 is a circuit diagram showing the level-up circuit and its peripheral circuits.
- FIG. 11 is a circuit diagram showing a level-down circuit and its peripheral circuits.
- FIG. 10 is a circuit diagram showing the level-up circuit and its peripheral circuits.
- FIG. 12 is a detailed diagram of a level shift circuit diagram of a conventional HVIC.
- FIG. 13 is a cross-sectional view showing a main part of a high-side circuit and a low-side circuit of a conventional self-isolation type high-voltage integrated circuit device, a logic part, a level-up circuit part, and a high-voltage junction termination region (HVJT). .
- FIG. 14 is a layout diagram showing the main parts such as the high-side circuit and level shifter of FIG.
- FIG. 15 is a diagram illustrating the relationship between the negative voltage surge and the distance from the contact region to the intermediate potential region.
- FIG. 16 is a plan view showing a main part of a high voltage integrated circuit device according to Embodiment 4 of the present invention.
- FIG. 17 is a cross-sectional view showing the main parts of the high voltage integrated circuit device according to Embodiment 4 of the present invention.
- FIG. 1 is a plan view showing a main part of a high voltage integrated circuit device 100 according to the first embodiment of the present invention.
- FIG. 2 is a cross-sectional view showing the main part of the whole when cut in a direction parallel to the cutting line AA in FIG. 1 and 2, the same reference numerals are given to the components corresponding to those shown in FIGS. 9 to 13.
- FIG. 3 is a plan view of the main part showing the flow of holes and electrons in the enlarged view of the F part in FIG. Note that a region indicated by an oblique dotted line is a portion (opposing portion) E in which a part of the intermediate potential region is disposed close to the n contact region 62, and a facing distance W to the intermediate potential region is larger than that of other portions. This is a short high-voltage junction termination region.
- FIG. 4 is a cross-sectional view of the main part of the high withstand voltage junction termination region in FIG. 1 and its periphery.
- FIG. 4A is a cross-sectional view of the main part showing the cross-sectional structure taken along the line AA in FIG.
- FIG. 4B is a cross-sectional view of the main part showing the cross-sectional structure taken along the line BB in FIG. 2 is the same as the cross-sectional view of FIG.
- the high side shown in FIG. 2 includes a high potential region to which a potential (H-VDD potential) on which the L-VDD potential is superimposed with the Vs potential as a reference potential is applied, and an intermediate potential region to which the Vs potential is applied. It is an area to include.
- the low side is a region including a low potential region to which the L-VDD potential is applied with GND as a reference potential and a ground potential region to which the GND potential is applied.
- the n-well region 3 is on the high side, and an H-VDD pad, an H-OUT pad, a Vs pad, and an intermediate potential region are formed on the n-well region 3. These pads serve as terminals in FIG.
- the intermediate potential region is the p offset region 31 and the p drain region 34.
- the p drain region 34 becomes a Vs potential when the nMOSFET 85 configured by the n source region 37 and the n drain region 36 shown in FIG. 2 is turned on, so that the p drain region 34 becomes an intermediate potential region.
- the pMOSFET 86 constituted by the p source region 33 and the p drain region 34 is turned on, so that it becomes a high potential region. That is, the p drain region 34 is either an intermediate potential region or a high potential region. In the present embodiment, the intermediate potential region is the p offset region 31 and the p drain region 34, but is not limited to these regions.
- the low potential regions are the p region 61, the p region 51 constituting the level shifter (NchMOSFET 41 shown in FIG. 2), and the p semiconductor substrate 1 shown in FIG.
- the n source region 53 of the Nch MOSFET 41 is formed in the surface layer of the p region 51.
- the n drain region of the Nch MOSFET 41 is the n ⁇ well region 4.
- the high withstand voltage junction termination region is the n ⁇ well region 4 and the p region 61 between the high concentration n contact region 62 and the high concentration p contact region 56.
- the n ⁇ well region 4 is a region that mainly extends the depletion layer when a reverse bias is applied to the pn junction with the p region 61, and is a breakdown voltage region.
- the n well region 2 is a low potential region. In the n-well region 2, an L-VDD terminal and an L-OUT terminal are formed.
- the ground potential region is a p region 61, and a GND terminal is formed in the p region 61.
- a strip-like n contact region 62 is formed on the surface layer so as to surround the n well region 3 and to straddle the n ⁇ well region 4 and the n well region 3.
- a strip-shaped first pickup electrode 81 is formed on the strip-shaped n contact region 62.
- the contact portions 81a between the first pickup electrodes 81 and the n contact regions 62 are scattered in ohmic contact.
- the contact part 81a may be strip-shaped.
- n ⁇ well region 4 surrounding the n well region 3 and connected to the n well region 3 is formed, and a p region 61 is formed surrounding the n ⁇ well region 4.
- the p region 61 is formed in a band shape, and a p contact region 56 is formed in a band shape on the surface layer of the p region 61.
- a band-shaped second pickup electrode 82 is formed on the band-shaped p contact region 56. Contact portions 82a between the second pickup electrodes 82 and the p contact regions 56 are scattered in ohmic contact.
- the contact part 82a may have a belt shape.
- n well region 2 which is a low potential region is formed in contact with the p region 61, and a low side circuit (low side shown in FIG. 2) is formed in the n well region 2.
- the p region 51 is a region where a level shifter is formed.
- the p region 51 is formed in the surface layer of the p semiconductor substrate 1 in contact with the n ⁇ well region 4 and overhanging the p region 61. However, in FIG. 1, it has shown so that the location overhanging may be touched.
- a first pickup electrode 81 connected to the H-VDD terminal and a second pickup electrode 82 connected to the GND terminal are formed on the n contact region 62 and the p contact region 56, respectively.
- the contact portions 81a and 82a of the first and second pickup electrodes 81 and 82 and the contact regions 62 and 56 are formed in a scattered manner as described above.
- the contact portions 81a and 82a may be formed in a band shape.
- the facing portion E of the high breakdown voltage junction termination region where the facing distance W to the intermediate potential region (here, the p offset region 31) is shorter than the other portions it is on the n contact region 62 and the p contact region 56.
- the first pickup electrode 81 and the second pickup electrode 82 are not arranged, respectively.
- the first and second pickup electrodes 81 and 82 may be disposed and the contact portions 81a and 82a may not be provided.
- an insulating film is sandwiched between the contact regions 56 and 62 and the first and second pickup electrodes 81 and 82 to eliminate the contact portions 81a and 82a.
- the end of the intermediate potential region (the end of the p offset region 31) and the end of the n contact region 62 are parallel to each other.
- the resistance between the first pickup electrode 81 and the second pickup electrode 82 is reduced at the opposing portion E of the high-voltage junction termination region where the opposing distance W to the intermediate potential region is shorter than the other locations. Can be higher than other places.
- the region between the intermediate potential region and the high withstand voltage junction termination region is shown in FIG.
- a region where no malfunction occurs due to a negative voltage such as the level shift resistor 71 and the diode 75 is formed. For this reason, holes that have entered the n ⁇ well region 4 when a negative voltage surge is input flow predominantly to regions other than the E region through the high withstand voltage junction termination region (other portions) having a low resistance value.
- the middle point between the opposing contact portions 82a of the n contact region 62 where the first pickup electrode 81 (contact portion 81a) is not formed is Z1, and the second pickup electrode 82 (contact portion 82a) is formed.
- Z2 be the midpoint between the contact portions 82a of the p contact region 56 that are not facing each other.
- the end where the first pickup electrode 81 is interrupted is Z3 (there are two locations on the left and right)
- the end where the second pickup electrode 82 is interrupted (the end of the connection portion 82a where the interruption occurs) Is Z4 (there are two places on the left and right).
- the electrons 84 flowing from Z1 to Z2 and the holes 83 flowing from Z2 to Z1 when a negative voltage surge is input will be described.
- the electrons 84 enter the n contact region 62 from the end Z3 where the first pickup electrode 81 (contact portion 81a) in FIG. 3 is interrupted. After flowing through the band-shaped n contact region 62 to Z1, the n ⁇ The well region 4 is entered. In the figure, only one path (solid line) is shown. Thereafter, the electrons 84 flow through the n ⁇ well region 4 toward Z2.
- the electrons 84 entering the n ⁇ well region 4 from the point Z1 flow through a long path along the band-shaped n contact region 62, so that the resistance increases and the amount of electrons 84 is greatly reduced.
- the second pickup electrode 81 at the opposite location E is in contact with the amount of electrons 84 entering the n ⁇ well region 4 from the n contact region 62 at locations other than the opposite location E where the first pickup electrode 81 is in contact.
- the amount of electrons 84 that enter the n ⁇ well region 4 from the n contact region 62 that is not present decreases.
- the hole 83 enters the p contact region 56 from the end Z4 where the second pickup electrode 82 (contact portion 82a) in FIG. 3 is interrupted, and flows through the band-shaped p contact region 61 to Z2, and then the p contact region 56. Enters n - well region 4. Only one path (dotted line) is shown in the figure. Thereafter, it flows through the n ⁇ well region 4 toward Z1.
- the resistance increases and the amount of the holes 83 decreases.
- both the amount of electrons 84 and the amount of holes 83 are decreased. That is, in this facing portion E, the resistance (electric resistance) of the current path between the first pickup electrode 81 and the second pickup electrode 82 is equivalent to the amount that the holes 83 and the electrons 84 flow along the band-shaped contact regions 56 and 62. Get higher. This is because the resistance of the current path between the first pick-up electrode 81 and the second pick-up electrode 82 is higher than that of the other part in the opposite part E of the high voltage junction termination region where the opposing distance W to the intermediate potential region is short. It means to become.
- the applied voltage of the negative voltage surge can be changed to another location.
- the depletion layer spreads in the band-shaped n contact region 62 or the band-shaped p contact region 56 at the opposite location E the applied voltage in the n ⁇ well region 4 is lowered, and the amount of injected holes 83 and electrons 84 are reduced. The amount decreases.
- the amount of electrons 84 flowing toward the p region 61 or the amount of holes 83 flowing toward the n contact region 62 at the opposite location E is increased. Decrease. This also reduces the amount of holes 83 or 84 that attempts to neutralize the electrons 84 or holes 83 based on the neutral principle of charge. That is, by disposing the first pickup electrode 81 or the second pickup electrode 82, the amount of holes 83 flowing into the n-well region 3 via the n ⁇ well region 4 or the amount of electrons 84 flowing into the p-region 61 is reduced. .
- the n well region 3 and the n ⁇ well region 4 which are high potential regions formed on the p semiconductor substrate 1 have, for example, phosphorus (P) with a dose amount of 1 ⁇ 10 13 / cm 2 to 2 ⁇ 10 13 / Ions are implanted at an impurity concentration of cm 2 , 1 ⁇ 10 12 / cm 2 to 2 ⁇ 10 12 / cm 2 , and then diffused to a predetermined diffusion depth by a diffusion process at a high temperature (about 1100 ° C. to 1200 ° C.). . Thereby, an n well region 3 and an n ⁇ well region 4 are formed.
- P phosphorus
- boron (B) is ion-implanted, it is diffused to a predetermined diffusion depth by a diffusion process at a high temperature (about 1100 to 1200 ° C.).
- a high-concentration n-contact region 62 for making ohmic contact with the H-VDD terminal is ion-implanted to a surface concentration of about 1 ⁇ 10 20 / cm 3 , for example, and then 750 ° C. to 900 ° C.
- the p region 61 is formed with a predetermined depth by an annealing process of about 0 ° C.
- a high concentration p contact region 56 for making ohmic contact with the GND terminal is ion-implanted with, for example, boron fluoride (BF 2 ) so as to have a surface concentration of about 1 ⁇ 10 20 / cm 3 .
- the p contact region 56 is formed at a predetermined depth by the subsequent annealing process at about 750 ° C. to 900 ° C.
- each electrode and each terminal are formed on the first and second pickup electrodes 81 and 82 and each region. Thereafter, the surface of the p semiconductor substrate 1 on which electrodes and terminals are formed is covered with a protective film (not shown).
- a pMOSFET 86 composed of a p source region 33 and a p drain region 34, an intermediate potential region and an n contact region 62 are arranged on the surface layer of the n well region 3 which is a high potential region. Is done.
- This intermediate potential region is a p offset region 31 and a p drain region 34.
- an nMOSFET 85 including an n source region 37 and an n drain region 36 is disposed on the surface layer of the p offset region 31, an nMOSFET 85 including an n source region 37 and an n drain region 36 is disposed.
- the p drain region 34 becomes an intermediate potential region.
- a C-MOS circuit composed of a pMOSFET 86 and an nMOSFET 85 is formed in the n-well region 3 and becomes a high-side logic unit.
- the first region is located on the n contact region 62 and the p contact region 56 in the high breakdown voltage junction termination region at the facing portion E where the facing distance W is short.
- the facing portion E can have a higher resistance than other portions.
- the p region 61 and the n ⁇ well region 4 are continuous even at a location where the first pickup electrode 81 and the second pickup electrode 82 are not disposed (or an insulating film is formed and the contact portions 81a and 82a are not provided). It is connected to. For this reason, the influence on the breakdown voltage characteristic is small, and the breakdown voltage characteristic comparable to that of the place where the first pickup electrode 81 and the second pickup electrode 82 are disposed can be obtained.
- the same effect can be obtained even if at least one of the first pickup electrode 81 and the second pickup electrode 82 is removed. In particular, the removal of the second pickup electrode 82 is effective.
- an insulating film such as an interlayer insulating film is sandwiched between at least one of the contact regions 62 and 56 and the first and second pickup electrodes 81 and 82. The same effect can be obtained even if the contact regions 62 and 56 are electrically insulated.
- FIG. 5 is a plan view showing a main part of the high voltage integrated circuit device 200 according to the second embodiment of the present invention.
- FIG. 6 is a cross-sectional view showing a main part of the high voltage integrated circuit device 200 according to the second embodiment of the present invention.
- FIG. 6A is a cross-sectional view of the main part showing the cross-sectional structure taken along the line AA in FIG.
- FIG. 6B is a cross-sectional view of the main part showing the cross-sectional structure taken along the line BB in FIG.
- the difference between the high voltage integrated circuit device 200 of FIG. 5 and the high voltage integrated circuit device 100 of FIG. 1 is that the first pickup electrode 81 and the second pickup electrode 82 (or the contact portions 81a and 82a) are not removed and the intermediate potential is reduced.
- the double resurf structure 87 is formed in the high voltage junction termination region of the facing portion E where the facing distance W to the region is short.
- the p region 61 and the n contact region 62 are formed on the surface layer of the n ⁇ well region 4, which is the high breakdown voltage junction termination region at the facing portion E where the facing distance is short with respect to the intermediate potential region.
- a p ⁇ top layer 63 is formed away from the structure to form a double RESURF structure.
- the n ⁇ well region 4 is narrowed in the vertical direction (depth direction of the p semiconductor substrate 1) at the facing portion E, and thus the current path between the first pickup electrode 81 and the second pickup electrode 82.
- the resistance can be increased.
- the portion other than the facing portion E has a single resurf structure and the n ⁇ well region 4 is not narrowed in the vertical direction.
- Increasing the resistance of the facing portion E increases the cathode resistance 88 of the parasitic diode 46 composed of the p region 61 and the n ⁇ well region 4. As a result, when a negative voltage surge is input, the injection of holes at the opposite location E can be locally reduced.
- the double resurf structure 87 is a structure in which a p ⁇ top layer 63 that is an electric field relaxation region is provided on the surface of the n ⁇ well region 4 constituting the high breakdown voltage junction termination region. Since the n ⁇ well region 4 is sandwiched between the p semiconductor substrate 1 and the p ⁇ top layer 63, depletion of the n ⁇ well region 4 is promoted, and the electric field at the facing portion E is relaxed.
- the facing portion E where the double resurf structure 87 is formed is a portion where the surface electric field is relaxed compared to the portion where the single resurf structure is formed, so that the p ⁇ top layer 63 and the n ⁇ well region 4
- the breakdown voltage characteristics can be realized without any problem.
- the double resurf structure 87 in which the p ⁇ top layer 63 is formed on the surface layer of the high breakdown voltage junction termination region (n ⁇ well region 4) in the facing portion E where the facing distance W to the Vs potential region is short is used.
- a high resistance region cathode resistance 88 in which hole injection is suppressed when a negative voltage surge is input.
- FIG. 7 is a plan view showing a main part of the high voltage integrated circuit device 300 according to the third embodiment of the present invention.
- FIG. 8 is a cross-sectional view showing a main part of the high voltage integrated circuit device 300 according to the third embodiment of the present invention.
- FIG. 8A is a cross-sectional view of the main part showing the cross-sectional structure taken along the line AA in FIG.
- FIG. 8B is a cross-sectional view of the main part showing the cross-sectional structure taken along the line CC in FIG.
- the high withstand voltage integrated circuit device 300 in FIG. 7 is different from the high withstand voltage integrated circuit device 200 in FIG. 5 in that instead of forming the p ⁇ top layer 63 in the facing portion E where the facing distance W to the Vs potential region is short. This is the point that the width of the n ⁇ well region 4 which is a high voltage junction termination region is wider than other portions. By doing so, the resistance of the current path between the first pickup electrode 81 and the second pickup electrode 82 can be made higher at the opposite location E of the high breakdown voltage junction termination region than at other locations.
- the expanded portion 90 of the n ⁇ well region 89 whose width is expanded as compared with other portions may be a distance that satisfies the negative voltage surge resistance required for the HVIC.
- the n-type impurity concentration of the n ⁇ well region 4 is an order of magnitude thinner than that of the n well region 3, it may be about several ⁇ m. Therefore, there is no increase in chip area.
- the cathode resistance 91 of the parasitic diode 46 composed of the p region 61 and the n ⁇ well region 4 can be increased. As a result, a region where the injection of holes is locally small when a negative voltage surge is input can be formed in the breakdown voltage region.
- the case where the p offset region 31 constituting the intermediate potential region is adjacent to the high withstand voltage junction termination region has been described.
- the n drain region 34 constituting the intermediate potential region has the high withstand voltage. The same applies to the case adjacent to the junction termination region. Further, the configurations shown in Embodiments 1 to 3 can be combined.
- FIG. 16 is a plan view showing a main part of a high voltage integrated circuit device 400 according to the fourth embodiment of the present invention.
- FIG. 17 is a cross-sectional view showing a main part of the high voltage integrated circuit device 400 according to the fourth embodiment of the present invention.
- FIG. 17A is a main part sectional view showing a sectional structure taken along the line GG in FIG.
- FIG. 17B is a main part sectional view showing another example of the sectional structure taken along the cutting line GG of FIG. 16, and is a modification of FIG. 17A.
- a high voltage integrated circuit device 400 of FIG. 16 is a modification of the high voltage integrated circuit device 100 of FIG.
- the high voltage integrated circuit device 400 of FIG. 16 is different from the high voltage integrated circuit device 100 of FIG. 1 in that the n well region 3 is separated into an n well region 301 and an n well region 302 by a p-type isolation region 611. And the n ⁇ well region 4 is separated into the n ⁇ well region 401 and the n ⁇ well region 402 by the p-type isolation region 611.
- the p-type isolation region 611 is configured by the p semiconductor substrate 1 that is in contact with the LOCOS oxide film between the n-well region 301 and the n-well region 302.
- the p-type diffusion region reaches the p semiconductor substrate 1 from the surface of the well region 3. Even in such a configuration, the same effect as in the first embodiment can be obtained.
- the p-type isolation region 611 can be formed similarly to the high voltage integrated circuit device 400.
- the effects of the present invention can be achieved.
- the high voltage integrated circuit device is a high voltage integrated circuit used for transmitting an on / off drive signal to the gate of a switching power device in a PWM inverter, a switching power supply or the like. Useful for equipment.
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Abstract
Description
図1は、この発明の実施の形態1にかかる高耐圧集積回路装置100の要部を示す平面図である。また、図2は、図1の切断線A-Aに平行な方向で切断した場合の全体の要部を示す断面図である。図1,2において、図9~図13に示した構成に対応する構成には同一の符号を付した。
図5は、この発明の実施の形態2にかかる高耐圧集積回路装置200の要部を示す平面図である。また、図6は、この発明の実施の形態2にかかる高耐圧集積回路装置200の要部を示す断面図である。図6(a)は、図5の切断線A-Aの断面構造について示す要部断面図である。図6(b)は、図5の切断線B-Bの断面構造について示す要部断面図である。
図7は、この発明の実施の形態3にかかる高耐圧集積回路装置300の要部を示す平面図である。また、図8は、この発明の実施の形態3にかかる高耐圧集積回路装置300の要部を示す断面図である。図8(a)は、図7の切断線A-Aの断面構造について示す要部断面図である。図8(b)は、図7の切断線C-Cの断面構造について示す要部断面図である。
図16は、この発明の実施の形態4にかかる高耐圧集積回路装置400の要部を示す平面図である。また、図17は、この発明の実施の形態4にかかる高耐圧集積回路装置400の要部を示す断面図である。図17(a)は、図16の切断線G-Gの断面構造について示す要部断面図である。図17(b)は、図16の切断線G-Gの断面構造の別の一例について示す要部断面図であり、図17(a)の変形例である。
2 nウェル領域(低電位領域)
3 nウェル領域(高電位領域)
4 n-ウェル領域(高耐圧接合終端領域)
21 pオフセット領域(低電位領域)
31 pオフセット領域(中間電位領域)
46 寄生ダイオード
51 p領域(レベルシフト形成領域)
56 第2コンタクト領域(pコンタクト領域;グランド電位領域)
61 p領域(グランド電位領域)
62 第1コンタクト領域(nコンタクト領域;高電位領域)
81 第1ピックアップ電極
81a 接触部
82 第2ピックアップ電極
82a 接触部
83 正孔
84 電子
85 nMOSFET
86 pMOSFET
87 ダブルリサーフ構造
100,200,300,400 高耐圧集積回路装置
Vs 中間電位
H-VDD Vs端子を基準とする低電圧電源の高電位側
GND グランド(接地)
L-VDD GNDを基準とする低電圧電源の高電位側
Claims (7)
- 直列に接続された2つのパワートランジスタの高電位側パワートランジスタを駆動する高耐圧半導体集積回路装置であって、
第1導電型の半導体基板の表面層に形成された第2導電型の高電位領域と、
前記半導体基板の表面層に、前記高電位領域と接し、かつ前記高電位領域の外周に沿って形成された、前記高電位領域よりも不純物濃度の低い第2導電型の耐圧領域と、
前記半導体基板の表面層に、前記耐圧領域と接し、かつ前記耐圧領域の外周に沿って形成された、接地電位が印加される第1導電型のグランド電位領域と、
前記半導体基板の表面層の、前記グランド電位領域の外側に形成された第2導電型の低電位領域と、
前記高電位領域内に形成され前記高電位領域と接合分離された第1導電型の中間電位領域と、
前記耐圧領域の前記高電位領域側端部に沿って形成された第2導電型の第1コンタクト領域と、
前記グランド電位領域の表面層に前記第1コンタクト領域に対向して形成された第1導電型の第2コンタクト領域と、
前記第1コンタクト領域に接する第1ピックアップ電極と、
前記第2コンタクト領域に接する第2ピックアップ電極と、
を備え、
前記中間電位領域は、直列に接続された2つの前記パワートランジスタの主回路電源である高電圧電源の高電位側電位からグランド電位までの間の中間電位が印加される領域であり、
前記低電位領域は前記グランド電位を基準とする第1低電圧電源の高電位側電位が印加される領域であり、
前記高電位領域は、前記中間電位を基準とする第2低電圧電源の高電位側電位が印加される領域であり、
前記耐圧領域、前記グランド電位領域、前記第1コンタクト領域および前記第2コンタクト領域から構成される高耐圧接合終端領域が形成されており、
前記中間電位領域との対向距離が他の箇所より短い高耐圧接合終端領域の箇所における、前記第1ピックアップ電極と前記第2ピックアップ電極との間の電流通路の抵抗は他の箇所より高いことを特徴とする高耐圧集積回路装置。 - 直列に接続された2つのパワートランジスタの高電位側パワートランジスタを駆動するための高耐圧半導体集積回路装置であって、
第1導電型の半導体基板の表面層に形成された第2導電型の高電位領域と、
前記高電位領域の外周の一部を分離する第1導電型の分離領域と、
前記半導体基板の表面層に、前記高電位領域と接し、かつ前記高電位領域の外周に沿って形成された、前記高電位領域よりも不純物濃度の低い第2導電型の耐圧領域と、
前記半導体基板の表面層に、前記分離領域と接し、かつ前記耐圧領域の外周に形成された、接地電位が印加される第1導電型のグランド電位領域と、
前記半導体基板の表面層の、前記グランド電位領域の外側に形成された第2導電型の低電位領域と、
前記高電位領域内に形成され前記高電位領域と接合分離された第1導電型の中間電位領域と、
前記耐圧領域の前記高電位領域側端部に沿って形成された第1コンタクト領域と、
前記グランド電位領域の表面層に形成された第2コンタクト領域と、
前記第1コンタクト領域に接する第1ピックアップ電極と、
前記第2コンタクト領域に接する第2ピックアップ電極と、
を備え、
前記中間電位領域は、直列に接続された2つの前記パワートランジスタの主回路電源である高電圧電源の高電位側電位からグランド電位までの間の中間電位が印加される領域であり、
前記低電位領域は前記グランド電位を基準とする第1低電圧電源の高電位側電位が印加される領域であり、
前記高電位領域は、前記中間電位を基準とする第2低電圧電源の高電位側電位が印加される領域であり、
前記耐圧領域、前記グランド電位領域、前記第1コンタクト領域および前記第2コンタクト領域から構成される高耐圧接合終端領域が形成されており、
前記中間電位領域との対向距離が他の箇所より短い高耐圧接合終端領域の箇所における、前記第1ピックアップ電極と前記第2ピックアップ電極との間の電流通路の抵抗は他の箇所より高いことを特徴とする高耐圧集積回路装置。 - 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所を除いて前記第1ピックアップ電極を形成することで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
- 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所を除いて前記第2ピックアップ電極を形成することで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
- 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所において、少なくとも前記第1コンタクト領域と前記第1ピックアップ電極または第2コンタクト領域と第2ピックアップ電極いずれかを電気的に絶縁することで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
- 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所において、前記高耐圧接合終端領域の表面層に前記高電位領域と前記グランド電位領域とのそれぞれから離して前記グランド電位領域と同一の導電型の半導体領域を形成しダブルリサーフ構造とすることで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
- 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所において、前記耐圧領域を前記低電位領域側に伸ばすことで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
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JP2015173255A (ja) * | 2014-02-19 | 2015-10-01 | 富士電機株式会社 | 高耐圧集積回路装置 |
WO2016002508A1 (ja) * | 2014-07-02 | 2016-01-07 | 富士電機株式会社 | 半導体集積回路装置 |
WO2016132418A1 (ja) * | 2015-02-18 | 2016-08-25 | 富士電機株式会社 | 半導体集積回路 |
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