JP5435138B2 - 高耐圧集積回路装置 - Google Patents
高耐圧集積回路装置 Download PDFInfo
- Publication number
- JP5435138B2 JP5435138B2 JP2012527559A JP2012527559A JP5435138B2 JP 5435138 B2 JP5435138 B2 JP 5435138B2 JP 2012527559 A JP2012527559 A JP 2012527559A JP 2012527559 A JP2012527559 A JP 2012527559A JP 5435138 B2 JP5435138 B2 JP 5435138B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- potential
- contact
- voltage
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015556 catabolic process Effects 0.000 claims description 37
- 239000004065 semiconductor Substances 0.000 claims description 36
- 239000002344 surface layer Substances 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 35
- 238000002955 isolation Methods 0.000 claims description 10
- 239000012535 impurity Substances 0.000 claims description 9
- 230000010354 integration Effects 0.000 claims 1
- 238000000926 separation method Methods 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 description 20
- 230000007257 malfunction Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 17
- 239000010410 layer Substances 0.000 description 13
- 238000000034 method Methods 0.000 description 9
- 230000006378 damage Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 230000007423 decrease Effects 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000001514 detection method Methods 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910015900 BF3 Inorganic materials 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
図1は、この発明の実施の形態1にかかる高耐圧集積回路装置100の要部を示す平面図である。また、図2は、図1の切断線A−Aに平行な方向で切断した場合の全体の要部を示す断面図である。図1,2において、図9〜図13に示した構成に対応する構成には同一の符号を付した。
図5は、この発明の実施の形態2にかかる高耐圧集積回路装置200の要部を示す平面図である。また、図6は、この発明の実施の形態2にかかる高耐圧集積回路装置200の要部を示す断面図である。図6(a)は、図5の切断線A−Aの断面構造について示す要部断面図である。図6(b)は、図5の切断線B−Bの断面構造について示す要部断面図である。
図7は、この発明の実施の形態3にかかる高耐圧集積回路装置300の要部を示す平面図である。また、図8は、この発明の実施の形態3にかかる高耐圧集積回路装置300の要部を示す断面図である。図8(a)は、図7の切断線A−Aの断面構造について示す要部断面図である。図8(b)は、図7の切断線C−Cの断面構造について示す要部断面図である。
図16は、この発明の実施の形態4にかかる高耐圧集積回路装置400の要部を示す平面図である。また、図17は、この発明の実施の形態4にかかる高耐圧集積回路装置400の要部を示す断面図である。図17(a)は、図16の切断線G−Gの断面構造について示す要部断面図である。図17(b)は、図16の切断線G−Gの断面構造の別の一例について示す要部断面図であり、図17(a)の変形例である。
2 nウェル領域(低電位領域)
3 nウェル領域(高電位領域)
4 n-ウェル領域(高耐圧接合終端領域)
21 pオフセット領域(低電位領域)
31 pオフセット領域(中間電位領域)
46 寄生ダイオード
51 p領域(レベルシフト形成領域)
56 第2コンタクト領域(pコンタクト領域;グランド電位領域)
61 p領域(グランド電位領域)
62 第1コンタクト領域(nコンタクト領域;高電位領域)
81 第1ピックアップ電極
81a 接触部
82 第2ピックアップ電極
82a 接触部
83 正孔
84 電子
85 nMOSFET
86 pMOSFET
87 ダブルリサーフ構造
100,200,300,400 高耐圧集積回路装置
Vs 中間電位
H−VDD Vs端子を基準とする低電圧電源の高電位側
GND グランド(接地)
L−VDD GNDを基準とする低電圧電源の高電位側
Claims (7)
- 直列に接続された2つのパワートランジスタの高電位側パワートランジスタを駆動する高耐圧半導体集積回路装置であって、
第1導電型の半導体基板の表面層に形成された第2導電型の高電位領域と、
前記半導体基板の表面層に、前記高電位領域と接し、かつ前記高電位領域の外周に沿って形成された、前記高電位領域よりも不純物濃度の低い第2導電型の耐圧領域と、
前記半導体基板の表面層に、前記耐圧領域と接し、かつ前記耐圧領域の外周に沿って形成された、接地電位が印加される第1導電型のグランド電位領域と、
前記半導体基板の表面層の、前記グランド電位領域の外側に形成された第2導電型の低電位領域と、
前記高電位領域内に形成され前記高電位領域と接合分離された第1導電型の中間電位領域と、
前記耐圧領域の前記高電位領域側端部に沿って形成された第2導電型の第1コンタクト領域と、
前記グランド電位領域の表面層に前記第1コンタクト領域に対向して形成された第1導電型の第2コンタクト領域と、
前記第1コンタクト領域に接する第1ピックアップ電極と、
前記第2コンタクト領域に接する第2ピックアップ電極と、
を備え、
前記中間電位領域は、直列に接続された2つの前記パワートランジスタの主回路電源である高電圧電源の高電位側電位からグランド電位までの間の中間電位が印加される領域であり、
前記低電位領域は前記グランド電位を基準とする第1低電圧電源の高電位側電位が印加される領域であり、
前記高電位領域は、前記中間電位を基準とする第2低電圧電源の高電位側電位が印加される領域であり、
前記耐圧領域、前記グランド電位領域、前記第1コンタクト領域および前記第2コンタクト領域から構成される高耐圧接合終端領域が形成されており、
前記中間電位領域との対向距離が他の箇所より短い高耐圧接合終端領域の箇所における、前記第1ピックアップ電極と前記第2ピックアップ電極との間の電流通路の抵抗は他の箇所より高いことを特徴とする高耐圧集積回路装置。 - 直列に接続された2つのパワートランジスタの高電位側パワートランジスタを駆動するための高耐圧半導体集積回路装置であって、
第1導電型の半導体基板の表面層に形成された第2導電型の高電位領域と、
前記高電位領域の外周の一部を分離する第1導電型の分離領域と、
前記半導体基板の表面層に、前記高電位領域と接し、かつ前記高電位領域の外周に沿って形成された、前記高電位領域よりも不純物濃度の低い第2導電型の耐圧領域と、
前記半導体基板の表面層に、前記分離領域と接し、かつ前記耐圧領域の外周に形成された、接地電位が印加される第1導電型のグランド電位領域と、
前記半導体基板の表面層の、前記グランド電位領域の外側に形成された第2導電型の低電位領域と、
前記高電位領域内に形成され前記高電位領域と接合分離された第1導電型の中間電位領域と、
前記耐圧領域の前記高電位領域側端部に沿って形成された第2導電型の第1コンタクト領域と、
前記グランド電位領域の表面層に前記第1コンタクト領域に対向して形成された第1導電型の第2コンタクト領域と、
前記第1コンタクト領域に接する第1ピックアップ電極と、
前記第2コンタクト領域に接する第2ピックアップ電極と、
を備え、
前記中間電位領域は、直列に接続された2つの前記パワートランジスタの主回路電源である高電圧電源の高電位側電位からグランド電位までの間の中間電位が印加される領域であり、
前記低電位領域は前記グランド電位を基準とする第1低電圧電源の高電位側電位が印加される領域であり、
前記高電位領域は、前記中間電位を基準とする第2低電圧電源の高電位側電位が印加される領域であり、
前記耐圧領域、前記グランド電位領域、前記第1コンタクト領域および前記第2コンタクト領域から構成される高耐圧接合終端領域が形成されており、
前記中間電位領域との対向距離が他の箇所より短い高耐圧接合終端領域の箇所における、前記第1ピックアップ電極と前記第2ピックアップ電極との間の電流通路の抵抗は他の箇所より高いことを特徴とする高耐圧集積回路装置。 - 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所を除いて前記第1ピックアップ電極を形成することで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
- 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所を除いて前記第2ピックアップ電極を形成することで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
- 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所において、少なくとも前記第1コンタクト領域と前記第1ピックアップ電極または前記第2コンタクト領域と前記第2ピックアップ電極いずれかを電気的に絶縁することで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
- 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所において、前記高耐圧接合終端領域の表面層に前記高電位領域と前記グランド電位領域とのそれぞれから離して前記グランド電位領域と同一の導電型の半導体領域を形成しダブルリサーフ構造とすることで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
- 前記中間電位領域との対向距離が他の箇所より短い前記高耐圧接合終端領域の箇所において、前記耐圧領域を前記低電位領域側に伸ばすことで、前記抵抗が他の箇所より高くなっていることを特徴とする請求項1または2に記載の高耐圧集積回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012527559A JP5435138B2 (ja) | 2011-06-24 | 2011-09-12 | 高耐圧集積回路装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011140137 | 2011-06-24 | ||
JP2011140137 | 2011-06-24 | ||
JP2012527559A JP5435138B2 (ja) | 2011-06-24 | 2011-09-12 | 高耐圧集積回路装置 |
PCT/JP2011/070760 WO2012176347A1 (ja) | 2011-06-24 | 2011-09-12 | 高耐圧集積回路装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP5435138B2 true JP5435138B2 (ja) | 2014-03-05 |
JPWO2012176347A1 JPWO2012176347A1 (ja) | 2015-02-23 |
Family
ID=47422214
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012527559A Active JP5435138B2 (ja) | 2011-06-24 | 2011-09-12 | 高耐圧集積回路装置 |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP2725606A4 (ja) |
JP (1) | JP5435138B2 (ja) |
CN (1) | CN103038876B (ja) |
WO (1) | WO2012176347A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160133473A (ko) * | 2014-03-17 | 2016-11-22 | 케이엘에이-텐코 코포레이션 | 화상 센서, 검사 시스템 및 물품의 검사 방법 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6447139B2 (ja) * | 2014-02-19 | 2019-01-09 | 富士電機株式会社 | 高耐圧集積回路装置 |
WO2016002508A1 (ja) * | 2014-07-02 | 2016-01-07 | 富士電機株式会社 | 半導体集積回路装置 |
JPWO2016132418A1 (ja) * | 2015-02-18 | 2017-05-25 | 富士電機株式会社 | 半導体集積回路 |
CN104900645B (zh) * | 2015-05-28 | 2019-01-11 | 北京燕东微电子有限公司 | 电压浪涌保护器件及其制造方法 |
JP7472522B2 (ja) | 2019-04-11 | 2024-04-23 | 富士電機株式会社 | 半導体集積回路 |
FR3101970B1 (fr) * | 2019-10-15 | 2021-10-01 | Seb Sa | Circuit de contrôle de machine de distribution de boissons à sécurité électrique renforcée |
CN111081705B (zh) * | 2019-11-25 | 2022-06-10 | 重庆大学 | 单片集成式半桥功率器件模块 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0738011B1 (en) * | 1995-04-12 | 2014-12-10 | Fuji Electric Co., Ltd. | High voltage integrated circuit, high voltage junction terminating structure, and high voltage MIS transistor |
JP3941206B2 (ja) * | 1998-02-26 | 2007-07-04 | 富士電機デバイステクノロジー株式会社 | 高耐圧ic |
JP4961658B2 (ja) * | 2003-02-17 | 2012-06-27 | 富士電機株式会社 | 双方向素子および半導体装置 |
CN101567373B (zh) * | 2004-02-16 | 2011-04-13 | 富士电机系统株式会社 | 双方向元件及其制造方法 |
JP5191132B2 (ja) * | 2007-01-29 | 2013-04-24 | 三菱電機株式会社 | 半導体装置 |
JP5072043B2 (ja) * | 2009-03-24 | 2012-11-14 | 三菱電機株式会社 | 半導体装置 |
-
2011
- 2011-09-12 WO PCT/JP2011/070760 patent/WO2012176347A1/ja active Application Filing
- 2011-09-12 CN CN201180005561.5A patent/CN103038876B/zh active Active
- 2011-09-12 EP EP11846055.9A patent/EP2725606A4/en not_active Withdrawn
- 2011-09-12 JP JP2012527559A patent/JP5435138B2/ja active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160133473A (ko) * | 2014-03-17 | 2016-11-22 | 케이엘에이-텐코 코포레이션 | 화상 센서, 검사 시스템 및 물품의 검사 방법 |
KR102172956B1 (ko) * | 2014-03-17 | 2020-11-02 | 케이엘에이 코포레이션 | 화상 센서, 검사 시스템 및 물품의 검사 방법 |
Also Published As
Publication number | Publication date |
---|---|
CN103038876B (zh) | 2016-08-24 |
JPWO2012176347A1 (ja) | 2015-02-23 |
CN103038876A (zh) | 2013-04-10 |
WO2012176347A1 (ja) | 2012-12-27 |
EP2725606A1 (en) | 2014-04-30 |
EP2725606A4 (en) | 2015-07-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5435138B2 (ja) | 高耐圧集積回路装置 | |
US9478543B2 (en) | Semiconductor integrated circuit | |
JP6447139B2 (ja) | 高耐圧集積回路装置 | |
JP5099282B1 (ja) | 高耐圧集積回路装置 | |
US8704328B2 (en) | High-voltage integrated circuit device | |
JP4993092B2 (ja) | レベルシフト回路および半導体装置 | |
JP6237901B2 (ja) | 半導体集積回路装置 | |
JP5991435B2 (ja) | 半導体装置 | |
US9412732B2 (en) | Semiconductor device | |
JP5353016B2 (ja) | 半導体装置 | |
WO2014058028A1 (ja) | 半導体装置 | |
EP2924723A2 (en) | Semiconductor device | |
JP2014138091A (ja) | 半導体装置およびその製造方法 | |
JP2010010264A (ja) | 半導体装置 | |
JP5256750B2 (ja) | 半導体装置 | |
JP2009266933A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20131112 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131125 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5435138 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |