WO2012174689A1 - 一种应变半导体沟道的形成方法 - Google Patents

一种应变半导体沟道的形成方法 Download PDF

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Publication number
WO2012174689A1
WO2012174689A1 PCT/CN2011/001311 CN2011001311W WO2012174689A1 WO 2012174689 A1 WO2012174689 A1 WO 2012174689A1 CN 2011001311 W CN2011001311 W CN 2011001311W WO 2012174689 A1 WO2012174689 A1 WO 2012174689A1
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forming
layer
semiconductor channel
ion implantation
strained semiconductor
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French (fr)
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尹海洲
骆志炯
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/380,019 priority Critical patent/US20120329228A1/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/21—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically active species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/28—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by an annealing step, e.g. for activation of dopants

Definitions

  • the present invention relates to the field of semiconductors, and more particularly to a method of forming a strained semiconductor channel.
  • strain channel engineering which aims to increase channel mobility, plays an increasingly important role.
  • Theoretical and empirical studies have confirmed that when stress is applied to the channel of a transistor, the carrier mobility of the transistor can be increased or decreased; however, it is also known that electrons and holes have different responses to the same type of strain. .
  • the application of compressive stress in the direction of current flow is advantageous for hole mobility, but is detrimental to electron mobility.
  • the application of tensile stress is advantageous for electron mobility but is detrimental to hole mobility.
  • introducing a tensile stress in the channel direction increases the mobility of electrons in the channel; on the other hand, for a PMOS device, introducing a compressive stress in the channel direction increases the hole in the channel. Mobility.
  • a number of methods have been developed, one of which is to produce a "global strain", i.e., to generate strain applied to the bulk transistor device region from the substrate, the global strain being generated using a structure such as strained Si /SiGe relaxation layer, strain Si on the insulator, etc.
  • a strained Si cladding layer must be formed on, for example, a SiGe layer before a device fabrication process (e.g., shallow trench isolation (STI), gate formation, etc.).
  • a device fabrication process e.g., shallow trench isolation (STI), gate formation, etc.
  • the strained Si coating may be damaged during the device fabrication process, for example, pad oxidation treatment in the STI process, sacrificial oxidation treatment before the gate formation process, various wet chemistry Cleaning treatment, etc., may cause loss of the strained Si coating;
  • the strained Si coating may relax in the high temperature step (stress is released), for example, to activate the source/drain dopant annealing Treatment may cause stress in the strained Si coating to be released.
  • One solution is to etch a portion of the SiGe relaxation layer after removing the replacement gate, and epitaxially grow the strained semiconductor layer at the location where the etched SiGe relaxation layer is removed to form a channel, thereby avoiding strained semiconductor channel exposure. Source/drain annealing at high temperatures, and The processing steps to be experienced in straining the semiconductor channel are reduced, and semiconductor layer loss is avoided.
  • the SiGe single material is etched, and there is a problem that the etching depth is difficult to control due to the selection ratio.
  • the etch stop layer can be formed using SiGe, this will undoubtedly increase the process difficulty of epitaxial growth, and the effect of controlling the etching is not obvious.
  • the present invention provides a novel method of forming a strained semiconductor channel, comprising the steps of:
  • a second gate structure is formed on the semiconductor epitaxial layer.
  • the present invention avoids the source/drain annealing process in which the strained semiconductor channel is exposed to high temperatures by forming a strained channel after source/drain annealing, and also reduces the processing steps to be experienced by straining the semiconductor channel. Semiconductor layer loss is avoided. In addition, since the etching rate of the ion implantation region is significantly larger than the etching rate of the portion of the relaxation layer where the ion implantation is not performed, the etching depth can be easily controlled.
  • Figure 1 is a cross-sectional view showing the structure after forming a relaxation layer on a village floor
  • FIG. 2 is a cross-sectional view showing a structure in which a first gate structure and a sidewall are formed on a relaxation layer
  • FIG. 3 is a cross-sectional view showing a structure after forming an interlayer dielectric layer
  • FIG. 4 is a cross-sectional view showing a structure after chemical mechanical planarization (CMP) treatment
  • Figure 5 is a cross-sectional view showing the structure after removing the exposed first gate structure
  • Figure 6 is a cross-sectional view showing the structure after ion implantation
  • Figure 7 is a cross-sectional view showing the structure after the ion implantation region is removed to form a trench
  • Figure 8 is a cross-sectional view showing the structure after forming a semiconductor epitaxial layer
  • Figure 9 is a cross-sectional view showing the structure after forming the second gate structure.
  • a relaxation layer 105 is formed on a substrate 100 (e.g., Si, silicon-on-insulator (SOI), etc.) as shown in FIG.
  • the relaxation layer may be formed of SiGe.
  • 06 atom% is from the adjacent substrate 100 to a direction away from the substrate 100, for example, gradually changing from 20% to 100%, that is, Si 1-
  • the X in x Ge x gradually changes from 0.2 to 1.
  • the specific value of the composition of the SiGe relaxation layer 105 is composed only by him (that is, the range of variation of X is reselected), and the gradual change of X may be various variations such as a linear change, a hyperbolic change, an exponential change, and the like.
  • a first gate structure is formed on the relaxation layer 105 (as a sacrificial gate stack, which may include a first dielectric layer 110, a first gate layer 115 on the first dielectric layer 110, and a cap layer 123) And a sidewall 120 surrounding the first dielectric layer 110 and the first gate layer 115, as shown in FIG.
  • the first dielectric layer 110 is typically formed of an oxide or nitride, such as Si0 2 .
  • the first gate layer 1 15 is formed, for example, of polysilicon.
  • the cap layer 123 is formed of, for example, a nitride.
  • the spacers 120 are typically oxides, nitrides, oxynitrides, carbides or carbon oxides, and other materials such as silicon nitride.
  • the above structures may also be selected from other materials known in the art.
  • the first dielectric layer 110 has a thickness of 1 to 5 nm.
  • the first gate layer 115 has a thickness of 20 to 70 nm, and the sidewall spacer 120 has a thickness of 10 to 40 nm. This step is part of the traditional process and will not be repeated here.
  • a source/drain (not shown) may be formed in the relaxation layer on both sides of the first gate structure by a conventional method such as ion implantation and high temperature annealing.
  • an interlayer dielectric layer 125 is formed on the relaxation layer, the first gate structure, and the side walls, as shown in FIG.
  • undoped silicon oxide various doped silicon oxides (e.g., borosilicate glass, borophosphosilicate glass, etc.), silicon nitride, or the like may be used as the constituent material of the interlayer dielectric layer 125.
  • the method of forming the interlayer dielectric layer can be formed, for example, by a deposition process including, but not limited to, chemical vapor deposition (CVD), plasma assisted CVD, atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition, or the like. Deposition process.
  • CMP chemical mechanical planarization
  • the first gate structure is removed to form an opening, thereby exposing the relaxation layer 105, as shown in FIG.
  • the cap layer 123 is present in the first gate structure, it is necessary to first perform an additional CMP process or reactive ion etching (RIE) process to remove the cap layer.
  • RIE reactive ion etching
  • the first gate layer 151 and the first dielectric layer 110 are then sequentially removed. This step can be carried out by any method well known in the art, such as wet etching or dry etching.
  • the ion implantation implant is P, As or a combination of both, and has a dose ranging from 5 ⁇ 10 13 -4 ⁇ 10 15 cm - 3 and an implantation energy of l - 3 keV.
  • Embodiments of the present invention are easy to control the depth by controlling the energy of ion implantation, for example, controlling the depth of the ion implantation region 130 to 3 nm to 10 nm.
  • the annealing is followed, for example, at a temperature in the range of 700 to 800 °C.
  • the ion implantation region 130 is etched to form a trench in the relaxation layer, as shown in FIG.
  • the etching can be performed by techniques well known in the art, such as by wet etching or dry etching. For example, for a SiGe relaxed layer, it can be done by dry etching using NF 3 and Cl 2 . Since the etching rate of the ion implantation region 130 is significantly larger than the etching rate of the portion of the relaxation layer where the ion implantation is not performed, the etching depth can be easily controlled. The proper channel thickness enables the best electron mobility.
  • the lattice constant of the epitaxial layer material is different from the lattice constant of the relaxation layer material to form a strained semiconductor channel.
  • Epitaxial growth for example, using metal Physical chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE).
  • MOCVD metal Physical chemical vapor deposition
  • MBE molecular beam epitaxy
  • the semiconductor epitaxial layer is composed of a Si epitaxial layer, a Ge epitaxial layer, or a SiGe epitaxial layer (where Ge atom% can be freely adjusted), which cooperates with the SiGe relaxed layer, and the epitaxial layer formed therein Strain is introduced into the channel to increase the mobility of electrons or holes in the channel, which is beneficial to improve the performance of the MOS device.
  • the thickness of the semiconductor epitaxial layer can be in the range of 5-10 nm.
  • the top surface of the epitaxial layer 135 may be on the same plane as the top surface of the relaxation layer 105 (as shown in FIG. 8) or may not be on the same plane (not shown), but should be within the tolerances allowed by the semiconductor process.
  • the epitaxial layer is Si, a tensile stress channel can generally be formed, thereby facilitating adjustment of the electron mobility of the n-type device; if the epitaxial layer is Ge, a compressive stress channel can be formed, thereby facilitating adjustment of the cavity of the p-type device. Mobility; If the SiGe layer is epitaxial, it is possible to control the formation of compressive stress or tensile stress on both sides of the channel by adjusting the ratio of Ge. Therefore, the embodiment of the present invention can be applied to a pMOSFET or an nMOSFET.
  • a second gate dielectric layer 140 and a second gate layer 145 are formed on the surface of the above structure, and planarized to the interlayer dielectric layer to form a second gate structure, as shown in FIG.
  • the method of forming the second gate dielectric layer 140 and the second gate layer 145 may be formed, for example, by a deposition process including, but not limited to, chemical vapor deposition (CVD), plasma assisted CVD, atomic layer deposition (ALD), evaporation, reactive sputtering. , chemical solution deposition or other similar deposition processes.
  • the second gate dielectric layer may be formed of SiO 2 or a high K dielectric material selected from Zr0 2 , Hf0 2 , A1 2 0 3 , HfSiO, HfSiON, and/or mixtures thereof.
  • the second gate layer includes a work function metal gate (TiN) and a metal conductor layer (TiAl), and may have polysilicon thereon.
  • the thickness of the second gate dielectric shield layer 140 may be in the range of 1 to 5 nm.
  • a semiconductor fabrication process such as forming contact holes and metallization interconnections, etc., can be performed in a conventional manner to form a MOS device.
  • This embodiment avoids the source/drain annealing process in which the strained semiconductor channel is exposed to high temperatures in a conventional MOS process by forming a strained channel 135 after source/drain annealing, which is experienced by reducing the strained semiconductor channel.
  • the processing steps avoid the loss of the semiconductor layer.
  • the etching rate of the ion implantation region formed in the relaxation layer is significantly larger than the etching rate of the portion of the relaxation layer where the ion implantation is not performed, the etching depth can be easily controlled to control the finally formed trench.
  • the thickness of the land region can thus further control the stress generated on both sides of the channel region.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

一种应变半导体沟道的形成方法，通过在源极/漏极退火之后形成应变沟道，即避免了应变半导体沟道暴露于高温的源极/漏极退火处理，又由于减少了应变半导体沟道所要经历的处理步骤，而避免了半导体层损耗。另外，由于离子注入区的刻蚀速率明显大于未经过离子注入的弛豫层部分的刻蚀速率，故可容易的控制刻蚀深度。

Description

一种应变半导体沟道的形成方法 优先权要求
本申请要求了 201 1年 6月 23日提交的、申请号为 201 1 10171241.9、 发明名称为 "一种应变半导体沟道的形成方法" 的中国专利申请的优 先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体领域， 特别涉及一种应变半导体沟道的形成方 法。
背景技术
随着器件特征尺寸的不断缩小， 以提高沟道栽流子迁移率为目的 的应变沟道工程起到越来越重要的作用。 理论和经验研究已经证实，当 将应力施加到晶体管的沟道中时,晶体管的载流子迁移率会得以提高或 降低;然而,还已知，电子和空穴对相同类型的应变具有不同的响应。例如 在电流流动的方向上施加压应力对空穴迁移率有利,但是对电子迁移率 有害。 而施加张应力对电子迁移率有利,但是对空穴迁移率有害。 具体 而言， 对于 NMOS器件， 在沿沟道方向引入张应力提高了其沟道中电 子的迁移率； 另一方面， 对于 PMOS器件， 在沿沟道方向引入压应力 提高了其沟道中空穴的迁移率。 根据这一理论， 已发展了许多方法， 其中一种方法是产生 "全局应变" ， 也即， 从衬底产生施加到整体晶 体管器件区域的应变， 全局应变是利用如下结构产生的， 例如应变 Si/SiGe弛豫层、 绝缘体上的应变 Si 等结构。 但是， 在传统的应变 Si 沟道形成方法中， 在器件制造工艺 （例如， 浅沟槽隔离 （STI ) 、 栅极 形成等）之前， 必须先在例如 SiGe层上形成应变 Si覆层。 这也导致了 存在以下问题： （ 1 )在器件制造工艺期间，应变 Si覆层可能受到损耗， 例如， STI工艺中的垫氧化处理、 栅极形成工艺前的牺牲氧化处理、 多 种湿法化学清洗处理等， 都可能导致应变 Si覆层发生损耗； （2 )应变 Si 覆层在高温步骤中可能发生弛豫 （应力被释放） ， 例如， 用于激活 源极 /漏极掺杂剂的退火处理可能会导致应变 Si覆层中的应力被释放。
一种解决方案即在去除替代栅之后， 刻蚀部分 SiGe弛豫层， 并在 去除刻蚀掉的 SiGe弛豫层的位置外延生长应变半导体层以形成沟道， 从而避免了应变半导体沟道暴露于高温的源极 /漏极退火处理， 而且由 于减少了应变半导体沟道所要经历的处理步骤， 避免了半导体层损耗。 然而， 在这种解决方案中， 是对 SiGe单一材料进行刻蚀， 由于选择比 的原因而存在刻蚀深度难以控制的问题。 尽管可以利用 SiGe形成刻蚀 停止层， 但这无疑会增加外延生长的工艺难度， 并且控制刻蚀的效果 并不明显。
发明内容
基于上述问题， 本发明提供了一种新的应变半导体沟道的形成方 法， 包括以下步骤：
在半导体衬底上形成 SiGe弛豫层；
在所述弛豫层上形成第一栅结构以及环绕所述第一栅结构的側 墙；
在所述第一栅结构两侧的弛豫层中形成源极和漏极；
在所述弛豫层、 第一栅结构和侧墙上形成层间介电层；
对所述层间介电层进行平坦化处理， 以暴露出所述第一栅结构； 去除所述第一栅结构， 以形成开口， 从而露出所述弛豫层； 在所述开口中进行离子注入以在所述弛豫层中形成离子注入区； 刻蚀所述离子注入区以在所述弛豫层中形成沟槽；
在所述沟槽中外延形成半导体外延层以构成应变半导体沟道； 以 及
在所述半导体外延层上形成第二栅结构。
本发明通过在源极 /漏极退火之后形成应变沟道， 既避免了应变半 导体沟道暴露于高温的源极 /漏极退火处理， 又由于减少了应变半导体 沟道所要经历的处理步骤， 而避免了半导体层损耗。 另外， 由于离子 注入区的刻蚀速率明显大于其周围未经过离子注入的弛豫层部分的刻 蚀速率， 故可容易的控制刻蚀深度。
附图说明
通过参考以下描述和用于示出各个实施例的附图可以最好地理解 实施例。 在附图中：
图 1是在村底上形成弛豫层后的结构的剖面图；
图 2是在弛豫层上形成第一栅结构以及側墙后的结构的剖面图； 图 3是形成层间介电层后的结构的剖面图；
图 4是进行化学机械平坦化 （CMP ) 处理后的结构的剖面图； 图 5是去除暴露出的第一栅结构后的结构的剖面图；
图 6是离子注入后的结构的剖面图；
图 7是去除离子注入区以形成沟槽后的结构的剖面图；
图 8是形成半导体外延层后的结构的剖面图； 以及
图 9是形成第二栅结构后的结构的剖面图。
具体实施方式
下面， 参考附图描述本发明的实施例的一个或多个方面， 其中在 整个附图中一般用相同的参考标记来指代相同的元件。 在下面的描述 中， 为了解释的目的， 阐述了许多特定的细节以提供对本发明实施例 的一个或多个方面的彻底理解。 然而， 对本领域技术人员来说可以说 例的一个或多个方面。
另外， 虽然就一些实施方式中的仅一个实施方式来公开实施例的 定应用来 ^可能是期望的且有利的 ^它实 方式的一个或 个其 ^特 征或方面。
首先， 在衬底 100 (例如 Si、 绝缘体上硅 （ SOI ) 等） 上形成弛豫 层 105， 如图 1所示。 所述弛豫层可以由 SiGe形成。 在 SiGe弛豫层的 实施例中， 在 SiGe弛豫层 105中， 06原子％从邻近衬底 100到远离衬 底 100的方向， 例如， 从 20%逐渐变化至 100%, 即组成 Si1-xGex中的 X从 0.2逐渐变化为 1。 在此， SiGe弛豫层 105的组成的具体数值仅用 他组成（即， 重新选定 X的变化范围）， X的逐渐变化可以是线性变化、 双曲线变化、 指数变化等多种变化形式。
然后， 在弛豫层 105 上形成第一栅结构 （作为牺牲栅叠层， 其可 以包括第一电介质层 1 10、位于第一电介质层 1 10上的第一栅层 1 15以 及帽层 123 ) 以及环绕第一电介质层 1 10和第一栅层 1 15的侧墙 120, 如图 2所示。第一电介质层 1 10—般为氧化物或氮化物形成，例如 Si02。 第一栅层 1 15例如由多晶硅形成。 所述帽层 123例如由氮化物形成。 所述側墙 120 —般为氧化物、 氮化物、 氮氧化物、 碳化物或碳氧化物 以及其他^ (氐 k 材料， 例如氮化硅。 上述结构也可以选用本领域公知的 其他材料。 作为本发明的示例， 第一电介质层 1 10的厚度为 1 ~ 5nm， 第一栅层 115的厚度为 20 ~ 70nm, 側墙 120厚度为 10 ~ 40nm。 这一 步骤是传统工艺的一部分， 这里不再赘述。
在形成第一栅结构后， 可以采用常规方法例如离子注入和高温退 火来在所述第一栅结构两侧的弛豫层中形成源极 /漏极（图中未示出）。
之后， 在所述弛豫层、 第一栅结构和侧墙上形成层间介电层 125， 如图 3 所示。 例如， 未掺杂的氧化硅、 各种掺杂的氧化硅（如硼硅玻 璃、 硼磷硅玻璃等）和氮化硅等可以作为层间介电层 125的构成材料。 形成层间介电层的方法例如可以通过沉积工艺形成， 包括但不限于化 学气相沉积（CVD )、 等离子辅助 CVD、 原子层沉积（ALD )、 蒸镀、 反应溅射、 化学溶液沉积或其他类似沉积工艺。
接下来， 对所述层间介电层进行化学机械平坦化（CMP ) 处理， 从而暴露出第一栅结构， 如图 4所示。
之后， 去除所述第一栅结构， 以形成开口， 从而露出所述弛豫层 105 , 如图 5所示。 其中， 在所述第一栅结构中存在帽层 123的情况中， 需要首先执行另外的 CMP处理或反应离子刻蚀 （RIE ) 处理， 去除帽 层。接着依次去除第一栅层 1 15和第一电介质层 110。 该步骤可用本领 域熟知的任何方法进行， 例如采用湿法刻蚀或干法刻蚀。
接下来， 在所述开口中进行离子注入以在所述弛豫层中形成离子 注入区 130, 如图 6所示。 作为本发明的示例， 所述离子注入的注入剂 为 P、 As或者二者的组合， 剂量范围为 5 χ 1013-4 χ 1015cm-3 , 注入能量 为 l-3keV。本发明的实施例易于通过控制离子注入的能量来控制深度， 例如将离子注入区 130的深度控制为 3nm-10nm。
可选地， 之后进行退火， 例如在 700-800°C的温度范围内。
接下来， 刻蚀所述离子注入区 130 以在所述弛豫层中形成沟槽， 如图 7 所示。 所述刻蚀可通过本领域公知的技术进行， 例如采用湿法 刻蚀或干法刻蚀。 例如对于 SiGe弛豫层， 可以通过使用 NF3和 Cl2的 干法刻蚀完成。 由于离子注入区 130 的刻蚀速率明显大于其周围未经 过离子注入的弛豫层部分的刻蚀速率， 故可容易的控制刻蚀深度。 适 当的沟道厚度能够达到最好的电子迁移率。
然后， 在所述沟槽中， 执行半导体外延生长， 形成半导体外延层
135 , 如图 8所示。 其中所述外延层材料的晶格常数与所述弛豫层材料 的晶格常数不同， 以构成应变半导体沟道。 外延生长例如利用金属有 机物化学气相沉积（MOCVD )或分子束外延（MBE ) 。 作为本发明的 示例， 所述半导体外延层由 Si外延层、 Ge外延层、或 SiGe外延层（其 中 Ge原子％可以自由调节） 构成， 其与 SiGe弛豫层相配合， 在形成 的外延层即沟道中引入应变， 从而提高了沟道中电子或空穴的迁移率， 有利于提高 MOS器件的性能。 半导体外延层的厚度可以在 5-10nm的 范围内。外延层 135的顶面可以与弛豫层 105的顶面在同一平面上（如 图 8 所示） ， 也可以不在同一平面上 （未示出） ， 但应该在半导体工 艺允许的误差范围内。
如果外延层为 Si， 则通常能够形成张应力沟道， 从而有利于调节 n 型器件的电子迁移率； 如果外延层为 Ge,则能够形成压应力沟道， 从而 利于调节 p型器件的空穴迁移率； 如果外延 SiGe层， 则可以通过调节 Ge的比例， 从而控制形成沟道两侧产生压应力或者张应力。 因而， 本 发明的实施例， 能够适用于 pMOSFET或 nMOSFET。
之后， 在上述结构的表面上形成第二栅电介质层 140 和第二栅层 145 , 并平坦化至所述层间介电层， 以形成第二栅结构， 如图 9所示。 形成第二栅电介质层 140和第二栅层 145 的方法例如可以通过沉积工 艺形成， 包括但不限于化学气相沉积 （CVD ) 、 等离子辅助 CVD、 原 子层沉积 （ALD ) 、 蒸镀、 反应溅射、 化学溶液沉积或其他类似沉积 工艺。所述第二栅电介质层可以由 Si02或从 Zr02、 Hf02、 A1203、 HfSiO、 HfSiON和 /或其混合物中选择的高 K电介质材料形成。 所述第二栅层 包括功函数金属栅（TiN )和金属导体层（TiAl ) , 上面可以有多晶硅。 作为本发明的一个示例，第二栅电介盾层 140的厚度可以在 1 ~ 5nm的 范围内。
此后， 可以按照传统的方法执行半导体制造工艺， 例如形成接触 孔和金属化互连等以形成 MOS器件。
本实施例通过在源极 /漏极退火之后形成应变沟道 135， 避免了在 常规 MOS 工艺中应变半导体沟道暴露于高温的源极 /漏极退火处理， 由于减少了应变半导体沟道所要经历的处理步骤， 而避免了半导体层 损耗。 另外， 由于在弛豫层中形成的离子注入区的刻蚀速率明显大于 其周围未经过离子注入的弛豫层部分的刻蚀速率， 故可容易的控制刻 蚀深度， 以便控制最后形成的沟道区的厚度， 因而能够进一步控制产 生在沟道区两侧的应力。 以上所述仅是本发明的较佳实施例， 并非对本发明作任何限制。 因此， 在不脱离本发明技术方法的原理和随附权利要求书所保护范围 的情况下， 可以对本发明做出各种修改、 变化。

Claims

权 利 要 求
1. 一种应变半导体沟道的形成方法， 包括以下步骤：
在半导体衬底上形成 SiGe弛豫层；
在所述弛豫层上形成第一栅结构以及环绕所述第一栅结构的侧 墙；
在所述第一栅结构两側的弛豫层中形成源极和漏极；
在所述弛豫层、 第一栅结构和侧墙上形成层间介电层；
对所述层间介电层进行平坦化处理， 以暴露出所述第一栅结构； 去除所述第一栅结构， 以形成开口， 从而露出所述弛豫层； 在所述开口中进行离子注入以在所述弛豫层中形成离子注入区； 刻蚀所述离子注入区以在所述弛豫层中形成沟槽；
在所述沟槽中外延形成半导体外延层以构成应变半导体沟道； 以 及
在所述半导体外延层上形成笫二栅结构。
2. 根据权利要求 1所述的应变半导体沟道的形成方法， 其中 所述半导体衬底由 Si或绝缘体上硅形成。
3. 根据权利要求 1所述的应变半导体沟道的形成方法， 其中 所述 SiGe弛豫层中 Ge原子百分比从邻近所述半导体村底的 20% 逐渐变化为远离所述半导体衬底的 100%。
4. 根据权利要求 1所述的应变半导体沟道的形成方法， 其中 所述离子注入的注入剂为 P、 As或者是二者的组合。
5. 根据权利要求 4所述的应变半导体沟道的形成方法， 其中 所述离子注入的剂量范围为 5 X 1013-4 X 1015cnT3， 注入能量为 l-3keV。
6. 根据权利要求 1所述的应变半导体沟道的形成方法， 其中 通过所述离子注入， 使得所述离子注入区的深度为 3nm-10nm。
7. 根据权利要求 1 所述的应变半导体沟道的形成方法， 其中在离 子注入之后， 还包括以下步骤：
在 700-800 °C的温度范围内进行退火。
8. 根据权利要求 1 所述的应变半导体沟道的形成方法， 其中所述 刻蚀所述离子注入区是通过使用 NF3和 Cl2的干法刻蚀完成的。
9. 根据权利要求 1所述的应变半导体沟道的形成方法， 其中所述 半导体外延层包括 Si外延层、 Ge外延层或 SiGe外延层。
10. 根据权利要求 9所述的应变半导体沟道的形成方法， 其中 所述半导体外延层的厚度在 5-10nm的范围内。
PCT/CN2011/001311 2011-06-23 2011-08-09 一种应变半导体沟道的形成方法 Ceased WO2012174689A1 (zh)

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