CN102842506B - 一种应变半导体沟道的形成方法 - Google Patents
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Abstract
本发明涉及一种应变半导体沟道的形成方法。本发明通过在源极/漏极退火之后形成应变沟道,既避免了应变半导体沟道暴露于高温的源极/漏极退火处理,又由于减少了应变半导体沟道所要经历的处理步骤,而避免了半导体层损耗。另外,由于离子注入区的刻蚀速率明显大于未经过离子注入的弛豫层部分的刻蚀速率,故可容易的控制刻蚀深度。
Description
技术领域
本发明涉及半导体领域,特别涉及一种应变半导体沟道的形成方法。
背景技术
随着器件特征尺寸的不断缩小,以提高沟道载流子迁移率为目的的应变沟道工程起到越来越重要的作用。理论和经验研究已经证实,当将应力施加到晶体管的沟道中时,晶体管的载流子迁移率会得以提高或降低;然而,还已知,电子和空穴对相同类型的应变具有不同的响应。例如,在电流流动的方向上施加压应力对空穴迁移率有利,但是对电子迁移率有害。而施加张应力对电子迁移率有利,但是对空穴迁移率有害。具体而言,对于NMOS器件,在沿沟道方向引入张应力提高了其沟道中电子的迁移率;另一方面,对于PMOS器件,在沿沟道方向引入压应力提高了其沟道中空穴的迁移率。根据这一理论,已发展了许多方法,其中一种方法是产生“全局应变”,也即,从衬底产生施加到整体晶体管器件区域的应变,全局应变是利用如下结构产生的,例如应变Si/SiGe弛豫层、绝缘体上的应变Si等结构。但是,在传统的应变Si沟道形成方法中,在器件制造工艺(例如,浅沟槽隔离(STI)、栅极形成等)之前,必须先在例如SiGe层上形成应变Si覆层。这也导致了存在以下问题:(1)在器件制造工艺期间,应变Si覆层可能受到损耗,例如,STI工艺中的垫氧化处理、栅极形成工艺前的牺牲氧化处理、多种湿法化学清洗处理等,都可能导致应变Si覆层发生损耗;(2)应变Si覆层在高温步骤中可能发生弛豫(应力被释放),例如,用于激活源极/漏极掺杂剂的退火处理可能会导致应变Si覆层中的应力被释放。
一种解决方案即在去除替代栅之后,刻蚀部分SiGe弛豫层,并在去除刻蚀掉的SiGe弛豫层的位置外延生长应变半导体层以形成沟道,从而避免了应变半导体沟道暴露于高温的源极/漏极退火处理,而且由于减少了应变半导体沟道所要经历的处理步骤,避免了半导体层损耗。然而,在这种解决方案中,是对SiGe单一材料进行刻蚀,由于选择比的原因而存在刻蚀深度难以控制的问题。尽管可以利用SiGe形成刻蚀停止层,但这无疑会增加外延生长的工艺难度,并且控制刻蚀的效果并不明显。
发明内容
基于上述问题,本发明提供了一种新的应变半导体沟道的形成方法,包括以下步骤:
在半导体衬底上形成SiGe弛豫层;
在所述弛豫层上形成第一栅结构以及环绕所述第一栅结构的侧墙;
在所述第一栅结构两侧的弛豫层中形成源极和漏极;
在所述弛豫层、第一栅结构和侧墙上形成层间介电层;
对所述层间介电层进行平坦化处理,以暴露出所述第一栅结构;
去除所述第一栅结构,以形成开口,从而露出所述弛豫层;
在所述开口中进行离子注入以在所述弛豫层中形成离子注入区;
刻蚀所述离子注入区以在所述弛豫层中形成沟槽;
在所述沟槽中外延形成半导体外延层以构成应变半导体沟道;以及
在所述半导体外延层上形成第二栅结构。
本发明通过在源极/漏极退火之后形成应变沟道,既避免了应变半导体沟道暴露于高温的源极/漏极退火处理,又由于减少了应变半导体沟道所要经历的处理步骤,而避免了半导体层损耗。另外,由于离子注入区的刻蚀速率明显大于其周围未经过离子注入的弛豫层部分的刻蚀速率,故可容易的控制刻蚀深度。
附图说明
通过参考以下描述和用于示出各个实施例的附图可以最好地理解实施例。在附图中:
图1是在衬底上形成弛豫层后的结构的剖面图;
图2是在弛豫层上形成第一栅结构以及侧墙后的结构的剖面图;
图3是形成层间介电层后的结构的剖面图;
图4是进行化学机械平坦化(CMP)处理后的结构的剖面图;
图5是去除暴露出的第一栅结构后的结构的剖面图;
图6是离子注入后的结构的剖面图;
图7是去除离子注入区以形成沟槽后的结构的剖面图;
图8是形成半导体外延层后的结构的剖面图;以及
图9是形成第二栅结构后的结构的剖面图。
具体实施方式
下面,参考附图描述本发明的实施例的一个或多个方面,其中在整个附图中一般用相同的参考标记来指代相同的元件。在下面的描述中,为了解释的目的,阐述了许多特定的细节以提供对本发明实施例的一个或多个方面的彻底理解。然而,对本领域技术人员来说可以说显而易见的是,可以利用较少程度的这些特定细节来实行本发明实施例的一个或多个方面。
另外,虽然就一些实施方式中的仅一个实施方式来公开实施例的特定特征或方面,但是这样的特征或方面可以结合对于任何给定或特定应用来说可能是期望的且有利的其它实施方式的一个或多个其它特征或方面。
首先,在衬底100(例如Si、绝缘体上硅(SOI)等)上形成弛豫层105,如图1所示。所述弛豫层可以由SiGe形成。在SiGe弛豫层的实施例中,在SiGe弛豫层105中,Ge原子%从邻近衬底100到远离衬底100的方向,例如,从20%逐渐变化至100%,即组成Si1-xGex中的x从0.2逐渐变化为1。在此,SiGe弛豫层105的组成的具体数值仅用作示例的目的,本领域普通技术人员可以根据实际需要选用适当的其他组成(即,重新选定x的变化范围),x的逐渐变化可以是线性变化、双曲线变化、指数变化等多种变化形式。
然后,在弛豫层105上形成第一栅结构(作为牺牲栅叠层,其可以包括第一电介质层110、位于第一电介质层110上的第一栅层115以及帽层123)以及环绕第一电介质层110和第一栅层115的侧墙120,如图2所示。第一电介质层110一般为氧化物或氮化物形成,例如SiO2。第一栅层115例如由多晶硅形成。所述帽层123例如由氮化物形成。所述侧墙120一般为氧化物、氮化物、氮氧化物、碳化物或碳氧化物以及其他低k材料,例如氮化硅。上述结构也可以选用本领域公知的其他材料。作为本发明的示例,第一电介质层110的厚度为1~5nm,第一栅层115的厚度为20~70nm,侧墙120厚度为10~40nm。这一步骤是传统工艺的一部分,这里不再赘述。
在形成第一栅结构后,可以采用常规方法例如离子注入和高温退火来在所述第一栅结构两侧的弛豫层中形成源极/漏极(图中未示出)。
之后,在所述弛豫层、第一栅结构和侧墙上形成层间介电层125,如图3所示。例如,未掺杂的氧化硅、各种掺杂的氧化硅(如硼硅玻璃、硼磷硅玻璃等)和氮化硅等可以作为层间介电层125的构成材料。形成层间介电层的方法例如可以通过沉积工艺形成,包括但不限于化学气相沉积(CVD)、等离子辅助CVD、原子层沉积(ALD)、蒸镀、反应溅射、化学溶液沉积或其他类似沉积工艺。
接下来,对所述层间介电层进行化学机械平坦化(CMP)处理,从而暴露出第一栅结构,如图4所示。
之后,去除所述第一栅结构,以形成开口,从而露出所述弛豫层105,如图5所示。其中,在所述第一栅结构中存在帽层123的情况中,需要首先执行另外的CMP处理或反应离子刻蚀(RIE)处理,去除帽层。接着依次去除第一栅层115和第一电介质层110。该步骤可用本领域熟知的任何方法进行,例如采用湿法刻蚀或干法刻蚀。
接下来,在所述开口中进行离子注入以在所述弛豫层中形成离子注入区130,如图6所示。作为本发明的示例,所述离子注入的注入剂为P、As或者二者的组合,剂量范围为5×1013-4×1015cm-3,注入能量为1-3keV。本发明的实施例易于通过控制离子注入的能量来控制深度,例如将离子注入区130的深度控制为3nm-10nm。
可选地,之后进行退火,例如在700-800℃的温度范围内。
接下来,刻蚀所述离子注入区130以在所述弛豫层中形成沟槽,如图7所示。所述刻蚀可通过本领域公知的技术进行,例如采用湿法刻蚀或干法刻蚀。例如对于SiGe弛豫层,可以通过使用NF3和Cl2的干法刻蚀完成。由于离子注入区130的刻蚀速率明显大于其周围未经过离子注入的弛豫层部分的刻蚀速率,故可容易的控制刻蚀深度。适当的沟道厚度能够达到最好的电子迁移率。
然后,在所述沟槽中,执行半导体外延生长,形成半导体外延层135,如图8所示。其中所述外延层材料的晶格常数与所述弛豫层材料的晶格常数不同,以构成应变半导体沟道。外延生长例如利用金属有机物化学气相沉积(MOCVD)或分子束外延(MBE)。作为本发明的示例,所述半导体外延层由Si外延层、Ge外延层、或SiGe外延层(其中Ge原子%可以自由调节)构成,其与SiGe弛豫层相配合,在形成的外延层即沟道中引入应变,从而提高了沟道中电子或空穴的迁移率,有利于提高MOS器件的性能。半导体外延层的厚度可以在5-10nm的范围内。外延层135的顶面可以与弛豫层105的顶面在同一平面上(如图8所示),也可以不在同一平面上(未示出),但应该在半导体工艺允许的误差范围内。
如果外延层为Si,则通常能够形成张应力沟道,从而有利于调节n型器件的电子迁移率;如果外延层为Ge,则能够形成压应力沟道,从而利于调节p型器件的空穴迁移率;如果外延SiGe层,则可以通过调节Ge的比例,从而控制形成沟道两侧产生压应力或者张应力。因而,本发明的实施例,能够适用于pMOSFET或nMOSFET。
之后,在上述结构的表面上形成第二栅电介质层140和第二栅层145,并平坦化至所述层间介电层,以形成第二栅结构,如图9所示。形成第二栅电介质层140和第二栅层145的方法例如可以通过沉积工艺形成,包括但不限于化学气相沉积(CVD)、等离子辅助CVD、原子层沉积(ALD)、蒸镀、反应溅射、化学溶液沉积或其他类似沉积工艺。所述第二栅电介质层可以由SiO2或从ZrO2、HfO2、Al2O3、HfSiO、HfSiON和/或其混合物中选择的高K电介质材料形成。所述第二栅层包括功函数金属栅(TiN)和金属导体层(TiAl),上面可以有多晶硅。作为本发明的一个示例,第二栅电介质层140的厚度可以在1~5nm的范围内。
此后,可以按照传统的方法执行半导体制造工艺,例如形成接触孔和金属化互连等以形成MOS器件。
本实施例通过在源极/漏极退火之后形成应变沟道135,避免了在常规MOS工艺中应变半导体沟道暴露于高温的源极/漏极退火处理,由于减少了应变半导体沟道所要经历的处理步骤,而避免了半导体层损耗。另外,由于在弛豫层中形成的离子注入区的刻蚀速率明显大于其周围未经过离子注入的弛豫层部分的刻蚀速率,故可容易的控制刻蚀深度,以便控制最后形成的沟道区的厚度,因而能够进一步控制产生在沟道区两侧的应力。
以上所述仅是本发明的较佳实施例,并非对本发明作任何限制。因此,在不脱离本发明技术方法的原理和随附权利要求书所保护范围的情况下,可以对本发明做出各种修改、变化。
Claims (9)
1.一种应变半导体沟道的形成方法,包括以下步骤:
在半导体衬底上形成SiGe弛豫层;
在所述弛豫层上形成第一栅结构以及环绕所述第一栅结构的侧墙;
在所述第一栅结构两侧的弛豫层中形成源极和漏极;
在所述弛豫层、第一栅结构和侧墙上形成层间介电层;
对所述层间介电层进行平坦化处理,以暴露出所述第一栅结构;
去除所述第一栅结构,以形成开口,从而露出所述弛豫层;
在所述开口中进行离子注入以在所述弛豫层中形成离子注入区,其中所述离子注入的注入剂为P、As或者是二者的组合;
刻蚀所述离子注入区以在所述弛豫层中形成沟槽;
在所述沟槽中外延形成半导体外延层以构成应变半导体沟道;以及
在所述半导体外延层上形成第二栅结构。
2.根据权利要求1所述的应变半导体沟道的形成方法,其中
所述半导体衬底由Si或绝缘体上硅形成。
3.根据权利要求1所述的应变半导体沟道的形成方法,其中
所述SiGe弛豫层中Ge原子百分比从邻近所述半导体衬底的20%逐渐变化为远离所述半导体衬底的100%。
4.根据权利要求1所述的应变半导体沟道的形成方法,其中
所述离子注入的剂量范围为5×1013-4×1015cm-3,注入能量为1-3keV。
5.根据权利要求1所述的应变半导体沟道的形成方法,其中
通过所述离子注入,使得所述离子注入区的深度为3nm-10nm。
6.根据权利要求1所述的应变半导体沟道的形成方法,其中在离子注入之后,还包括以下步骤:
在700-800℃的温度范围内进行退火。
7.根据权利要求1所述的应变半导体沟道的形成方法,其中所述刻蚀所述离子注入区是通过使用NF3和Cl2的干法刻蚀完成的。
8.根据权利要求1所述的应变半导体沟道的形成方法,其中所述半导体外延层包括Si外延层、Ge外延层或SiGe外延层。
9.根据权利要求8所述的应变半导体沟道的形成方法,其中
所述半导体外延层的厚度在5-10nm的范围内。
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