WO2012132207A1 - 半導体装置、半導体装置の製造方法及びsoi基板 - Google Patents
半導体装置、半導体装置の製造方法及びsoi基板 Download PDFInfo
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- WO2012132207A1 WO2012132207A1 PCT/JP2012/001161 JP2012001161W WO2012132207A1 WO 2012132207 A1 WO2012132207 A1 WO 2012132207A1 JP 2012001161 W JP2012001161 W JP 2012001161W WO 2012132207 A1 WO2012132207 A1 WO 2012132207A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device, a method for manufacturing a semiconductor device, and an SOI substrate.
- Patent Document 1 Japanese Patent Laid-Open No. 2008-227084 describes a semiconductor device in which boron as an acceptor is introduced into a region of a silicon substrate in contact with a silicon oxide film. As a result, the boron-doped layer serves as a hole source, charges can be compensated for electrons collected in the vicinity of the interface, interface carriers contributing to conduction can be reduced, and a semiconductor device with low harmonics can be realized. Has been.
- Patent Document 1 in the method of doping an acceptor by ion implantation with respect to the entire surface of the silicon oxide film interface, when the interface electron density varies in-plane, It has been found that there is a possibility that the high-frequency characteristics may deteriorate, for example, when the doping amount varies.
- Forming a first insulating layer on the silicon substrate and forming, on the silicon substrate, diffusion regions into which acceptors are introduced and non-diffusion regions in which the diffusion regions are alternately arranged and the acceptors are not introduced.
- Process Forming a wiring on the first insulating layer; A method for manufacturing a semiconductor device is provided.
- diffusion regions in which acceptors are introduced and non-diffusion regions in which no acceptors are introduced are alternately arranged on the silicon substrate.
- the diffusion region into which the acceptor is introduced becomes a p-type region.
- the non-diffusion region in which no acceptor is introduced becomes an n-type region due to interface electrons.
- p-type regions and n-type regions are formed alternately.
- electrons and holes generated near the surface of the silicon substrate are confined by the mutual band barrier. Therefore, the resistivity of the silicon substrate can be effectively increased.
- the influence can be reduced. As described above, the influence of carriers generated near the surface of the silicon substrate when a high frequency is applied can be suppressed.
- the influence of carriers generated near the surface of the silicon substrate when a high frequency is applied can be suppressed.
- FIG. 1 is a diagram illustrating a configuration of a semiconductor device according to a first embodiment. It is a sectional view for explaining a method for manufacturing a semiconductor device according to the first embodiment. It is a figure for demonstrating the effect of 1st Embodiment. It is a figure which shows the structure of the semiconductor device which concerns on 2nd Embodiment. It is a sectional view for explaining a method for manufacturing a semiconductor device according to a second embodiment. It is a figure which shows the structure of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing to which the A section of FIG. 6 was expanded. It is a top view which shows the structure of the semiconductor device which concerns on 3rd Embodiment.
- FIG. 1 is a diagram illustrating a configuration of the semiconductor device according to the first embodiment.
- FIG. 1A is a cross-sectional view showing the configuration of the semiconductor device 10.
- FIG. 1B is a plan view of the vicinity of the surface of the silicon substrate 100.
- the semiconductor device 10 has the following configuration.
- a diffusion region 220 into which an acceptor is introduced is formed.
- non-diffusion regions 240 into which no acceptor is introduced are alternately arranged with the diffusion regions 220.
- the first insulating layer 300 is provided in contact with the silicon substrate 100.
- a wiring 620 is provided on the first insulating layer 300. Details will be described below.
- the silicon substrate 100 here has a high resistivity of several k ⁇ cm or more.
- the silicon substrate 100 is formed with a diffusion region 220 into which acceptors are introduced.
- the acceptor is introduced by, for example, ion implantation.
- An example of the acceptor is B (boron).
- the diffusion region 220 is a p-type region.
- non-diffusion regions 240 into which no acceptor is introduced are alternately arranged with the diffusion regions 220.
- the non-diffusion region 240 is an n-type region due to interface electrons generated near the surface of the silicon substrate 100.
- carriers generated near the surface of the silicon substrate 100 are referred to as “interface carriers”. Note that "near the surface of the silicon substrate 100", of the vicinity of the interface between the silicon substrate 100 and the first insulating layer 300 refers to a vicinity of the interface between the silicon substrate 100 side.
- the first insulating layer 300 is provided so as to be in contact with the silicon substrate 100. Since a high-frequency signal is applied to the semiconductor device 10, the first insulating layer 300 preferably has a low dielectric constant.
- the first insulating layer 300 is, for example, a silicon oxide film. Alternatively, the first insulating layer 300 may be a stack of a plurality of types of insulating layers.
- a wiring 620 is provided on the first insulating layer 300.
- the wiring 620 is a transmission line to which a high frequency signal is applied.
- the frequency F (GHz) of the high-frequency signal applied to the wiring 620 is, for example, 0.1 (GHz) or more.
- the diffusion region 220 and the non-diffusion region 240 have long sides in a direction parallel to the extending direction of the wiring 620.
- the diffusion region 220 has a stripe shape, for example, and is arranged in parallel to the extending direction of the wiring 620.
- adjacent diffusion regions 220 are separated from each other. That is, in the range where the wiring 620 extends, there is no portion in contact with both of the adjacent diffusion regions 220 in plan view. Thereby, the carrier of the diffusion region 220 can be prevented from propagating between the adjacent diffusion regions 220 due to the high frequency signal.
- the diffusion regions 220 and the non-diffusion regions 240 are alternately arranged.
- the wirings 620 are alternately arranged in the direction perpendicular to the extending direction.
- an electric field induced by the high frequency signal is generated in the vicinity of the surface of the silicon substrate 100 in the interface direction. Accordingly, the diffusion of the interface carriers can be suppressed by alternately arranging the diffusion regions 220 and the non-diffusion regions 240 in the direction perpendicular to the extending direction of the wiring 620 in this way.
- the shorter length of the diffusion region 220 in the direction parallel or perpendicular to the extending direction of the wiring 620 is 25. / F ( ⁇ m) or less.
- the shorter length of the non-diffusion region 240 in the direction parallel or perpendicular to the extending direction of the wiring 620 is 25 / F ( ⁇ m) or less.
- the shorter length of the diffusion region 220 in the first embodiment is the length (stripe width) in the direction perpendicular to the extending direction of the diffusion region 220. The same applies to “the shorter length of the non-diffusion region 240”.
- the electric field in the interface direction generated in the vicinity of the surface of the silicon substrate 100 alternates with a period of 1 / (2F) seconds.
- the typical saturation speed of carriers in silicon is 1 ⁇ 10 7 cm / s
- the distance that carriers can travel in 1 / (2F) second is 50 / F ⁇ m at maximum. Therefore, according to the present embodiment, the shorter length of the diffusion region 220 and the shorter length of the non-diffusion region 240 are 1 ⁇ 2 the distance that the carrier can travel, that is, 25 / F ⁇ m or less. And Thereby, the probability of trapping carriers can be increased by the band barrier between the diffusion region 220 and the non-diffusion region 240.
- the reason why the distance that the carrier can travel is 1 ⁇ 2 of the distance that the carrier can travel is that, as the confinement effect, the carrier can be sufficiently confined even if the distance that the carrier can travel is 1 ⁇ 2 or less.
- the distance that the carrier can travel is 50 ⁇ m.
- the shorter length of the diffusion region 220 and the shorter length of the non-diffusion region 240 are preferably 25 ⁇ m or less.
- the shorter length of diffusion region 220 and the shorter length of non-diffusion region 240 are, for example, 1.5 ⁇ m.
- the dose amount of the acceptor in the diffusion region 220 is designed based on the area average value of the surface density of the acceptor in which the diffusion region 220 and the non-diffusion region 240 are combined.
- the interface electron surface density in the vicinity of the surface of the silicon substrate 100 is typically 5 ⁇ 10 10 cm ⁇ 2 or more and 1 ⁇ 10 11 cm ⁇ 2 or less. It exists to the extent. Therefore, the area average value of the surface density of the acceptor by adding the diffusion region 220 and the non-diffusion region 240 is about 1 ⁇ 10 10 cm ⁇ 2 to 1 ⁇ 10 12 cm ⁇ 2 .
- the dose amount of the acceptor in the diffusion region 220 is increased so that the area average value of the surface density of the acceptor is 1 ⁇ 10 12 cm ⁇ 2 or more, the number of holes in the diffusion region 220 increases, and the non-diffusion region Intrusions up to 240. In this case, hole conduction occurs in the entire region including the non-diffusion region 240, and the effective resistivity in the interface direction becomes low.
- the dose amount of the acceptor in the diffusion region 220 is lowered so that the area average value of the surface density of the acceptor is 1 ⁇ 10 10 cm ⁇ 2 or less, the interface electrons existing in the silicon substrate 100 are compensated. In the diffusion region 220, the electron conduction is dominant.
- the area average value of the surface density of the acceptor is 1 ⁇ 10 10 cm ⁇ 2 or more and 1 ⁇ 10 12 cm ⁇ 2 or less.
- the dose amount of the acceptor in the diffusion region 220 is determined in consideration of the area ratio between the diffusion region 220 and the non-diffusion region 240 so as to satisfy the area average value of the surface density of the acceptor.
- the area ratio between the diffusion region 220 and the non-diffusion region 240 is, for example, 46:54.
- the dose amount of the acceptor in the diffusion region 220 is, for example, 1.4 ⁇ 10 11 cm ⁇ 2 .
- the area average value of the surface density of the acceptor including the diffusion region 220 and the non-diffusion region 240 is 6.4 ⁇ 10 10 cm ⁇ 2 , which is close to the interface electron surface density near the surface of the silicon substrate 100. It has become. Therefore, interfacial electrons can be compensated for the entire region including the diffusion region 220 and the non-diffusion region 240.
- the interface electrons are compensated near the surface of the silicon substrate 100, and the effective resistivity can be increased.
- the resistivity of the region including the diffusion region 220 and the non-diffusion region 240 in the silicon substrate 100 is 300 ⁇ cm or more.
- FIG. 2 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment.
- the manufacturing method of the semiconductor device 10 according to the first embodiment includes the following steps. First, while forming the 1st insulating layer 300 on the silicon substrate 100, the diffusion region 220 which introduce
- an acceptor is introduced into the silicon substrate 100 in a region to be the diffusion region 220.
- the acceptor is introduced by, for example, ion implantation.
- a method is used in which the ion beam itself is scanned only in the region to be the diffusion region 220.
- a method may be used in which a resist film (not shown) having an opening right above the diffusion region 220 is patterned on the silicon substrate 100 and ion implantation is performed.
- An example of the acceptor is B (boron).
- diffusion regions 220 into which acceptors are introduced and non-diffusion regions 240 that are alternately arranged with the diffusion regions 220 and do not introduce acceptors are formed in the silicon substrate 100.
- the first insulating layer 300 is formed on the silicon substrate 100 on which the diffusion region 220 is formed.
- the first insulating layer 300 is, for example, a silicon oxide film.
- the first insulating layer 300 is formed by, for example, thermal oxidation.
- the first insulating layer 300 is formed by a CVD (Chemical Vapor Deposition) method.
- heat treatment is performed to activate the introduced acceptor.
- the heat treatment is performed, for example, by lamp annealing.
- the ion implantation region for forming the diffusion region 220 is designed in consideration of thermal diffusion by this heat treatment.
- a wiring 620 is formed on the first insulating layer 300.
- the wiring 620 is, for example, Cu or Al.
- the wiring 620 is formed by the following procedure. First, a resist film (not shown) is applied on the wiring 620 and patterned by exposure and development. Next, the wiring 620 is etched. Next, the resist film is removed. Thereby, the wiring 620 is obtained.
- the semiconductor device 10 of the first embodiment can be obtained.
- FIG. 3 is a diagram for explaining the effect of the first embodiment.
- the horizontal axis of FIG. 3 is the area average value of the surface density of the acceptor in the region where the acceptor is introduced into the silicon substrate 100 (“effective dose amount” in FIG. 3).
- the vertical axis in FIG. 3 is a transmission coefficient when a 1 GHz high frequency signal is applied to the wiring 620.
- FIG. 3 shows the results of a two-dimensional device simulation in three cases.
- white circles indicate a case where an acceptor is introduced to the entire surface of the silicon substrate 100 as a comparative example.
- it closed triangles as an example of the first embodiment, the width of the diffusion region 220 is 1.5 [mu] m, and shows a case where the width of the non-diffusion region 240 is 1.5 [mu] m.
- white squares indicate a case where the width of the diffusion region 220 is 3 ⁇ m and the width of the non-diffusion region 240 is 3 ⁇ m.
- the transfer coefficient is maximum when the area average value (effective dose amount) of the surface density of the acceptor is 6.4 ⁇ 10 10 cm ⁇ 2 . This indicates that interfacial electrons could be optimally compensated at this dose.
- the interface electron density varies for each wafer or within the wafer surface.
- it is difficult to evaluate the interface electron density in advance because the mass productivity of the semiconductor device is significantly impaired. Therefore, in the comparative example, a constant dose is introduced over the entire surface of the wafer without considering the variation in the interface electron density.
- acceptors are introduced over the entire surface of the silicon substrate 100, either one of the interfaces described above is applied to a wafer that is deviated from the interface electron density, or a part of the wafer. Carriers are generated, causing transmission loss.
- the transfer coefficient shows a higher value than the comparative example.
- the diffusion regions 220 into which acceptors are introduced and the non-diffusion regions 240 into which no acceptors are introduced are alternately arranged on the silicon substrate 100.
- the diffusion region 220 into which the acceptor is introduced becomes a p-type region.
- the non-diffusion region 240 into which no acceptor is introduced becomes an n-type region due to interface electrons. In this way, p-type regions and n-type regions are alternately arranged.
- electrons and holes generated near the surface of the silicon substrate 100 are confined by the mutual band barrier. Therefore, the resistivity of the silicon substrate 100 can be effectively increased.
- the influence can be reduced.
- the transfer coefficient is higher than that in the comparative example. Conceivable.
- the influence of carriers generated in the vicinity of the surface of the silicon substrate 100 when a high frequency is applied can be suppressed.
- FIG. 4 is a diagram illustrating a configuration of a semiconductor device according to the second embodiment.
- FIG. 4A is a cross-sectional view showing the configuration of the semiconductor device 10.
- FIG. 4B is a plan view of the vicinity of the surface of the silicon substrate 100.
- the second embodiment is the same as the first embodiment except for the following points.
- One of the diffusion region 220 and the non-diffusion region 240 is arranged in an island shape in a region where the wiring 620 is bent. Details will be described below.
- the configuration of the cross section of the semiconductor device 10 is the same as that of the first embodiment.
- the wiring 620 is bent in an L shape within the illustrated region.
- the frequency F (GHz) of the high-frequency signal applied to the wiring 620 is, for example, 0.1 (GHz) or more.
- a high-frequency signal is applied to the wiring 620, in the vicinity of the surface of the silicon substrate 100, in the interface direction, two directions orthogonal to each other in plan view (vertical direction and horizontal direction in FIG. An electric field will be generated.
- the diffusion region 220 is arranged in a rectangular island shape, for example.
- the minimum dimension of the mask pattern there is a definition of the minimum dimension of the mask pattern, and a pattern in which each island portion of the diffusion region 220 is in contact at the corner cannot be produced. Therefore, the island portions of the diffusion region 220 are separated from each other in the vicinity of the corner.
- the distance at which the islands are separated from each other in the vicinity of the corner is preferably the minimum dimension that can be designed. Thereby, it is possible to minimize the propagation of interface electrons in the non-diffusion region 240 through this gap.
- FIG. 5 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the second embodiment.
- the manufacturing method of the second embodiment in the first step, after forming the first insulating layer 300, an acceptor is introduced into the silicon substrate 100 through the first insulating layer 300 to form the diffusion region 220. Is the same as the manufacturing method of the first embodiment. Details will be described below.
- the first insulating layer 300 is formed on the silicon substrate 100 where the diffusion region 220 is not formed.
- an acceptor is introduced into the silicon substrate 100 through the first insulating layer 300 to form the diffusion region 220.
- the acceptor is introduced so that the diffusion region 220 has an island shape.
- the acceleration voltage is adjusted so that the diffusion region 220 is formed near the surface of the silicon substrate 100.
- heat treatment is performed to activate the introduced acceptor.
- the heat treatment is the same as in the first embodiment.
- a wiring 620 is formed on the first insulating layer 300. Through the above steps, the semiconductor device 10 can be obtained.
- one of the diffusion region 220 and the non-diffusion region 240 is arranged in an island shape in the region where the wiring 620 is bent.
- the region where the wiring 620 is bent when a high-frequency signal is applied to the wiring 620, in the vicinity of the surface of the silicon substrate 100, in the interface direction, in each direction before and after the wiring 620 is bent, in that direction. An electric field is generated in the vertical direction.
- the interface carrier in each direction before and after the wiring 620 bends. Can be suppressed. Therefore, even in this case, the resistivity of the silicon substrate 100 can be effectively increased.
- the acceptor is introduced into the silicon substrate 100 through the first insulating layer 300 to form the diffusion region 220.
- the position of the diffusion region 220 can be adjusted according to the pattern of the first insulating layer 300 formed in advance.
- heat treatment for acceptor activation is performed after the first insulating layer 300 is formed. Thereby, the acceptor is not excessively diffused.
- configuration of the first embodiment may be manufactured by the manufacturing method of the second embodiment.
- configuration of the second embodiment may be produced by the manufacturing method of the first embodiment.
- FIG. 6 is a diagram illustrating a configuration of the semiconductor device 10 according to the third embodiment.
- FIG. 6A is a cross-sectional view showing the configuration of the semiconductor device 10.
- FIG. 6B is a plan view of the vicinity of the surface of the silicon substrate 100.
- FIG. 6A is a cross-sectional view taken along the line BB ′ of FIG.
- the third embodiment is the same as the second embodiment except for the following points.
- This semiconductor device has the following configuration in addition to the second embodiment.
- a silicon layer 400 is provided in contact with the first insulating layer 300.
- the silicon layer 400 is provided with an element isolation region 420. Further, the silicon layer 400 is provided with a semiconductor element (40).
- An interlayer insulating layer 500 is provided on the silicon layer 400, the element isolation region 420, and the semiconductor element (40).
- the interlayer insulating layer 500 is provided with a via 540. Further, the wiring 620 is provided on the interlayer insulating layer 500 and is connected to the semiconductor element (40) via the via 540. Details will be described below.
- the diffusion region 220 is provided in the silicon substrate 100 as in the first embodiment. Further, the diffusion regions 220 and the non-diffusion regions 240 are alternately arranged.
- the length a of the island part of the diffusion region 220 is, for example, 1.5 ⁇ m. Further, the length b of the non-diffusion region is also 1.5 ⁇ m, for example.
- the diffusion regions 220 are arranged in an island shape. Furthermore, each island part of the diffusion region 220 is, for example, an octagon. Also in this case, the islands of the diffusion region 220 are separated from each other in the vicinity of a corner portion having a short side of the octagon. Moreover, the distance which each island part has mutually separated in the corner
- the first insulating layer 300 is provided on the silicon substrate 100 so as to be in contact therewith.
- the first insulating layer 300 is, for example, a silicon oxide film.
- the silicon layer 400 is provided so as to be in contact with the first insulating layer 300.
- the silicon layer 400 is a so-called SOI (Silicon On Insulator) layer. Therefore, the first insulating layer 300 described above is a buried oxide (BOX) layer. Details of the process of forming the silicon layer 400 will be described later.
- the silicon layer 400 is provided with an element isolation region 420 having an opening.
- the element isolation region 420 is, for example, STI (Shallow Trench Isolation).
- the element isolation region 420 is formed by removing the silicon layer 400 once to form an opening and then embedding it with an insulating layer.
- the element isolation region 420 is, for example, a silicon oxide film.
- FIG. 7 is an enlarged cross-sectional view of part A of FIG.
- the semiconductor element 40 is provided in the silicon layer 400.
- the semiconductor element 40 is formed in a portion where the element isolation region 420 is not formed.
- the semiconductor element 40 is, for example, a field effect transistor (FET).
- the semiconductor element 40 has the following configuration, for example.
- a source region 402 and a drain region 404 are provided in the vicinity of the interface on the interlayer insulating layer 500 side.
- a channel region (not shown) is formed between them.
- a gate insulating film 510 and a gate electrode 520 are provided on the channel region in the silicon layer 400.
- Side wall insulating films 522 are provided on the side walls on both sides of the gate insulating film 510 and the gate electrode 520.
- an interlayer insulating layer 500 is provided on the silicon layer 400, the element isolation region 420, and the semiconductor element (40).
- the interlayer insulating layer 500 is, for example, a silicon oxide film.
- the interlayer insulating layer 500 may be formed of a plurality of layers.
- a liner insulating film (not shown) located under the interlayer insulating layer 500 in FIG. 6A may be provided on the silicon layer 400, the element isolation region 420, and the semiconductor element (40).
- an etching stopper film (not shown) may be provided between an interlayer insulating layer 600 and an interlayer insulating layer 500 described later.
- the liner insulating film or the etching stopper film is, for example, a silicon nitride film having etching selectivity with respect to the silicon oxide film.
- the interlayer insulating layer 500 may be formed of the same composition as the element isolation region 420. Furthermore, an interface may not be formed between the interlayer insulating layer 500 and the element isolation region 420.
- the interlayer insulating layer 500 is provided with a via 540.
- a wiring 620 is provided over the interlayer insulating layer 500.
- the wiring 620 is connected to the above-described semiconductor element 40 through the via 540.
- the via 540 is connected to, for example, the source region 402 or the drain region 404 in the semiconductor element 40.
- the via 540 is connected to the gate electrode 520 in a region not shown in FIG.
- An interlayer insulating layer 600 is further provided in a region other than the wiring 620.
- An interlayer insulating layer 700 is provided over the interlayer insulating layer 600 and the wiring 620. Note that a via (not shown) or a wiring (not shown) connected to the wiring 620 may be provided in a region not shown in FIG.
- FIG. 8 is a plan view showing the configuration of the semiconductor device 10 according to the third embodiment.
- FIG. 8 schematically shows only the wiring in each layer.
- the semiconductor device 10 is an SPST (Single Pole Single Throw) switch circuit.
- the wiring 620 connected to the source region 402 of the semiconductor element 40 and the wiring 620 connected to the drain region 404 are alternately arranged in a comb shape.
- the gate wiring 660 connected to the gate electrode 520 is provided in a region that does not overlap with the wiring 620 connected to the source region 402 or the drain region 404 in a plan view.
- an electrode pad 640 connected to the wiring 620 is provided in the uppermost layer.
- a wiring 620 or a semiconductor element (40) to which a high-frequency signal is applied is formed in a region inside a dotted line in plan view. At least in this region, diffusion regions 220 and non-diffusion regions 240 are formed alternately. Thereby, the resistivity of the silicon substrate 100 can be effectively increased in the region where the wiring 620 or the semiconductor element (40) is provided.
- FIGS. 9 and 10 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the third embodiment.
- the manufacturing method of the third embodiment includes the following steps in addition to the steps of the first embodiment.
- the silicon layer 400 is formed so as to be in contact with the first insulating layer 300.
- an element isolation region 420 having an opening is formed in the silicon layer 400.
- a semiconductor element (40) is formed in a portion of the silicon layer 400 that is located in the opening of the element isolation region 420.
- an interlayer insulating layer 500 is formed on the silicon layer 400, the element isolation region 420, and the semiconductor element (40).
- a via 540 is formed in the interlayer insulating layer 500.
- a wiring 620 is formed on the interlayer insulating layer 500 so as to be connected to the semiconductor element (40) through the via 540. Details will be described below.
- an acceptor is introduced into the silicon substrate 100 in a region to be the diffusion region 220.
- diffusion regions 220 into which acceptors are introduced and non-diffusion regions 240 into which acceptors are not introduced are formed alternately in the silicon substrate 100.
- a bonding silicon substrate (400) having a first insulating layer 300 to be a BOX layer formed on the substrate surface is prepared.
- H + ions are ion-implanted into the bonding silicon substrate (400) in a portion on the surface side of a silicon layer 400 described later.
- the bonding silicon substrate (400) is bonded onto the silicon substrate 100.
- the two bonded substrates are heat-treated at a high temperature and bonded.
- the silicon substrate for bonding (400) is peeled off from the interface into which the H + ions have been implanted to form a silicon layer 400. Note that, instead of the above-described method of implanting H + ions, a method of polishing the bonding silicon substrate (400) may be used.
- heat treatment is performed to activate the introduced acceptor.
- the heat treatment is performed, for example, by lamp annealing.
- an element isolation region 420 is formed in the silicon layer 400.
- an STI is formed as the element isolation region 420.
- a semiconductor element (40) is formed on the silicon layer 400.
- the semiconductor element (40) has the configuration as shown in FIG. 7, it is formed by the following process.
- the gate insulating film 510 and the gate electrode 520 are formed on the silicon layer 400.
- extension regions (not shown) of the source region 402 and the drain region 404 are formed by ion implantation of impurity ions using the gate insulating film 510 and the gate electrode 520 as a mask.
- sidewall insulating films 522 are formed on the sidewalls on both sides of the gate insulating film 510 and the gate electrode 520.
- the semiconductor element 40 is formed by the above process.
- an interlayer insulating layer 500 is formed on the silicon layer 400, the element isolation region 420, and the semiconductor element (40).
- a silicon oxide film is formed on the interlayer insulating layer 500 by, for example, CVD.
- the interlayer insulating layer 500 may have a plurality of layers.
- a liner insulating film (not shown) may be formed on the silicon layer 400, the element isolation region 420, and the semiconductor element (40).
- via holes are formed in the interlayer insulating layer 500 by dry etching so as to be connected to the gate electrode 520 of the semiconductor element (40), the source region (402), or the drain region (404).
- the via hole is filled with a conductive material by a plating method.
- a via 540 connected to the gate electrode 520, the source region (402) or the drain region (404) is formed.
- An example of the conductive material is Cu.
- the conductive material and the interlayer insulating layer 500 are planarized by CMP (Chemical Mechanical Polishing).
- the interlayer insulating layer 600 and the wiring 620 are formed by the same method as the formation of the via 540 described above.
- the wiring 620 may be formed by a dual damascene method by forming an etching stopper film (not shown) between the interlayer insulating layer 600 and the interlayer insulating layer 500.
- an interlayer insulating layer 700 is formed on the interlayer insulating layer 600 and the wiring 620.
- a via (not shown) or wiring (not shown) may be formed to be connected to the wiring 620.
- the silicon layer 400 that is an SOI layer is provided so as to be in contact with the first insulating layer 300.
- a semiconductor element (40) is provided in a portion of the silicon layer 400 located in the opening of the element isolation region 420.
- the diffusion region 220 and the non-diffusion region 240 is formed so as to be arranged alternately.
- an electric field is generated in a complicated direction in plan view in the interface direction near the surface of the silicon substrate 100.
- FIG. 11 is a cross-sectional view for explaining the method for manufacturing the semiconductor device 10 according to the fourth embodiment.
- an acceptor is introduced into the silicon substrate 100 through the silicon layer 400 and the first insulating layer 300 to form the diffusion region 220. Except for this, it is the same as the third embodiment.
- SIMOX Separatation by Implanted Oxygen
- SOI substrate First, the silicon substrate 100, after injecting a high concentration of oxygen ions, by performing high-temperature annealing to form a first insulating layer 300 (BOX layer). At the same time, the silicon layer 400 is formed by restoring crystallinity.
- an acceptor is introduced into the silicon substrate 100 through the silicon layer 400 and the first insulating layer 300 to form a diffusion region 220.
- the following steps are the same as those in the third embodiment.
- an acceptor is applied to the silicon substrate 100 via the silicon layer 400 and the first insulating layer 300.
- the diffusion region 220 is formed by introduction.
- heat treatment for acceptor activation is performed after an SOI substrate including the first insulating layer 300 and the silicon layer 400 is formed. Accordingly, the acceptor is not excessively diffused by the heat treatment for forming the SOI substrate.
- SOI substrate shown in FIG. 11 (b) in FIG. 3 9 in embodiment (b), or fourth embodiment may be in the form of transaction supplied to semiconductor manufacturers.
- silicon layer 400 formation methods SOI substrate formation methods
- the other method may be used in either embodiment.
- FIGS. 12 to 15 are plan views showing the configuration of the semiconductor device according to the fifth embodiment. Except for the difference in the arrangement of the diffusion regions 220, the present embodiment is the same as the first or third embodiment.
- the wiring 620 or the semiconductor element (40) which is a transmission line to which a high frequency signal is applied Is formed.
- a diffusion region 220 is formed in this region.
- the non-diffusion region 240 is arranged in an island shape.
- the diffusion region 220 and the non-diffusion region 240 are disposed opposite to FIG. 6B in the third embodiment. Even in this case, the same effect as the third embodiment can be obtained.
- the diffusion regions 220 are arranged in an island shape.
- the area occupied by the diffusion region 220 is formed to be 50% or less of the formation region (inside the dotted line).
- the area average value of the surface density of the acceptor including the diffusion region 220 and the non-diffusion region 240 in order to set the area average value of the surface density of the acceptor including the diffusion region 220 and the non-diffusion region 240 to 1 ⁇ 10 10 cm ⁇ 2 or more and 1 ⁇ 10 12 cm ⁇ 2 or less, relatively The amount of acceptor introduced into diffusion region 220 is increased.
- the required acceptor introduction amount can be adjusted within a range in which the accuracy of the ion implantation amount can be taken high, for example, in the ion implantation apparatus to be used.
- the diffusion region 220 is formed so as to surround the non-diffusion region 240.
- the electron mobility of the carriers in the non-diffusion region 240 is higher than the mobility of holes as a carrier diffusion region 220, it is possible to more reliably suppress the electronic conduction.
- “the shorter length of the diffusion region 220” described above is the distance c in FIG.
- the distance c is 25 / F ⁇ m or less.
- the diffusion region 220 includes a plurality of island portions that are spaced apart from each other and a connection portion that is smaller in width than the island portion in plan view and is connected to the island portion.
- This connection part connects between two adjacent island parts.
- the non-diffusion region 240 is divided by the diffusion region 220.
- variety and length of a connection part are the distance of the minimum dimension which can be designed, for example.
- adjacent island portions of the diffusion region 220 are connected by a connecting portion at a distance of the smallest dimension that can be designed.
- a connecting portion at a distance of the smallest dimension that can be designed.
- FIG. 16 is a plan view showing the configuration of the semiconductor device according to the sixth embodiment.
- FIG. 16A is a plan view showing the configuration of the semiconductor device 10.
- FIG. 16B shows a region of the semiconductor device 10 where the diffusion region 220 is formed.
- the sixth embodiment is the same as the first to fifth embodiments except that the semiconductor device 10 includes a bias generation circuit 800 and a control circuit 820.
- the semiconductor device 10 includes an SP8T switch circuit.
- Branches 1 to 8 include the same cross-sectional configuration as in the third embodiment.
- the high-frequency signal passes between the ANT port and a selected port among the ports P1 to P8 via the wiring 620.
- a bias generation circuit 800 that generates a power supply voltage and a control circuit 820 that controls a high-frequency signal are provided.
- the bias circuit 800 or the control circuit 820 is connected to the gate wiring (660) in a layer not shown.
- the power supply voltage generated from the bias generation circuit 800 is supplied to the gate of the semiconductor element (40).
- the control circuit 820 is a logic circuit that controls the switch selection state of the high-frequency signal in each branch by controlling the gate bias.
- the diffusion region 220 is formed at least in the region where the branch 1 to the branch 8 are formed.
- the region (hatched portion) in which the diffusion region 220 is formed may be any pattern in the above-described embodiment, and is appropriately selected according to the pattern of the wiring 620 and the like.
- the diffusion region 220 may be provided in a region where the bias generation circuit 800 and the control circuit 820 are formed.
- the same effects as those of the first to fifth embodiments can be obtained.
- the diffusion region 220 is provided in the region where the wiring 620 or the semiconductor element (40) which is a transmission line is formed has been described. It may be a region.
- the case where the pattern of the region where the diffusion region 220 is provided is the same pattern within the region, but the above-described various patterns may be combined even within the same region. Can do.
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Abstract
Description
シリコン基板に設けられ、アクセプタが導入された拡散領域と、
前記シリコン基板に、前記拡散領域と交互に配置され、前記アクセプタが導入されていない非拡散領域と、
前記シリコン基板に接するように設けられた第1絶縁層と、
前記第1絶縁層上に設けられた配線と、
を備える半導体装置が提供される。
シリコン基板上に第1絶縁層を形成するとともに、前記シリコン基板に、アクセプタを導入する拡散領域と、当該拡散領域と交互に配置され、前記アクセプタを導入しない非拡散領域と、を形成する第1工程と、
前記第1絶縁層上に配線を形成する工程と、
を備える半導体装置の製造方法が提供される。
シリコン基板に、アクセプタが導入された拡散領域と、
前記シリコン基板に、前記拡散領域と交互に配置され、前記アクセプタが導入されていない非拡散領域と、
前記シリコン基板上に接するように設けられた第1絶縁層と、
前記第1絶縁層上に接するように設けられたシリコン層と、
を備えるSOI基板が提供される。
図1は、第1の実施形態に係る半導体装置の構成を示す図である。なお、図1(a)は、半導体装置10の構成を示す断面図である。また、図1(b)は、シリコン基板100の表面付近の平面図である。この半導体装置10は、以下のような構成を備えている。シリコン基板100には、アクセプタが導入された拡散領域220が形成されている。また、シリコン基板100には、アクセプタが導入されていない非拡散領域240が、拡散領域220と交互に配置されている。また、第1絶縁層300は、シリコン基板100に接するように設けられている。さらに、第1絶縁層300上には、配線620が設けられている。以下、詳細を説明する。
図4は、第2の実施形態に係る半導体装置の構成を示す図である。なお、図4(a)は、半導体装置10の構成を示す断面図である。また、図4(b)は、シリコン基板100の表面付近の平面図である。第2の実施形態は、以下の点を除いて、第1の実施形態と同様である。拡散領域220または非拡散領域240の一方は、配線620が屈曲する領域において、島状に配置されている。以下、詳細を説明する。
図6は、第3の実施形態に係る半導体装置10の構成を示す図である。なお、図6(a)は、半導体装置10の構成を示す断面図である。また、図6(b)は、シリコン基板100の表面付近の平面図である。また、図6(a)は、後述する図8のB-B'の断面図である。
次に、図11を用いて、第4の実施形態に係る半導体装置10の製造方法を説明する。図11は、第4の実施形態に係る半導体装置10の製造方法を説明するための断面図である。第4の実施形態は、第1工程において、シリコン層400を形成した後、シリコン層400および第1絶縁層300を介して、シリコン基板100にアクセプタを導入して拡散領域220を形成する点を除いて、第3の実施形態と同様である。
次に、図12から図15を用いて、第5の実施形態に係る半導体装置10を説明する。図12から図15は、第5の実施形態に係る半導体装置の構成を示す平面図である。拡散領域220の配置が異なる点を除いて、第1または第3の実施形態と同様である。
次に、図16を用いて、第6の実施形態に係る半導体装置10を説明する。図16は、第6の実施形態に係る半導体装置の構成を示す平面図である。なお、図16(a)は、半導体装置10の構成を示す平面図である。また、図16(b)は、半導体装置10のうち、拡散領域220が形成されている領域を示している。第6の実施形態は、半導体装置10に、バイアス発生回路800および制御回路820を備えている点を除いて、第1から第5の実施形態と同様である。
Claims (16)
- シリコン基板に設けられ、アクセプタが導入された拡散領域と、
前記シリコン基板に、前記拡散領域と交互に配置され、前記アクセプタが導入されていない非拡散領域と、
前記シリコン基板に接するように設けられた第1絶縁層と、
前記第1絶縁層上に設けられた配線と、
を備える半導体装置。 - 請求項1に記載の半導体装置において、
前記第1絶縁層上に接するように設けられたシリコン層と、
前記シリコン層に設けられた素子分離領域と、
前記シリコン層に設けられた半導体素子と、
前記シリコン層、前記素子分離領域および前記半導体素子上に設けられた層間絶縁層と、
前記層間絶縁層に設けられたビアと、
を備え、
前記配線は、前記層間絶縁層上に設けられ、前記ビアを介して前記半導体素子と接続している半導体装置。 - 請求項1または2に記載の半導体装置において、
前記配線に印加される高周波信号の周波数をF(GHz)としたとき、前記配線の延伸方向に対して平行または垂直な方向のうち、前記拡散領域の短い方の長さは、25/F(μm)以下であり、
前記配線の延伸方向に対して平行または垂直な方向のうち、前記非拡散領域の短い方の長さは、25/F(μm)以下である半導体装置。 - 請求項1~3のいずれか一項に記載の半導体装置において、
前記拡散領域と前記非拡散領域は、前記配線の延伸方向に対して、平行な方向に長辺を備える半導体装置。 - 請求項1~4のいずれか一項に記載の半導体装置において、
拡散領域または非拡散領域の一方は、前記配線が屈曲する領域において島状に配置されている半導体装置。 - 請求項1~5のいずれか一項に記載の半導体装置において、
前記拡散領域は、
各々に離間して配置した複数の島部と、
平面視で前記島部よりも幅が小さく、前記島部と接続する接続部と、
を備え、
前記非拡散領域は、前記拡散領域によって区切られている半導体装置。 - 請求項1~6のいずれか一項に記載の半導体装置において、
前記拡散領域と前記非拡散領域を合わせた前記アクセプタの面密度の面積平均値は、1×1010cm-2以上1×1012cm-2以下である半導体装置。 - 請求項1~7のいずれか一項に記載の半導体装置において、
前記シリコン基板のバルク抵抗率は、300Ωcm以上である半導体装置。 - 請求項1~8のいずれか一項に記載の半導体装置において、
前記配線に印加される高周波信号の周波数は、0.1GHz以上である半導体装置。 - 請求項9に記載の半導体装置において、
電源電圧を発生させるバイアス発生回路と、
前記高周波信号を制御する制御回路と、
を備え、
前記バイアス回路または前記制御回路は前記配線と接続している半導体装置。 - シリコン基板上に第1絶縁層を形成するとともに、前記シリコン基板に、アクセプタを導入する拡散領域と、当該拡散領域と交互に配置され、前記アクセプタを導入しない非拡散領域と、を形成する第1工程と、
前記第1絶縁層上に配線を形成する工程と、
を備える半導体装置の製造方法。 - 請求項11に記載の半導体装置の製造方法において、
前記第1工程において、前記第1絶縁層上に接するようにシリコン層を形成する工程を含み、
前記シリコン層に素子分離領域を形成する工程と、
前記シリコン層に半導体素子を形成する工程と、
前記シリコン層、前記素子分離領域および前記半導体素子上に層間絶縁層を形成する工程と、
前記層間絶縁層にビアを形成する工程と、
前記層間絶縁層上に、前記配線を、前記ビアを介して前記半導体素子と接続するように形成する工程と、
を備える半導体装置の製造方法。 - 請求項11または12に記載の半導体装置の製造方法において、
前記第1工程において、前記シリコン基板に前記アクセプタを導入して前記拡散領域を形成した後、前記シリコン基板上に前記第1絶縁層を形成する半導体装置の製造方法。 - 請求項11または12に記載の半導体装置の製造方法において、
前記第1工程において、前記第1絶縁層を形成した後、前記第1絶縁層を介して、前記シリコン基板に前記アクセプタを導入して前記拡散領域を形成する半導体装置の製造方法。 - 請求項12に記載の半導体装置の製造方法において、
前記第1工程において、前記シリコン層を形成した後、前記シリコン層および前記第1絶縁層を介して、前記シリコン基板に前記アクセプタを導入して前記拡散領域を形成する半導体装置の製造方法。 - シリコン基板に、アクセプタが導入された拡散領域と、
前記シリコン基板に、前記拡散領域と交互に配置され、前記アクセプタが導入されていない非拡散領域と、
前記シリコン基板上に接するように設けられた第1絶縁層と、
前記第1絶縁層上に接するように設けられたシリコン層と、
を備えるSOI基板。
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JP2000323658A (ja) * | 1999-05-10 | 2000-11-24 | Nec Corp | 高周波半導体装置 |
JP2008108799A (ja) * | 2006-10-24 | 2008-05-08 | Sony Corp | 半導体装置 |
JP2008282988A (ja) * | 2007-05-10 | 2008-11-20 | Sanyo Electric Co Ltd | 半導体装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6373121B1 (en) * | 2001-03-23 | 2002-04-16 | United Microelectronics Corp. | Silicon chip built-in inductor structure |
TWI300617B (en) * | 2002-11-15 | 2008-09-01 | Via Tech Inc | Low substrate loss inductor |
US7247922B2 (en) * | 2004-09-24 | 2007-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Inductor energy loss reduction techniques |
JP2007096211A (ja) * | 2005-09-30 | 2007-04-12 | Ricoh Co Ltd | 半導体装置 |
US7554137B2 (en) * | 2005-10-25 | 2009-06-30 | Infineon Technologies Austria Ag | Power semiconductor component with charge compensation structure and method for the fabrication thereof |
-
2012
- 2012-02-21 WO PCT/JP2012/001161 patent/WO2012132207A1/ja active Application Filing
- 2012-02-21 JP JP2013507097A patent/JP5665970B2/ja not_active Expired - Fee Related
- 2012-02-21 US US14/006,939 patent/US20140015091A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH08222696A (ja) * | 1995-02-13 | 1996-08-30 | Nec Corp | 半導体集積回路 |
JPH08316420A (ja) * | 1995-05-23 | 1996-11-29 | Hitachi Ltd | 半導体装置 |
JPH0974102A (ja) * | 1995-09-04 | 1997-03-18 | Mitsubishi Electric Corp | 高周波回路装置およびその製造方法 |
JP2000323658A (ja) * | 1999-05-10 | 2000-11-24 | Nec Corp | 高周波半導体装置 |
JP2008108799A (ja) * | 2006-10-24 | 2008-05-08 | Sony Corp | 半導体装置 |
JP2008282988A (ja) * | 2007-05-10 | 2008-11-20 | Sanyo Electric Co Ltd | 半導体装置 |
Also Published As
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JPWO2012132207A1 (ja) | 2014-07-24 |
US20140015091A1 (en) | 2014-01-16 |
JP5665970B2 (ja) | 2015-02-04 |
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