WO2012117439A1 - Dispositif semiconducteur à couches minces et procédé de fabrication de celui-ci - Google Patents

Dispositif semiconducteur à couches minces et procédé de fabrication de celui-ci Download PDF

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Publication number
WO2012117439A1
WO2012117439A1 PCT/JP2011/001157 JP2011001157W WO2012117439A1 WO 2012117439 A1 WO2012117439 A1 WO 2012117439A1 JP 2011001157 W JP2011001157 W JP 2011001157W WO 2012117439 A1 WO2012117439 A1 WO 2012117439A1
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WO
WIPO (PCT)
Prior art keywords
thin film
semiconductor device
layer
crystalline silicon
protective layer
Prior art date
Application number
PCT/JP2011/001157
Other languages
English (en)
Japanese (ja)
Inventor
孝啓 川島
永井　久雄
悠治 岸田
佐藤　栄一
玄士朗 河内
Original Assignee
パナソニック株式会社
パナソニック液晶ディスプレイ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社, パナソニック液晶ディスプレイ株式会社 filed Critical パナソニック株式会社
Priority to PCT/JP2011/001157 priority Critical patent/WO2012117439A1/fr
Priority to PCT/JP2012/001332 priority patent/WO2012117718A1/fr
Priority to JP2013502190A priority patent/JPWO2012117718A1/ja
Priority to US13/984,931 priority patent/US9178075B2/en
Publication of WO2012117439A1 publication Critical patent/WO2012117439A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to a thin film semiconductor device and a manufacturing method thereof, and more particularly to a channel protection type (etching stopper type) thin film semiconductor device used in an active matrix organic EL display device and a manufacturing method thereof.
  • a channel protection type (etching stopper type) thin film semiconductor device used in an active matrix organic EL display device and a manufacturing method thereof.
  • One aspect of a thin film semiconductor device is formed on a gate electrode formed on a substrate, a gate insulating film formed to cover the substrate on which the gate electrode is formed, and the gate insulating film.
  • a crystalline silicon thin film having a channel region, a channel protective layer formed on the crystalline silicon thin film including the channel region and containing an organic material containing silicon, oxygen, and carbon, a channel region of the crystalline silicon thin film, and the Formed at the interface with the channel protective layer, containing carbon as a main component, and the carbon as the main component is an interface layer made of carbon derived from the organic material, and the channel protective layer above the channel region via the channel protective layer
  • the concentration of sulfur contained in the interface layer is preferably 100 times or more the concentration of sulfur as an impurity contained in the crystalline silicon thin film. In one embodiment of the thin film semiconductor device according to the present invention, the concentration of sulfur contained in the interface layer is preferably 5 ⁇ 10 19 [atoms / cm 3 ] or more.
  • the interface layer preferably contains sulfur.
  • each of the pair of contact layers 7 is formed so as to straddle the channel protective layer 5 and the semiconductor layer 4.
  • the upper and side surfaces of the channel protective layer 5, the side surfaces of the interface layer 6, and the semiconductor layer 4 is formed so as to cover the upper surface.
  • the pair of contact layers 7 is, for example, an n-type semiconductor layer in which amorphous silicon is doped with phosphorus (P) as an impurity, and n containing a high-concentration impurity of 1 ⁇ 10 19 [atm / cm 3 ] or more. + Layer.
  • the film thickness of the contact layer 7 is, for example, 5 nm to 100 nm.
  • the source electrode 8s and the drain electrode 8d have a single layer structure or a multilayer structure such as a conductive material and an alloy, respectively.
  • a conductive material and an alloy for example, aluminum (Al), molybdenum (Mo), tungsten (W), copper It is comprised with materials, such as (Cu), titanium (Ti), and chromium (Cr).
  • the source electrode 8s and the drain electrode 8d are formed by a three-layer structure of MoW / Al / MoW.
  • the film thickness of the source electrode and the drain electrode is, for example, about 100 nm to 500 nm.
  • the pair of amorphous silicon layers 70 are formed above the channel region of the semiconductor layer 4 via the channel protective layer 5.
  • the pair of amorphous silicon layers 70 are arranged to face each other with a predetermined interval.
  • FIG. 2B is a cross-sectional view schematically showing a configuration of a thin film semiconductor device 10B according to another modification of the present invention.
  • FIG. 2B the same components as those shown in FIG.
  • the interface layer 6 is not removed by the development processing when the channel protective layer 5 is patterned, and the interface layer 6 in a region not covered with the channel protective layer 5 is exposed.
  • the interface layer 6 has a higher carbon concentration and sulfur concentration than the other layers, and the carbon concentration contained in the interface layer 6 is 5 ⁇ 10 20 [atoms / cm 3 ] or more. In addition, it can be seen that the concentration of sulfur contained in the interface layer 6 is 5 ⁇ 10 19 [atoms / cm 3 ] or more.
  • the carbon concentration contained in the interface layer 6 is 50 times or more the carbon concentration as an impurity contained in the semiconductor layer 4. It can also be seen that the sulfur concentration contained in the interface layer 6 is 100 times or more the sulfur concentration as impurities contained in the semiconductor layer 4.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

Le dispositif comprend : une électrode de grille (2) formée sur un substrat (1) ; un film d'isolation de grille (3) formé pour recouvrir le substrat (1) sur lequel est formée l'électrode de grille (2) ; une couche semiconductrice (4) qui est formée sur le film d'isolation de grille (3) et qui comprend une couche mince de silicium cristallin qui possède une région de canal prédéterminée ; une couche de protection de canal (5) qui contient un matériau organique contenant du silicium, de l'oxygène et du carbone et qui est formée sur la couche semiconductrice (4) contenant une région de canal ; une couche d'interface (6) qui consiste principalement en carbone issu du matériau organique constituant la couche de protection de canal (5) et qui est formée à l'interface entre la région de canal de la couche semiconductrice (4) et la couche de protection de canal (5) ; une électrode de source (8s) formée au-dessus de la région de canal, avec la couche de protection de canal (5) interposée entre elles ; et une électrode de drain (8d) disposée, à l'opposé de l'électrode de source (8s), au-dessus de la région de canal, la couche de protection de canal (5) étant interposée entre elles.
PCT/JP2011/001157 2011-02-28 2011-02-28 Dispositif semiconducteur à couches minces et procédé de fabrication de celui-ci WO2012117439A1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
PCT/JP2011/001157 WO2012117439A1 (fr) 2011-02-28 2011-02-28 Dispositif semiconducteur à couches minces et procédé de fabrication de celui-ci
PCT/JP2012/001332 WO2012117718A1 (fr) 2011-02-28 2012-02-27 Dispositif à semi-conducteur en couche mince et procédé pour sa fabrication
JP2013502190A JPWO2012117718A1 (ja) 2011-02-28 2012-02-27 薄膜半導体装置及びその製造方法
US13/984,931 US9178075B2 (en) 2011-02-28 2012-02-27 Thin-film semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2011/001157 WO2012117439A1 (fr) 2011-02-28 2011-02-28 Dispositif semiconducteur à couches minces et procédé de fabrication de celui-ci

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WO2012117439A1 true WO2012117439A1 (fr) 2012-09-07

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PCT/JP2012/001332 WO2012117718A1 (fr) 2011-02-28 2012-02-27 Dispositif à semi-conducteur en couche mince et procédé pour sa fabrication

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JP (1) JPWO2012117718A1 (fr)
WO (2) WO2012117439A1 (fr)

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CN102738007B (zh) * 2012-07-02 2014-09-03 京东方科技集团股份有限公司 一种薄膜晶体管的制造方法及阵列基板的制造方法
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CN103178119B (zh) * 2013-03-25 2015-07-29 京东方科技集团股份有限公司 阵列基板、阵列基板制备方法以及显示装置
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JP6509740B2 (ja) * 2013-11-28 2019-05-08 国立大学法人東北大学 半導体素子の製造方法
JP6436660B2 (ja) 2014-07-07 2018-12-12 三菱電機株式会社 薄膜トランジスタ基板およびその製造方法
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CN105514127A (zh) * 2016-02-25 2016-04-20 昆山龙腾光电有限公司 氧化物薄膜晶体管阵列基板及制作方法与液晶显示面板
CN108885987A (zh) * 2016-03-14 2018-11-23 国立大学法人北陆先端科学技术大学院大学 层叠体、蚀刻掩模、层叠体的制造方法、蚀刻掩模的制造方法、及薄膜晶体管的制造方法
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US20130320339A1 (en) 2013-12-05
WO2012117718A1 (fr) 2012-09-07
US9178075B2 (en) 2015-11-03
JPWO2012117718A1 (ja) 2014-07-07

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