WO2012083600A1 - 控制金属硅化物横向侵入沟道区的方法 - Google Patents

控制金属硅化物横向侵入沟道区的方法 Download PDF

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Publication number
WO2012083600A1
WO2012083600A1 PCT/CN2011/070698 CN2011070698W WO2012083600A1 WO 2012083600 A1 WO2012083600 A1 WO 2012083600A1 CN 2011070698 W CN2011070698 W CN 2011070698W WO 2012083600 A1 WO2012083600 A1 WO 2012083600A1
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Prior art keywords
sacrificial
sidewall
semiconductor substrate
gate
stack structure
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English (en)
French (fr)
Inventor
罗军
赵超
钟汇才
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/063,922 priority Critical patent/US8536053B2/en
Publication of WO2012083600A1 publication Critical patent/WO2012083600A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0112—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors using conductive layers comprising silicides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Definitions

  • the present invention relates to the field of semiconductor fabrication, and more particularly to a method of controlling lateral intrusion of metal silicide into a channel region during fabrication of a MOSFET.
  • a common method of reducing the contact resistance is to form a metal silicide on the contact electrode of the device.
  • 1 to 3 show a prior art method for forming a metal silicide by taking a MOS field effect transistor as an example.
  • a semiconductor substrate 10 is provided, on which a MOS field effect transistor is formed, the MOS field effect transistor including a gate stack structure 11 and a source region 12 in a semiconductor substrate 10 on both sides of the gate stack structure 11. And a drain region 13, wherein the gate stack structure 11 mainly includes a gate dielectric layer 11a and a gate electrode lib, and sidewall spacers 11c located on the sidewalls of the gate dielectric layer 11a and the gate electrode lib, the gate dielectric layer 11a- Typically, the gate electrode lib is typically polysilicon, and the sidewall spacer 11c is typically a silicon oxide or silicon nitride or a stacked structure of the two.
  • a metal layer 14 is deposited to cover the surface of the semiconductor substrate 10 and the gate stack structure 11.
  • the material of the metal layer 14 is generally selected from a nickel-based metal such as nickel, a nickel-platinum alloy or the like to form a nickel-based metal silicide (Ni).
  • Ni nickel-based metal
  • -based silicide such as NiSi, NiPtSi, NiCoSi, NiPtCoSi, etc.
  • the semiconductor substrate 10 is subjected to heat treatment such as annealing or the like to make the metal layer
  • the metal layer 14 reacts with the surface of the source region 12 and the drain region 13 of the silicon material, and the surface of the gate electrode lib of the polysilicon material to produce a metal silicide 14a having a lower resistivity, and the spacer 11c is a dielectric material, not The metal layer 14 reacts.
  • the unreacted metal layer 14 is removed to complete the metal silicide formation process. Still referring to FIGS. 2 and 3, during the formation of the metal silicide 14a, the side walls 11c and other metals in the metal layer 14 that does not react with the semiconductor substrate 10 are laterally diffused so that they are formed in the source region 12. And the metal silicide 14a on the drain region 13 is grown in the region 15 below the spacer 11c, even into the semiconductor substrate 10 under the gate dielectric layer 11a, that is, in the channel region of the MOS field effect transistor, resulting in The gate electrode leakage current increases, the reliability of the device decreases, and may even cause a short circuit between the source region 12 and the drain region 13, which seriously affects the performance of the device. For MOS field effect transistors formed on silicon-on-insulator (SOI), since the silicon material used in the device itself is very limited, the lateral growth of metal silicide has a more serious effect on device performance.
  • SOI silicon-on-insulator
  • the problem solved by the present invention is that lateral growth occurs in the formation of metal silicide in the prior art, which affects device performance.
  • the present invention provides a method of controlling lateral intrusion of a metal silicide into a channel region, including:
  • a gate stack structure is formed on the bottom of the semiconductor village, and an active region and a drain region are formed in a semiconductor village on both sides of the gate stack structure;
  • the sacrificial sidewall and the reaction product of the sacrificial sidewall and the metal layer and the unreacted metal layer are removed.
  • the semiconductor substrate is a silicon village bottom, a silicon fault bottom, a III-V element compound compound bottom or a silicon-on-insulator structure.
  • the material of the metal layer is selected from the group consisting of titanium (Ti), cobalt (Co), nickel (Ni), nickel-platinum alloy (Ni-Pt), nickel-cobalt alloy (Ni-Co) or nickel-platinum-cobalt alloy ( One of Ni-Co-Pt).
  • the material of the sacrificial sidewall is selected from the group consisting of (Ge), tin (Sn), or silicon germanium (Si ⁇ Ge).
  • the sacrificial sidewalls are removed using wet etching, and the reaction products of the sacrificial sidewalls and the metal layer.
  • the unreacted metal layer is removed using a wet etch.
  • the reaction solution used in the wet etching includes one of H 2 O 2 , HC1, H 2 S0 4 , NH 4 OH, HNO 3 or a mixture of any one of them.
  • the forming a sacrificial sidewall on the sidewall of the gate stack structure on the semiconductor substrate comprises:
  • the sacrificial layer is etched back to remove the sacrificial layer of the semiconductor substrate surface and the surface of the gate stack structure, and sacrificial sidewalls are formed on sidewalls of the gate stack structure.
  • the gate stack structure includes a gate dielectric layer in a front gate process, a gate electrode on the gate dielectric layer, and a dielectric spacer on a sidewall of the gate dielectric layer and the gate electrode, the sacrificial side A wall is formed on an outer side wall of the side wall of the medium.
  • the gate stack structure includes a gate dielectric layer in a front gate process and a gate electrode on the gate dielectric layer, the sacrificial sidewalls being formed on sidewalls of the gate dielectric layer and the gate electrode, After removing the sacrificial sidewall, the method further includes:
  • a dielectric spacer is formed on sidewalls of the gate dielectric layer and the gate electrode.
  • the gate stack structure comprises a dummy gate electrode in a back gate process and a dielectric spacer on a sidewall of the dummy gate electrode, and the sacrificial sidewall is formed on an outer sidewall of the dielectric spacer.
  • the gate stack structure includes a dummy gate electrode in the back gate process, and the sacrificial sidewall spacer is formed on a sidewall of the dummy gate electrode.
  • the method further includes:
  • a dielectric spacer is formed on a sidewall of the dummy gate electrode.
  • all or part of the metal layer on the sacrificial side wall reacts with the sacrificial sidewall.
  • the technical solution first forms a sacrificial sidewall on the sidewall of the gate stack structure; then depositing a metal layer covering the surface of the semiconductor substrate, the gate stack structure and the sacrificial sidewall; and then heat treating the semiconductor substrate Reacting between the metal layer and the semiconductor substrate of the source region and the drain region and the sacrificial sidewall; finally removing the sacrificial sidewall, and the reaction product of the sacrificial sidewall and the metal layer and unreacted Metal layer.
  • the metal layer on the sacrificial side wall reacts with the sacrificial sidewall, which is beneficial to weaken or avoid lateral growth of the metal silicide, improve device performance and Rely on sex.
  • the technical solution can be applied to both the front gate process and the back gate process, and has high industrial availability.
  • the thickness of the sacrificial sidewall may be controlled such that all or part of the metal layer on the side wall of the sacrificial side wall reacts with the sacrificial sidewall during the heat treatment, that is, all or part of it is consumed.
  • the source-drain parasitic series resistance is reduced.
  • 1 to 3 are cross-sectional views showing an intermediate structure of a prior art method for controlling lateral intrusion of a metal silicide into a channel region;
  • FIG. 4 is a schematic flow chart of a specific embodiment of a method for controlling lateral intrusion of a metal silicide into a channel region according to the present invention
  • 5 to 10 are cross-sectional views showing an intermediate structure of a first embodiment of the method for controlling lateral intrusion of a metal silicide into a channel region of the present invention
  • 11 to 16 are cross-sectional views showing an intermediate structure of a second embodiment of the method for controlling lateral intrusion of a metal silicide into a channel region of the present invention
  • 17 to 24 are cross-sectional views showing an intermediate structure of a third embodiment of the method for controlling lateral intrusion of a metal silicide into a channel region of the present invention.
  • the metal silicide undergoes lateral growth during formation, and enters into the underside of the sidewall and even in the channel region, which affects the reliability and performance of the device.
  • the technical solution first forms a sacrificial sidewall on the sidewall of the gate stack structure; then depositing a metal layer covering the surface of the semiconductor substrate, the gate stack structure and the sacrificial sidewall; and then heat treating the semiconductor substrate Reacting between the metal layer and the semiconductor substrate of the source region and the drain region and the sacrificial sidewall; finally removing the sacrificial sidewall, and the reaction product of the sacrificial sidewall and the metal layer and unreacted Metal layer.
  • the metal layer on the sacrificial side wall reacts with the sacrificial sidewall, which helps to reduce or avoid lateral growth of the metal silicide and improve device performance and reliability.
  • the technical solution can be applied to both the front gate process and the back gate process, and has high industrial availability.
  • the thickness of the sacrificial sidewall may be controlled such that all or part of the metal layer on the side wall of the sacrificial side wall reacts with the sacrificial sidewall during the heat treatment, that is, all or part of it is consumed.
  • the source-drain parasitic series resistance is reduced.
  • FIG. 4 is a flow chart showing a specific implementation of a method for controlling lateral intrusion of a metal silicide into a channel region of the present invention, including:
  • Step S21 providing a semiconductor substrate, a gate stack structure is formed on the semiconductor substrate, and an active region and a drain region are formed in a semiconductor village on both sides of the gate stack structure;
  • Step S22 forming a sacrificial sidewall on the sidewall of the gate stack structure on the semiconductor substrate; step S23, depositing a metal layer covering the surface of the semiconductor substrate, the gate stack structure and the sacrificial sidewall;
  • Step S24 performing heat treatment on the semiconductor substrate to cause a reaction between the metal layer and the semiconductor substrate of the source region and the drain region and the sacrificial sidewall;
  • Step S25 removing the sacrificial sidewall and the reaction product of the sacrificial sidewall and the metal layer and the unreacted metal layer.
  • FIG. 10 are cross-sectional views showing an intermediate structure of a first embodiment of a method for controlling lateral intrusion of a metal silicide into a channel region according to the present invention
  • a first embodiment is a method for forming a front gate process of a MOS field effect transistor
  • the technical solution of the embodiment is also applicable to other semiconductors such as a Schottky barrier S/D MOSFET and a metal source/drain MOS field effect transistor (metallic S/D MOSFET).
  • the formation of metal silicide on the device will be described in detail below with reference to Figs. 4 and 5 to 10.
  • step S21 is performed to provide a semiconductor substrate.
  • a gate stack structure is formed on the semiconductor substrate, and active and drain regions are formed in the semiconductor substrate on both sides of the gate stack structure.
  • a semiconductor village bottom 20 is provided, and the semiconductor village bottom 20 may be a silicon village bottom.
  • a gate stack structure 21 is formed on the semiconductor substrate 20, and an active region 22 and a drain region 23 are formed in the semiconductor substrate 20 on both sides of the gate stack structure 21.
  • the gate stack structure 21 includes a gate dielectric layer 21a and a gate electrode 21b formed over the gate dielectric layer 21a, and a dielectric spacer 21c located on the sidewalls of the gate dielectric layer 21a and the gate electrode 21b.
  • the material of the gate dielectric layer 21a may be silicon oxide
  • the material of the gate electrode 21b may be polysilicon
  • the material of the dielectric spacer 21c may be a stacked structure of silicon oxide or silicon nitride or both.
  • step S22 is performed to form a sacrificial sidewall on the sidewall of the gate stack structure on the semiconductor substrate.
  • a sacrificial layer 24 is formed to cover the surface of the semiconductor substrate 20 and the surface and sidewalls of the gate stack structure 21.
  • the material of the sacrificial layer 24 may be erbium, tin or tantalum silicide (Si ⁇ GeJ, etc., or other material capable of reacting with the metal material used in the metal silicide when heated, and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like.
  • the sacrificial layer is etched back, the sacrificial layer of the surface of the semiconductor substrate 20 and the surface of the gate stack 21 is removed, and the sacrificial sidewall 24a is formed on the sidewall of the gate stack 21. Specifically, the sacrificial sidewall 24a is located on a peripheral sidewall of the dielectric sidewall 21c.
  • step S23 is performed to deposit a metal layer covering the surface of the semiconductor substrate, the gate stack structure, and the sacrificial sidewall.
  • a metal layer 25 is deposited covering the surface of the semiconductor substrate 20, the gate stack structure 21, and the sacrificial sidewall 24a.
  • the material of the metal layer 25 may be one of titanium, cobalt, nickel, nickel platinum alloy, nickel cobalt alloy or nickel cobalt platinum alloy, which may be formed by physical vapor deposition.
  • step S24 is performed to heat-treat the semiconductor substrate to cause a reaction between the metal layer and the semiconductor substrate and the sacrificial sidewall of the source region and the drain region.
  • the semiconductor substrate 20 is subjected to a heat treatment, such as annealing, to cause the metal layer 25 to react with materials in the source region 22, the drain region 23, and the sacrificial sidewall 24a, in the source region 22
  • the drain region 23 and the surface of the gate electrode 21b form a metal silicide 25a.
  • the metal layer 25 above the sacrificial sidewall 24a and the sacrificial side reacts and is consumed, which can effectively slow down or avoid lateral diffusion of metal elements.
  • the lateral diffusion of the metal element can be substantially avoided by increasing the thickness of the sacrificial spacer 24a such that the metal layer 25 above the sacrificial spacer 24a is completely consumed;
  • the metal layer 25 above the sacrificial spacer 24a may be partially consumed by reducing the thickness of the sacrificial spacer 24a, so that a moderate lateral diffusion phenomenon occurs in the metal element, so that the metal silicide 25a is laterally
  • the growth extends into the lower region 26 of the sacrificial sidewall 24a, but does not extend below the sidewall 21c, which facilitates the formation of the source region 22 and the drain region 23 after subsequent removal of the sacrificial sidewall 24a.
  • the coverage area of the metal silicide 25a reduces the source-drain parasitic series resistance.
  • step S25 is performed to remove the sacrificial sidewall and the reaction product of the sacrificial sidewall and the metal layer and the unreacted metal layer.
  • the unreacted metal layer and the sacrificial sidewall, and the reaction product of the sacrificial sidewall and the metal layer may be separately removed by wet etching, and the reaction solution used in the wet etching may include H 2 0 2 , one of HC1, H 2 S0 4 , NH4OH, HN0 3 or a mixture of any of them.
  • the formation process of the metal silicide is completed, because the sacrificial side wall reaction consumes the metal layer located thereon during the heat treatment, thereby effectively slowing or avoiding the lateral diffusion of the metal element and the lateral growth of the metal silicide to Below the dielectric sidewalls, it helps to improve the reliability and performance of the device.
  • FIG. 11 to FIG. 16 are cross-sectional views showing an intermediate structure of a method for controlling lateral intrusion of a metal silicide into a channel region according to a second embodiment of the present invention, and a second embodiment is a method for forming a front gate process of a MOS field effect transistor, Similarly, the technical solution of the embodiment is also applicable to a Schottky barrier S/D MOSFET, a metal source/drain MOS field effect transistor (metal S/D MOSFET), and the like. The formation of a metal silicide on a semiconductor device.
  • a semiconductor substrate 30 is provided.
  • a gate stack structure 31 is formed on the semiconductor substrate 30, and an active region 32 and a drain region 33 are formed in the semiconductor substrate 30 on both sides of the gate stack structure 31.
  • the gate stack structure 31 in the present embodiment includes the gate dielectric layer 31a and the gate electrode 31b thereon, and the dielectric spacers are not formed on the sidewalls of the gate stack structure 31 of the present embodiment.
  • the gate dielectric layer 31a and the gate electrode 31b please refer to the first embodiment, and details are not described herein.
  • a sacrificial side is formed on a sidewall of the gate stack structure 31 on the semiconductor substrate 30.
  • the wall 34, the material of the sacrificial spacer 34 may react with the metal material used in the metal silicide when heated, and may specifically be tantalum, tin or silicon germanium ( ).
  • a metal layer 35 is deposited overlying the surface of the semiconductor substrate 30, the gate stack 31 and the sacrificial sidewalls 34.
  • the material of the metal layer 35 may be titanium, cobalt, nickel, nickel-cobalt alloy, nickel-platinum alloy or nickel-cobalt-platinum alloy.
  • the semiconductor substrate 30 is heat treated such that the metal layer 35 reacts with the source region 32, the drain region 33, the gate electrode 31b, and the sacrificial sidewall 34, in the source region 32, and the drain region.
  • the surface 33 and the surface of the gate electrode 31b form a metal silicide 35a. Since the sacrificial sidewalls 34 can react with the metal layer 35 located thereon, the lateral growth of the metal silicide can be slowed or avoided. Similar to the first embodiment, the thickness of the sacrificial spacers 34 can be controlled such that all or part of the metal layer 35 above the sacrificial spacers 34 reacts with the sacrificial spacers 34 to properly adjust the lateral direction of the metal silicide. Growth, reducing the source-drain parasitic series resistance.
  • the sacrificial sidewalls and the reaction products of the sacrificial sidewalls and the metal layer and the unreacted metal layer are removed.
  • the removal method may be wet etching, please refer to the first embodiment for details.
  • a dielectric spacer 36 is formed on the sidewall of the gate stack 31.
  • 17 to 24 are cross-sectional views showing an intermediate structure of a method of controlling lateral intrusion of a metal silicide into a channel region according to a third embodiment of the present invention
  • a third embodiment is a method for forming a gate-gate process of a MOS field effect transistor
  • the technical solution of the embodiment is also applicable to a Schottky barrier S/D MOSFET, a metal source/drain MOS field effect transistor (metal S/D MOSFET), and the like.
  • the formation of a metal silicide on a semiconductor device is also applicable to a Schottky barrier S/D MOSFET, a metal source/drain MOS field effect transistor (metal S/D MOSFET), and the like.
  • a semiconductor substrate 40 is provided.
  • a gate stack structure 41 is formed on the semiconductor substrate 40, and an active region 42 and a drain region 43 are formed in the semiconductor substrate 40 on both sides of the gate stack structure 41.
  • the gate stack structure 41 includes a dummy gate electrode 41a and a dielectric spacer 41b located on a sidewall of the dummy gate electrode 41a.
  • the material of the dummy gate electrode 41a is generally polysilicon, and the material of the dielectric spacer 41b is generally a silicon oxide or silicon nitride or a stacked structure of the two.
  • the removal process of the subsequent dummy gate electrode 41a is affected.
  • the surface of the dummy gate electrode 41a of the present embodiment is further formed with a cap layer 41c, and the cap layer 41c is formed.
  • the material is a dielectric material, such as nitriding Silicon and so on.
  • a sidewall of the gate stack structure 41 is formed with a sacrificial spacer 44.
  • the material of the sacrificial spacer 44 can be reacted with the metal material used in the metal silicide during heating, specifically Can be tantalum, tin or silicon germanium ( ).
  • a metal layer 45 is deposited overlying the surface of the semiconductor substrate 40, the gate stack 41, and the sacrificial sidewalls 44.
  • the material of the metal layer 45 may be titanium, cobalt, nickel, nickel-cobalt alloy, nickel-platinum alloy or nickel-cobalt-platinum alloy.
  • the semiconductor substrate 40 is heat treated such that the metal layer 45 reacts with the source region 42, the drain region 43, and the sacrificial sidewall 44 at the surface of the source region 42 and the drain region 43. Since the metal silicide 45a is formed, since the cap layer 41c does not react with the metal layer 45, metal silicide is not formed on the dummy gate electrode 41a. Since the sacrificial spacer 44 can react with the metal layer 45 located thereon, lateral growth of the metal silicide can be slowed or avoided.
  • the thickness of the sacrificial spacer 44 can be controlled such that all or part of the metal layer 45 above the sacrificial sidewall 44 reacts with the sacrificial sidewall 44 to be properly adjusted.
  • the lateral growth of the metal silicide reduces the source-drain parasitic series resistance.
  • the sacrificial sidewalls and the reaction products of the sacrificial sidewalls and the metal layer and the unreacted metal layer are removed.
  • the removal method may be wet etching, please refer to the first embodiment for details.
  • a dielectric layer 46 is formed on the semiconductor substrate 40 of the sidewall of the dielectric spacer 41b.
  • the dielectric layer 46 may be made of silicon oxide, doped silicon glass, or the like, and may be formed by a chemical vapor phase. Deposition.
  • the cap layer over the dummy gate electrode and the dummy gate electrode is removed to form an opening in the dielectric layer 46, which may be wet etching or dry etching.
  • a gate dielectric layer 47 and a gate electrode 48 are formed in the opening.
  • the material of the gate dielectric layer 47 is generally a high dielectric constant (high-k) material such as Hf0 2 , La 2 . 0 3 and the like
  • the material of the gate electrode 48 is generally a metal material such as Ti, Ni, Al, W or the like.
  • the dielectric spacer may not be formed first, but directly on the sidewall of the dummy gate electrode.
  • a sacrificial sidewall is formed, and after the metal silicide is subsequently formed and the sacrificial sidewall is removed, a dielectric spacer is formed on the sidewall of the dummy gate electrode.
  • the technical solution first forms a sacrificial sidewall on the sidewall of the gate stack structure; then depositing a metal layer covering the surface of the semiconductor substrate, the gate stack structure and the sacrificial sidewall; and then heat treating the semiconductor substrate Reacting between the metal layer and the semiconductor substrate of the source region and the drain region and the sacrificial sidewall; finally removing the sacrificial sidewall and the reaction product of the sacrificial sidewall and the metal layer and The metal layer of the reaction.
  • the metal layer on the sacrificial side wall reacts with the sacrificial sidewall, which is beneficial to weaken or avoid lateral growth of the metal silicide and improve device performance and reliability.
  • the technical solution can be applied to both the front gate process and the back gate process, and has high industrial availability.
  • the thickness of the sacrificial sidewall may be controlled such that all or part of the metal layer on the side wall of the sacrificial side wall reacts with the sacrificial sidewall during the heat treatment, that is, all or part of it is consumed.
  • the source-drain parasitic series resistance is reduced.

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Description

控制金属硅化物橫向侵入沟道区的方法
本申请要求于 2010 年 12 月 21 日提交中国专利局、 申请号为 201010599252.2、 发明名称为 "自对准金属硅化物的形成方法"的中国专利申 请的优先权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体制造领域，特别涉及一种在 MOSFET制作过程中控制金 属硅化物横向侵入沟道区的方法。
背景技术
随着半导体器件的特征尺寸 （CD, Critical Dimension ) 的不断减小， 如 MOS场效应管等半导体器件与上层互连结构之间的接触电阻对器件性能的影 响越来越大，现有技术中常用的降低接触电阻的方法是在器件的接触电极上形 成金属硅化物 （Silicide ) 。
图 1至图 3以 MOS场效应管为例， 示出了现有技术的一种金属硅化物的形 成方法。
参考图 1 , 提供半导体村底 10, 其上形成有 MOS场效应管， 所述 MOS场效 应管包括栅堆叠结构 11和位于所述栅堆叠结构 11两侧的半导体村底 10中的源 区 12和漏区 13, 其中， 所述栅堆叠结构 11主要包括栅介质层 11a和栅电极 lib, 以及位于所述栅介质层 11a和栅电极 lib侧壁的侧墙 11c,所述栅介质层 11a—般 为氧化硅， 所述栅电极 lib—般为多晶硅， 所述侧墙 11c一般为氧化硅或氮化硅 或二者的叠层结构。 之后， 沉积金属层 14, 覆盖所述半导体村底 10的表面以及 所述栅堆叠结构 11。为了降低形成金属硅化物的温度和生成具有低电阻率的金 属硅化物， 所述金属层 14的材料一般选择镍基金属， 如镍、 镍铂合金等， 以形 成镍基的金属硅化物 （Ni-based silicide, 例如 NiSi, NiPtSi, NiCoSi, NiPtCoSi 等等） 。
参考图 2, 对所述半导体村底 10进行热处理， 如退火等， 使得所述金属层
14和硅材料的源区 12和漏区 13的表面、 以及多晶硅材料的栅电极 lib的表面发 生反应， 产生电阻率较低的金属硅化物 14a, 而侧墙 11c为介质材料， 不与所述 金属层 14发生反应。
参考图 3, 将未发生反应的金属层 14去除， 完成金属硅化物的形成过程。 仍然参考图 2和图 3, 在金属硅化物 14a的形成过程中， 侧墙 11c和其他未与 半导体村底 10发生反应的金属层 14中的金属会发生横向的扩散，使得形成在源 区 12和漏区 13上的金属硅化物 14a向所述侧墙 11c下方的区域 15中生长，甚至生 长至栅介质层 11a下方的半导体村底 10中， 即 MOS场效应管的沟道区域中， 导 致栅电极漏电流增大， 器件可靠性下降， 甚至可能导致源区 12和漏区 13之间短 路， 严重影响器件的性能。 对于形成在绝缘体上硅（SOI )的 MOS场效应管而 言， 由于器件使用的硅材料本身就非常有限， 因此金属硅化物横向生长对器件 性能的影响更加严重。
发明内容
本发明解决的问题是现有技术中金属硅化物形成过程中发生横向生长，影 响器件性能。
为解决上述问题，本发明提供了一种控制金属硅化物横向侵入沟道区的方 法， 包括：
提供半导体村底， 所述半导体村底上形成有栅堆叠结构， 所述栅堆叠结构 两侧的半导体村底中形成有源区和漏区；
在所述半导体村底上、 所述栅堆叠结构的侧壁形成牺牲侧墙；
沉积金属层， 覆盖所述半导体村底、 栅堆叠结构和牺牲侧墙的表面； 对所述半导体村底进行热处理，使所述金属层与所述源区、 漏区的半导体 村底以及牺牲侧墙之间发生反应；
去除所述牺牲侧墙以及所述牺牲侧墙与所述金属层的反应产物和未反应 的金属层。
可选的， 所述半导体村底为硅村底、 硅错村底、 III- V族元素化合物村底 或绝缘体上硅结构。
可选的， 所述金属层的材料选自钛（Ti )、 钴（Co )、 镍（Ni )、 镍铂合金 ( Ni-Pt )、 镍钴合金 ( Ni-Co )或镍铂钴合金 ( Ni-Co-Pt )其中之一。
可选的，所述牺牲侧墙的材料选自错（ Ge )、锡（ Sn )或硅化锗（ Si^Ge )。 可选的，使用湿法刻蚀去除所述牺牲侧墙， 以及所述牺牲侧墙与所述金属 层的反应产物。
可选的， 使用湿法刻蚀去除所述未反应的金属层。 可选的，所述湿法刻蚀中使用的反应溶液包括 H202, HC1, H2S04, NH4OH, HN03中的一种或其中任意几种的混合物。
可选的， 所述在所述半导体村底上、所述栅堆叠结构的侧壁形成牺牲侧墙 包括：
形成牺牲层，覆盖所述半导体村底的表面以及所述栅堆叠结构的表面和侧 壁；
对所述牺牲层进行回刻，去除所述半导体村底表面和栅堆叠结构表面的牺 牲层， 在所述栅堆叠结构的侧壁形成牺牲侧墙。
可选的， 所述栅堆叠结构包括前栅工艺中的栅介质层、位于所述栅介质层 上的栅电极以及位于所述栅介质层和栅电极侧壁的介质侧墙，所述牺牲侧墙形 成于所述介质侧墙的外侧侧壁上。
可选的，所述栅堆叠结构包括前栅工艺中的栅介质层和位于所述栅介质层 上的栅电极， 所述牺牲侧墙形成于所述栅介质层和栅电极的侧壁，在去除所述 牺牲侧墙之后， 还包括：
在所述栅介质层和栅电极的侧壁形成介质侧墙。
可选的，所述栅堆叠结构包括后栅工艺中的伪栅电极和位于所述伪栅电极 侧壁的介质侧墙， 所述牺牲侧墙形成于所述介质侧墙的外侧侧壁上。
可选的， 所述栅堆叠结构包括后栅工艺中的伪栅电极， 所述牺牲侧墙形成 于所述伪栅电极的侧壁， 在去除所述牺牲侧墙之后， 还包括：
在所述伪栅电极的侧壁形成介质侧墙。
可选的， 经过所述热处理之后， 所述牺牲侧墙上方的金属层全部或部分与 所述牺牲侧墙发生反应。
与现有技术相比， 本发明的技术方案有如下优点：
本技术方案首先在栅堆叠结构的侧壁形成牺牲侧墙； 之后沉积金属层，覆 盖所述半导体村底、栅堆叠结构和牺牲侧墙的表面； 之后对所述半导体村底进 行热处理，使所述金属层与所述源区、 漏区的半导体村底以及牺牲侧墙之间发 生反应； 最后去除所述牺牲侧墙， 以及所述牺牲侧墙与所述金属层的反应产物 和未反应的金属层。在所述热处理过程中，牺牲侧墙上方的金属层与所述牺牲 侧墙发生反应，有利于减弱或避免金属硅化物的横向生长，提高器件性能和可 靠性。
进一步的， 本技术方案既能够适用于前栅工艺， 也能够适用于后栅工艺， 工业可用性强。
此外， 在实际生产应用中， 可以控制所述牺牲侧墙的厚度， 使得在热处理 过程中牺牲侧墙上方的金属层全部或部分与所述牺牲侧墙发生反应，即全部或 部分被消耗掉， 以适当调节金属硅化物的横向生长， 降低源漏寄生串联电阻。
附图说明
图 1至图 3是现有技术的一种控制金属硅化物横向侵入沟道区的方法的中 间结构的剖面图；
图 4 是本发明控制金属硅化物横向侵入沟道区的方法的具体实施方式的 流程示意图；
图 5至图 10是本发明控制金属硅化物横向侵入沟道区的方法的第一实施 例的中间结构的剖面图；
图 11至图 16是本发明控制金属硅化物横向侵入沟道区的方法的第二实施 例的中间结构的剖面图；
图 17至图 24是本发明控制金属硅化物横向侵入沟道区的方法的第三实施 例的中间结构的剖面图。
具体实施方式
现有技术中金属硅化物在形成过程中会发生横向生长，进入侧墙下方甚至 沟道区域中， 影响器件的可靠性和性能。
本技术方案首先在栅堆叠结构的侧壁形成牺牲侧墙； 之后沉积金属层，覆 盖所述半导体村底、栅堆叠结构和牺牲侧墙的表面； 之后对所述半导体村底进 行热处理，使所述金属层与所述源区、 漏区的半导体村底以及牺牲侧墙之间发 生反应； 最后去除所述牺牲侧墙， 以及所述牺牲侧墙与所述金属层的反应产物 和未反应的金属层。在所述热处理过程中，牺牲侧墙上方的金属层与所述牺牲 侧墙发生反应，有利于减弱或避免金属硅化物的横向生长，提高器件性能和可 靠性。
进一步的， 本技术方案既能够适用于前栅工艺， 也能够适用于后栅工艺， 工业可用性强。 此外， 在实际生产应用中， 可以控制所述牺牲侧墙的厚度， 使得在热处理 过程中牺牲侧墙上方的金属层全部或部分与所述牺牲侧墙发生反应，即全部或 部分被消耗掉， 以适当调节金属硅化物的横向生长， 降低源漏寄生串联电阻。
为使本发明的上述目的、特征和优点能够更为明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
在以下描述中阐述了具体细节以便于充分理解本发明。但是本发明能够以 多种不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明 内涵的情况下做类似推广。 因此本发明不受下面公开的具体实施方式的限制。
图 4 示出了本发明的控制金属硅化物横向侵入沟道区的方法的具体实施 方式的流程示意图， 包括：
步骤 S21 , 提供半导体村底， 所述半导体村底上形成有栅堆叠结构， 所述 栅堆叠结构两侧的半导体村底中形成有源区和漏区；
步骤 S22, 在所述半导体村底上、 所述栅堆叠结构的侧壁形成牺牲侧墙； 步骤 S23, 沉积金属层， 覆盖所述半导体村底、 栅堆叠结构和牺牲侧墙的 表面；
步骤 S24, 对所述半导体村底进行热处理， 使所述金属层与所述源区、 漏 区的半导体村底以及牺牲侧墙之间发生反应；
步骤 S25, 去除所述牺牲侧墙以及所述牺牲侧墙与所述金属层的反应产物 和未反应的金属层。
第一实施例
图 5至图 10示出了本发明控制金属硅化物横向侵入沟道区的方法的第一 实施例的中间结构的剖面图， 第一实施例为 MOS场效应管的前栅工艺的形成 方法， 当然， 本实施例的技术方案也适用于肖特基势垒源 /漏 MOS 场效应管 ( Schottky barrier S/D MOSFET )、 金属源 /漏 MOS 场效应管 （metallic S/D MOSFET )等其他半导体器件上的金属硅化物的形成过程。 下面结合图 4和图 5至图 10对第一实施例进行详细说明。
结合图 4和图 5, 执行步骤 S21 , 提供半导体村底， 所述半导体村底上形 成有栅堆叠结构， 所述栅堆叠结构两侧的半导体村底中形成有源区和漏区。 具 体的， 如图 5所示， 提供半导体村底 20, 所述半导体村底 20可以是硅村底、 锗硅村底、 ΠΙ- V族元素化合物村底、 或绝缘体上硅结构， 或本领域技术人员 公知的其他半导体材料村底， 本实施例中， 所述半导体村底 20优选为硅村底。
所述半导体村底 20上形成有栅堆叠结构 21 , 所述栅堆叠结构 21两侧的 半导体村底 20中形成有源区 22和漏区 23。 本实施例中， 所述栅堆叠结构 21 包括栅介质层 21a和形成于栅介质层 21a之上的栅电极 21b, 以及位于所述栅 介质层 21a和栅电极 21b侧壁的介质侧墙 21c。 所述栅介质层 21a的材料可以 是氧化硅， 所述栅电极 21b的材料可以是多晶硅， 所述介质侧墙 21c的材料可 以是氧化硅或氮化硅或二者的叠层结构。
结合图 4、 图 6和图 7, 执行步骤 S22, 在所述半导体村底上、 所述栅堆 叠结构的侧壁形成牺牲侧墙。
具体的， 首先参考图 6, 形成牺牲层 24, 覆盖所述半导体村底 20的表面 以及所述栅堆叠结构 21的表面和侧壁。所述牺牲层 24的材料可以是错、锡或 硅化锗（Si^GeJ等， 或是其他在加热时能够与金属硅化物中使用的金属材 料反应的材料，其形成方法可以是化学气相沉积（ CVD )、物理气相沉积（ PVD ) 等。
参考图 7, 对所述牺牲层进行回刻 （etch back ), 去除所述半导体村底 20 表面和栅堆叠结构 21表面的牺牲层，在所述栅堆叠结构 21的侧壁形成牺牲侧 墙 24a, 具体的， 所述牺牲侧墙 24a位于所述介质侧墙 21c的外围侧壁上。
结合图 4和图 8, 执行步骤 S23 , 沉积金属层， 覆盖所述半导体村底、 栅 堆叠结构和牺牲侧墙的表面。 具体的， 沉积金属层 25 , 覆盖所述半导体村底 20、 栅堆叠结构 21和牺牲侧墙 24a的表面。 所述金属层 25的材料可以是钛、 钴、 镍、 镍铂合金、 镍钴合金或镍钴铂合金其中之一， 其形成方法可以是物理 气相沉积。
结合图 4和图 9, 执行步骤 S24, 对所述半导体村底进行热处理， 使所述 金属层与所述源区、 漏区的半导体村底以及牺牲侧墙之间发生反应。 具体的， 对所述半导体村底 20进行热处理， 如退火等， 使所述金属层 25与所述源区 22、 漏区 23以及牺牲侧墙 24a中的材料发生反应， 在所述源区 22、 漏区 23 和栅电极 21b的表面形成金属硅化物 25a。
在所述热处理过程中， 所述牺牲侧墙 24a上方的金属层 25和所述牺牲侧 墙 24a发生反应被消耗， 能够有效减緩或避免金属元素的横向扩散。 在具体实 施例中，可以通过增大所述牺牲侧墙 24a的厚度以使得所述牺牲侧墙 24a上方 的金属层 25全部反应消耗掉，从而基本上避免了金属元素的横向扩散； 此外， 也可以通过减小所述牺牲侧墙 24a的厚度以使得所述牺牲侧墙 24a上方的金属 层 25反应后被部分消耗， 使得金属元素发生适度的横向扩散现象， 以使所述 金属硅化物 25a横向生长延伸至牺牲侧墙 24a的下方区域 26中， 但同时并不 延伸至截至侧墙 21c的下方， 在后续去除所述牺牲侧墙 24a之后， 有利于增大 源区 22和漏区 23上形成的金属硅化物 25a的覆盖面积，减小源漏寄生串联电 阻。
结合图 4和图 10,执行步骤 S25 ,去除所述牺牲侧墙以及所述牺牲侧墙与 所述金属层的反应产物和未反应的金属层。具体的， 可以使用湿法刻蚀分别去 除所述未反应的金属层和牺牲侧墙， 以及所述牺牲侧墙与金属层的反应产物， 湿法刻蚀中使用的反应溶液可以包括 H202, HC1, H2S04, NH4OH, HN03中 的一种或其中任意几种的混合物。
至此， 完成了金属硅化物的形成过程， 由于在热处理过程中牺牲侧墙反应 消耗了位于其上的金属层，因而有效的减緩或避免了金属元素的横向扩散和金 属硅化物的横向生长至介质侧墙下方， 有利于提高器件的可靠性和性能。
第二实施例
图 11至图 16示出了本发明第二实施例的控制金属硅化物横向侵入沟道区 的方法的中间结构的剖面图， 第二实施例为 MOS场效应管的前栅工艺的形成 方法， 类似的， 本实施例的技术方案也适用于肖特基势垒源 /漏 MOS场效应管 ( Schottky barrier S/D MOSFET )、 金属源 /漏 MOS 场效应管 （metallic S/D MOSFET )等其他半导体器件上的金属硅化物的形成过程。
参考图 11 , 提供半导体村底 30, 所述半导体村底 30上形成有栅堆叠结构 31 , 栅堆叠结构 31两侧的半导体村底 30中形成有源区 32和漏区 33。 本实施 例中所述栅堆叠结构 31 包括栅介质层 31a和位于其上的栅电极 31b, 本实施 例的栅堆叠结构 31的侧壁上并没有形成介质侧墙。 所述半导体村底 30、 栅介 质层 31a和栅电极 31b的材料请参考第一实施例， 这里就不再赘述。
参考图 12, 在所述半导体村底 30上、 栅堆叠结构 31的侧壁形成牺牲侧 墙 34, 所述牺牲侧墙 34的材料可以在加热时与金属硅化物中所用的金属材料 反应， 具体可以为锗、 锡或硅化锗（ )。
参考图 13, 沉积金属层 35, 覆盖所述半导体村底 30、 栅堆叠结构 31和 牺牲侧墙 34的表面。 所述金属层 35的材料可以是钛、 钴、 镍、 镍钴合金、 镍 铂合金或镍钴铂合金等。
参考图 14, 对所述半导体村底 30进行热处理， 使得所述金属层 35与所 述源区 32、 漏区 33、 栅电极 31b和牺牲侧墙 34发生反应， 在所述源区 32、 漏区 33和栅电极 31b的表面形成金属硅化物 35a。 由于所述牺牲侧墙 34可以 和位于其上的金属层 35发生反应， 因而可以减緩或避免金属硅化物的横向生 长。 与第一实施例类似的， 可以通过控制牺牲侧墙 34的厚度， 以使得牺牲侧 墙 34上方的金属层 35全部或部分与所述牺牲侧墙 34发生反应， 从而适当调 节金属硅化物的横向生长， 减小源漏寄生串联电阻。
参考图 15, 去除所述牺牲侧墙以及牺牲侧墙与金属层的反应产物和未反 应的金属层。 去除方法可以是湿法刻蚀， 具体请参见第一实施例。
参考图 16, 在去除所述牺牲侧墙以及牺牲侧墙与金属层的反应产物和未 反应的金属层之后， 在所述栅堆叠结构 31的侧壁上形成介质侧墙 36。
第三实施例
图 17至图 24示出了本发明第三实施例的控制金属硅化物横向侵入沟道区 的方法的中间结构的剖面图， 第三实施例为 MOS场效应管的后栅工艺的形成 方法， 类似的， 本实施例的技术方案也适用于肖特基势垒源 /漏 MOS场效应管 ( Schottky barrier S/D MOSFET )、 金属源 /漏 MOS 场效应管 （metallic S/D MOSFET )等其他半导体器件上的金属硅化物的形成过程。
参考图 17,提供半导体村底 40, 所述半导体村底 40上形成有栅堆叠结构 41 , 栅堆叠结构 41两侧的半导体村底 40中形成有源区 42和漏区 43。 本实施 例中， 所述栅堆叠结构 41包括伪栅电极 41a和位于所述伪栅电极 41a侧壁的 介质侧墙 41b。 所述伪栅电极 41a的材料一般为多晶硅， 所述介质侧墙 41b的 材料一般为氧化硅或氮化硅或二者的叠层结构。 为了防止在所述伪栅电极 41a 上也形成金属硅化物， 影响后续伪栅电极 41a的去除过程， 本实施例的伪栅电 极 41a的表面上还形成有帽层 41c, 所述帽层 41c的材料为介质材料， 如氮化 硅等。
参考图 18, 在所述半导体村底 40上、 栅堆叠结构 41的侧壁形成牺牲侧 墙 44, 所述牺牲侧墙 44的材料可以在加热时与金属硅化物中所用的金属材料 反应， 具体可以为锗、 锡或硅化锗（
Figure imgf000011_0001
)。
参考图 19, 沉积金属层 45, 覆盖所述半导体村底 40、 栅堆叠结构 41和 牺牲侧墙 44的表面。 所述金属层 45的材料可以是钛、 钴、 镍、 镍钴合金、 镍 铂合金或镍钴铂合金等。
参考图 20, 对所述半导体村底 40进行热处理， 使得所述金属层 45与所 述源区 42、 漏区 43和牺牲侧墙 44发生反应， 在所述源区 42和漏区 43的表 面形成金属硅化物 45a, 由于所述帽层 41c并不与金属层 45反应， 因而伪栅 电极 41a上并不会形成金属硅化物。 由于所述牺牲侧墙 44可以和位于其上的 金属层 45发生反应， 因而可以减緩或避免金属硅化物的横向生长。 与第一实 施例和第二实施例类似的， 可以通过控制牺牲侧墙 44的厚度， 以使得牺牲侧 墙 44上方的金属层 45全部或部分与所述牺牲侧墙 44发生反应， 从而适当调 节金属硅化物的横向生长， 减小源漏寄生串联电阻。
参考图 21 , 去除所述牺牲侧墙以及所述牺牲侧墙与金属层的反应产物和 未反应的金属层。 去除方法可以是湿法刻蚀， 具体请参见第一实施例。
参考图 22, 在所述介质侧墙 41b侧壁的半导体村底 40上形成介质层 46, 所述介质层 46的材料可以是氧化硅、 掺杂的硅玻璃等， 其形成方法可以是化 学气相沉积。
参考图 23 , 去除所述伪栅电极和伪栅电极上方的帽层， 从而在所述介质 层 46中形成开口， 去除的方法可以是湿法刻蚀或干法刻蚀。
参考图 24, 在所述开口中填充形成栅介质层 47和栅电极 48,在后栅工艺 中， 栅介质层 47的材料一般为高介电常数（高 k )材料， 如 Hf02, La203等， 栅电极 48的材料一般为金属材料， 如 Ti, Ni, Al, W等。
至此，完成了后栅工艺中 MOS场效应管和金属硅化物的形成过程， 当然， 在其他具体实施例中，也可以先不形成介质侧墙， 而在所述伪栅电极的侧壁上 直接形成牺牲侧墙，在后续形成金属硅化物并去除所述牺牲侧墙之后，再在所 述伪栅电极的侧壁上形成介质侧墙。 综上， 本技术方案首先在栅堆叠结构的侧壁形成牺牲侧墙； 之后沉积金属 层， 覆盖所述半导体村底、栅堆叠结构和牺牲侧墙的表面； 之后对所述半导体 村底进行热处理，使所述金属层与所述源区、 漏区的半导体村底以及牺牲侧墙 之间发生反应；最后去除所述牺牲侧墙以及所述牺牲侧墙与所述金属层的反应 产物和未反应的金属层。在所述热处理过程中，牺牲侧墙上方的金属层与所述 牺牲侧墙发生反应，有利于减弱或避免金属硅化物的横向生长，提高器件性能 和可靠性。
进一步的， 本技术方案既能够适用于前栅工艺， 也能够适用于后栅工艺， 工业可用性强。
此外， 在实际生产应用中， 可以控制所述牺牲侧墙的厚度， 使得在热处理 过程中牺牲侧墙上方的金属层全部或部分与所述牺牲侧墙发生反应，即全部或 部分被消耗掉， 以适当调节金属硅化物的横向生长， 降低源漏寄生串联电阻。
本发明虽然已以较佳实施例公开如上，但其并不是用来限定本发明，任何 本领域技术人员在不脱离本发明的精神和范围内，都可以利用上述揭示的方法 和技术内容对本发明技术方案做出可能的变动和修改， 因此， 凡是未脱离本发 改、 等同变化及修饰， 均属于本发明技术方案的保护范围。

Claims

权 利 要 求
1. 一种控制金属硅化物横向侵入沟道区的方法， 其特征在于， 包括：
提供半导体村底， 所述半导体村底上形成有栅堆叠结构， 所述栅堆叠结构 两侧的半导体村底中形成有源区和漏区；
在所述半导体村底上、 所述栅堆叠结构的侧壁形成牺牲侧墙；
沉积金属层， 覆盖所述半导体村底、 栅堆叠结构和牺牲侧墙的表面； 对所述半导体村底进行热处理， 使所述金属层与所述源区、 漏区的半导体 村底以及牺牲侧墙之间发生反应；
去除所述牺牲侧墙以及所述牺牲侧墙与所述金属层的反应产物和未反应的 金属层。
2. 根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于， 所述半导体村底为硅村底、 硅锗村底、 III- V族元素化合物村底或绝缘体 上硅结构。
3. 根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于， 所述金属层的材料选自钛、 钴、 镍、 镍铂合金、 镍钴合金或镍铂钴合金其 中之一。
4. 根据权利要求 3所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于， 所述牺牲侧墙的材料选自锗、 锡或硅化锗。
5. 根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于，使用湿法刻蚀去除所述牺牲侧墙， 以及所述牺牲侧墙与所述金属层的反应 产物。
6. 根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于， 使用湿法刻蚀去除所述未反应的金属层。
7. 根据权利要求 5或 6所述的控制金属硅化物横向侵入沟道区的方法， 其特 征在于， 所述湿法刻蚀中使用的反应溶液包括 H202, HC1, H2S04, NH4OH,
HN03中的一种或其中任意几种的混合物。
8. 根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于， 所述在所述半导体村底上、 所述栅堆叠结构的侧壁形成牺牲侧墙包括： 形成牺牲层， 覆盖所述半导体村底的表面以及所述栅堆叠结构的表面和侧 壁；
对所述牺牲层进行回刻， 去除所述半导体村底表面和栅堆叠结构表面的牺 牲层， 在所述栅堆叠结构的侧壁形成牺牲侧墙。
9. 根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于， 所述栅堆叠结构包括前栅工艺中的栅介质层、位于所述栅介质层上的栅电 极以及位于所述栅介质层和栅电极侧壁的介质侧墙，所述牺牲侧墙形成于所述
10.根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于，所述栅堆叠结构包括前栅工艺中的栅介质层和位于所述栅介质层上的栅电 极， 所述牺牲侧墙形成于所述栅介质层和栅电极的侧壁，在去除所述牺牲侧墙 之后， 还包括：
在所述栅介质层和栅电极的侧壁形成介质侧墙。
11.根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于，所述栅堆叠结构包括后栅工艺中的伪栅电极和位于所述伪栅电极侧壁的介 质侧墙， 所述牺牲侧墙形成于所述介质侧墙的外侧侧壁上。
12.根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于， 所述栅堆叠结构包括后栅工艺中的伪栅电极， 所述牺牲侧墙形成于所述伪 栅电极的侧壁， 在去除所述牺牲侧墙之后， 还包括：
在所述伪栅电极的侧壁形成介质侧墙。
13.根据权利要求 1所述的控制金属硅化物横向侵入沟道区的方法， 其特征在 于， 经过所述热处理之后， 所述牺牲侧墙上方的金属层全部或部分与所述牺牲 侧墙发生反应。
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