WO2012025025A1 - 一种soi场效应晶体管的散热结构 - Google Patents

一种soi场效应晶体管的散热结构 Download PDF

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WO2012025025A1
WO2012025025A1 PCT/CN2011/078507 CN2011078507W WO2012025025A1 WO 2012025025 A1 WO2012025025 A1 WO 2012025025A1 CN 2011078507 W CN2011078507 W CN 2011078507W WO 2012025025 A1 WO2012025025 A1 WO 2012025025A1
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drain
source
type
field effect
effect transistor
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PCT/CN2011/078507
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English (en)
French (fr)
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黄如
黄欣
薛守斌
艾玉杰
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北京大学
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Priority to US13/582,624 priority Critical patent/US8598636B2/en
Priority to DE112011100484.2T priority patent/DE112011100484B4/de
Publication of WO2012025025A1 publication Critical patent/WO2012025025A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/38—Cooling arrangements using the Peltier effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N19/00—Integrated devices, or assemblies of multiple devices, comprising at least one thermoelectric or thermomagnetic element covered by groups H10N10/00 - H10N15/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to the field of microelectronics, and in particular to a heat dissipation structure of a SOI field effect transistor for Schottky source and drain.
  • S0I field effect transistors are widely used in the industry due to their ideal subthreshold swing, small leakage current, and effective suppression of short-channel effects.
  • Schottky source-drain S0I field effect transistors have received more and more attention.
  • the self-heating effect of the S0I field effect transistor limits the performance of the device to some extent.
  • the heat generated by the device is mainly dissipated through the bulk silicon substrate.
  • the S0I field effect transistor has a thick layer of silicon dioxide (generally on the order of 100 nanometers).
  • the thermal conductivity of silicon dioxide is much smaller than that of bulk silicon.
  • the silicon film of the S0I field effect transistor is very thin, and the surface emission of the phonon causes the thermal conductivity of the silicon film to be smaller than that of the bulk silicon, which further suppresses the heat dissipation of the device. Therefore, the S0I field effect transistor has a significant self-heating effect compared to the bulk silicon field effect transistor, which affects the electrical performance and reliability of the device.
  • some methods add a heat-dissipating heat-dissipating layer (such as graphene) above the buried oxide layer and dissipate heat from the side; there are other methods, such as in the STI region.
  • a material having a high thermal conductivity such as diamond
  • the heat dissipation structure is not directly connected to the device, so the heat dissipation effect is not good.
  • the heat dissipation structure for the Schottky source-drain SOI field effect transistor proposed by the present invention is shown in FIG.
  • the heat dissipating structure includes two holes respectively filled with N-type and P-type high thermoelectric efficiency materials under the source and the drain.
  • the structure can also be perforated only at the drain end because the heat generated is mainly concentrated at the drain end. Simultaneous punching of the source and drain can improve heat dissipation efficiency.
  • the N-type and P-type high thermoelectric constant materials are connected to the drain terminal of the field effect transistor, the connection is ohmic contact, and the metal lead of the N-type high thermoelectric constant material near the drain end is connected to the drain terminal with a high potential.
  • a metal lead of the P-type high thermoelectric constant material near the drain end is connected to a low potential with respect to the drain terminal; the N-type and P-type high thermoelectric constant materials are connected to the source end of the field effect transistor, and the joints are all ohmic contacts.
  • the metal lead of the N-type high thermoelectric constant material near the source end is connected to the source terminal with a high potential, and the metal lead of the P-type material near the source end is connected to the source terminal with a low potential; when the device is not working or does not need to be dissipated, Leak end
  • the metal potential of the near high thermoelectric constant material is equal to the drain voltage; the metal potential of the high thermoelectric constant material near the source end is equal to the source voltage.
  • the invention utilizes the Peltier effect to absorb heat at the contact of the thermoelectric material with the source and drain while releasing heat at the junction of the thermoelectric material and the bottom electrode metal, thereby effectively transferring the heat of the active region of the device to the substrate and dissipating through the heat sink. go.
  • the invention has the advantages that the heat dissipation structure is directly connected to the active region of the device, and the Peltier effect is used to reduce the temperature of the source and the drain of the device, thereby effectively reducing the channel temperature of the device and improving the performance of the device; when the device is not working,
  • the heat dissipation structure can be disabled by the voltage setting.
  • This structure can be applied to 3D circuit structures and can be extended to all Schottky source-drain S0I field effect transistors, regardless of material and structure.
  • the manufacturing process of the structure is compatible with the CMOS process.
  • Figure l (a) _ (m) is a process flow diagram for the heat dissipation structure
  • drain 104 semiconductor buried layer of S0I substrate
  • thermoelectric material 110 N type thermoelectric material 111 P type thermoelectric material
  • FIG. 3 is a schematic diagram of a heat dissipation structure of a S0I field effect transistor of the present invention. detailed description
  • the drain terminal is filled with N-type and P-type high thermoelectric constant materials (usually commonly used Bi2Te3 and Bi2Sb).
  • the v-vi compound semiconductor which may also be a novel nano-thermoelectric material, has two holes connected, and the connections are all ohmic contacts.
  • the N-type material is connected to a high potential with respect to the drain terminal, and the P-type material is connected to a low potential with respect to the drain terminal.
  • the bias voltage and the material doping concentration the current flowing from the N-type material to the drain terminal is opposite to the current flowing from the drain terminal to the P-type material in the opposite direction, without affecting the output current of the field effect transistor.
  • the source-drain characteristics of the Schottky source-drain field effect transistor are similar to those of the metal and the Peltier effect, which is absorbed at the drain end and the material contact.
  • the source function implementation method is consistent.
  • the process implementation of the structure mainly includes the following steps:
  • thermoelectric materials Depositing thermoelectric materials and doping them in situ to form N-type and P-type thermoelectric materials, respectively. Annealing, forming an ohmic contact, as shown in Figure 1 (h)
  • the currents in the N-type material and the P-type material at the source end and the drain end are equal in opposite directions.
  • the material of the filled hole has a small electrical resistance compared to the substrate.
  • the N-type and P-type materials at the same end are spaced as far as possible to neglect the flow of current into the silicon substrate.
  • the selected N-type thermoelectric material and the P-type thermoelectric material are heavily doped, and the resistance value is small and the same size, thereby ensuring the current flowing through the N-type thermoelectric material and the P-type thermoelectric material at each end of the source end and the drain end.
  • the opposite direction is opposite, which ultimately has no effect on the normal operation of the device.
  • the resistance of the thermoelectric material is small, the substrate resistance is large, and the distance between the N-type and P-type materials at the same end in the design is as far as possible to neglect the flow of current in the thermoelectric material to the silicon substrate.
  • the um is 0. 4um, and the width is 0. 8um. 5 ⁇
  • the width of the hole is less than 0. 4um and the minimum size is limited by lithography; The distance between the two holes at the same end is greater than 0. 3um about.
  • the present invention takes the N-type Schottky junction SOI field effect transistor as an example, taking the value of the 13um standard process, (for illustrative purposes only, not as a limitation of the present invention).
  • the voltage setting mainly includes the following two aspects:
  • Vl Vs
  • V2 Vs
  • V3 Vd
  • V4 Vd.
  • the voltage bias setting of the heat dissipation structure of the transistor provided by the present invention is described above by way of the embodiments. It should be understood by those skilled in the art that the device structure of the present invention may be modified or may be modified without departing from the spirit of the invention. Modifications, the test voltage is not limited to what is disclosed in the embodiments.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

一种 SOI场效应晶体管的散热结构
技术领域 本发明属于微电子领域，具体涉及一种用于肖特基源漏的 S0I场效应晶体管的散热结构。 背景技术 随着器件尺寸的减小， S0I 场效应晶体管以其理想的亚阈摆幅、 小的漏电流以及有效抑 制短沟效应等优势， 被业界广泛的使用。 同时为了减小源漏的串联电阻， 进一步提高器件性 能， 肖特基源漏 S0I场效应晶体管得到了越来越多的重视。
另一方面， S0I场效应晶体管具有的自加热效应在一定程度上限制了器件的性能。 对于体 硅场效应晶体管， 器件产生的热量主要通过体硅衬底散走。 而 S0I场效应晶体管具有一层厚 的二氧化硅层 （一般在百纳米量级）， 二氧化硅的热导率远远小于体硅， 常温下只有
1. 38 W/m/K, 阻碍了沟道向衬底的散热。 同时， S0I 场效应晶体管的硅膜很薄， 声子表面散 射导致硅膜热导率要小于体硅， 进一步抑制了器件的散热。 因此， S0I 场效应晶体管和体硅 场效应晶体管相比具有明显的自加热效应， 影响器件的电学性能和可靠性。 为了减小 S0I场 效应晶体管的自热效应， 有的方法在埋氧层上方添加一层热导率高的散热层（如石墨烯）， 并 从侧边散热； 也有其他方法， 如将 STI区域里填入热导率高的材料（如金刚石）， 并将该区域 延伸穿过埋氧层与硅衬底接触。 上述方法中， 散热结构未与器件直接连接， 故散热效果不佳。 发明内容 本发明的目的在于提供一种用于肖特基源漏 S0I场效应晶体管散热结构， 用以解决现有 该类型器件自加热效应的问题。
本发明提出的用于肖特基源漏 S0I场效应晶体管散热结构， 如图 3所示。 该散热结构包 括源、 漏下方分别设置填充 N型和 P型高热电效率材料的两个孔。 该结构也可以只在漏端打 孔， 因为产生的热量主要集中在漏端。 源漏同时打孔可以提高散热效率。 所述 N型和 P型高 热电常数材料与场效应晶体管的漏端连接， 所述连接处均为欧姆接触， 漏端附近的 N型高热 电常数材料的金属引线相对于漏端接高电位， 漏端附近的 P型高热电常数材料的金属引线相 对于漏端接低电位； 所述 N型和 P型高热电常数材料与场效应晶体管的源端连接， 所述连接 处均为欧姆接触， 源端附近的 N型高热电常数材料的金属引线相对于源端接高电位， 源端附 近的 P型材料的金属引线相对于源端接低电位； 当器件不工作或不需要进行散热时， 漏端附 近的高热电常数材料连接的金属电位均与漏电压相等； 源端附近的高热电常数材料连接的金 属电位均与源电压相等。 本发明利用帕尔帖效应， 在热电材料与源漏接触处吸收热量同时在 热电材料与底电极金属连接处放出热量， 从而将器件有源区的热量有效地传递到衬底， 通过 散热片散走。
本发明的优点是将散热结构直接与器件有源区相连， 利用帕尔帖效应， 降低器件源端和 漏端的温度， 从而有效地降低器件沟道温度， 提高器件性能； 当器件不工作时， 可以通过电 压设置使散热结构不工作。这种结构可以应用在 3D电路结构中， 并且可以扩展到所有肖特基 源漏 S0I场效应晶体管中，不受材料和结构的限制。同时该结构的制造工艺与 CMOS工艺兼容。 附图说明
图 l (a) _ (m)为散热结构实现工艺流程图；
图 l (a) - (m)中， 相同的标号表示相同的部件：
101 氮化硅阻挡层 102—多晶硅栅
103— n+源、 漏 104— S0I衬底的二氧化硅埋层
105—衬底 106—沟道 （S0I顶层硅） 107—栅氧
108 二氧化硅 （场氧） 109 二氧化硅薄膜
110 N型热电材料 111 P型热电材料
112—金属 (铜）
图 2为散热结构背面俯视图；
图 2中：
1 Vl=Vs + VI (VI为正） 2— V2=Vs -VI (VI为正）
3- V3=Vd - V2 (V2为正） 4 V4=Vd + V2 (V2为正）
5- 源端 N型热电材料 6—源端 P型热电材料
7- 漏端 P型热电材料 8—源端 N型热电材料
图 3为本发明 S0I场效应晶体管的散热结构示意图。 具体实施方式
下面通过实例对本发明做进一步说明。 需要注意的是， 公布实施例的目的在于帮助进一 步理解本发明， 但是本领域的技术人员可以理解： 在不脱离本发明及所附权利要求的精神和 范围内， 各种替换和修改都是可能的。 因此， 本发明不应局限于实施例所公开的内容， 本发 明要求保护的范围以权利要求书界定的范围为准。
以漏端为例， 漏端与分别填充 N型和 P型高热电常数材料 （一般常用 Bi2Te3和 Bi2Sb 等 v-vi族化合物半导体， 也可以是新型的纳米热电材料）的两个孔连接， 连接处均为欧姆接 触。 N型材料相对于漏端接高电位， P型材料相对于漏端接低电位。通过设计偏置电压以及材 料掺杂浓度， 使得从 N型材料流向漏端的电流与从漏端流向 P型材料的电流大小相等方向相 反， 进而不影响场效应晶体管的输出电流大小。 电流从 N型材料流向漏端和从漏端流向 P型 材料时， 利用肖特基源漏场效应晶体管的源漏特性与金属类似的特点以及帕尔帖效应， 在漏 端和材料接触处吸收器件沟道产生的热量； 电流从互联金属引线流向 N型材料和从 P型材料 流向金属引线时， 利用帕尔帖效应在金属和材料接触处放出热量。 源端功能实现方法一致。
该结构的工艺实现主要包括以下步骤：
1) 实现 S0I场效应晶体管， 淀积二氧化硅钝化层， 如图 1 (a)所示
2) CMP二氧化硅层， 以 Si3N4为停止层， 如图 1 (b)所示
3) 淀积二氧化硅， 形成表面平整的二氧化硅钝化层， 如图 1 (c)所示
4) 倒置器件， 淀积一层二氧化硅阻挡层， 如图 1 (d)所示
5) 光刻， 腐蚀二氧化硅， 形成孔的图形， 如图 1 (e)所示
6) 各向异性等离子体刻孔， 以埋氧层为停止层， 如图 1 (f)所示
7) 各向异性等离子体刻孔， 以源漏为停止层， 如图 1 (g)所示
8) 淀积热电材料并原位掺杂分别形成 N型和 P型热电材料。退火， 形成欧姆接触， 如图 1 (h) 所示
9) 腐蚀掉二氧化硅， 如图 l (i)所示
10)淀积一层二氧化硅保护层， 防止衬底被污染， 如图 l (j)所示
11)反应离子刻蚀金属连线孔， 以衬底 Si层为停止层， 并淀积金属， 如图 l (k)所示
12) 倒置器件， 各向异性等离子体刻蚀金属连线孔并淀积金属， 如图 1 (1)所示
13) CMP磨平金属， 以二氧化硅层为停止层， 如图 l (m)所示
本发明中， 源端及漏端 N型材料和 P型材料中的电流大小相等方向相反。 另外， 填充孔 的材料的电阻与衬底相比很小， 在设计中同一端的 N型和 P型材料距离尽量远一些从而忽略 材料中电流往硅衬底的流动。
本发明中， 选择的 N型热电材料和 P型热电材料均重掺， 电阻值很小且大小相同， 从而 保证源端及漏端每端 N型热电材料和 P型热电材料中流经的电流大小相等方向相反， 最终对 器件正常工作的电流不造成影响。 另外， 由于热电材料电阻很小， 衬底电阻很大， 并且在设 计中同一端的 N型和 P型材料距离尽量远一些从而忽略热电材料中电流往硅衬底的流动。 以 标准工艺. 013工艺为例， 场效应晶体管的源漏长为 0. 4um， 宽为 0. 8um。 可设计孔的长度小 于 0. 4um并且最小尺寸由光刻限制； 孔的宽度小于 0. 25um左右。 同一端两孔距离大于 0. 3um 左右。
本发明以 N型号肖特基结 SOI场效应晶体管为例， 取值. 13um标准工艺， （仅用来举例说 明， 不作为本发明的限制条件）。
电压设置主要包括以下两个方面：
( 1 )、 进行器件散热时， Vl=Vs+1. 5V， V2=Vs-l. 5V, V3=Vd-l. 5V, V4=Vd+l. 5V。
( 3)、 不进行器件散热时， Vl=Vs， V2=Vs, V3=Vd, V4=Vd。
以上通过实施例描述了本发明所提供的晶体管散热结构的电压偏置设定， 本领域的技术 人员应当理解， 在不脱离本发明实质的范围内， 可以对本发明的器件结构做一定的变形或修 改， 测试电压也不限于实施例所公开的内容。

Claims

权 利 要 求 书
1、 一种用于肖特基源漏 SOI场效应晶体管的散热结构， 其特征在于， 在肖特基源漏 S0I 场效应晶体管的漏端附近的 S0I衬底形成两个孔，孔内分别填充 N型和 P型高热电常数材料， 所述 N型和 P型高热电常数材料与场效应晶体管的漏端连接， 所述连接处均为欧姆接触， 且 所述 N型高热电常数材料的金属引线相对于漏端接高电位， 所述 P型高热电常数材料的金属 引线， 相对于漏端接低电位， 当器件不工作或不需要进行散热时， 上述高热电常数材料连接 的金属电位均与漏电压相等。
2、 一种用于肖特基源漏 S0I场效应晶体管的散热结构， 其特征在于， 在肖特基源漏 S0I 场效应晶体管的漏端附近的 S0I衬底形成两个孔，孔内分别填充 N型和 P型高热电常数材料， 所述 N型和 P型高热电常数材料与场效应晶体管的漏端连接， 所述连接处均为欧姆接触； 在 肖特基源漏 S0I场效应晶体管的源端附近的 S0I衬底也形成两个孔， 孔内分别填充 N型和 P 型高热电常数材料， 源端附近的 N型和 P型高热电常数材料与场效应晶体管的源端连接， 所 述连接处均为欧姆接触； 漏端附近的 N型高热电常数材料的金属引线相对于漏端接高电位， 漏端附近的 P型高热电常数材料的金属引线相对于漏端接低电位； 源端附近的 N型高热电常 数材料的金属引线相对于源端接高电位， 源端附近的 P型材料的金属引线相对于源端接低电 位； 当器件不工作或不需要进行散热时， 源端附近的高热电常数材料连接的金属电位均与源 电压相等； 漏端附近的高热电常数材料连接的金属电位均与漏电压相等。
3、如权利要求 1或 2所述散热结构，其特征在于，所述高热电常数材料为 Bi2Te3和 Bi2Sb 等常见 V-VI族化合物半导体、 纳米高热电常数材料或者其他高热电常数材料。
4、 如权利要求 1或 2所述散热结构， 其特征在于， 所述 N型和 P型高热电常数材料均重 掺， 且电阻值相同。
5、 如权利要求 1或 2所述的散热结构， 其特征在于， 针对肖特基源漏 S0I场效应晶体管 的源、 漏长为 0. 4um， 宽为 0. 8um的结构， 所述孔的长度小于 0. 4um， 孔的宽度小于 0. 25um， 最小尺寸由光刻条件限制。
6、 如权利要求 5所述的散热结构， 其特征在于， 位于肖特基源漏 S0I场效应晶体管的漏 端或源端附近的两个孔的距离大于 0. 3um。
PCT/CN2011/078507 2010-08-23 2011-08-17 一种soi场效应晶体管的散热结构 WO2012025025A1 (zh)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9559283B2 (en) 2015-03-30 2017-01-31 International Business Machines Corporation Integrated circuit cooling using embedded peltier micro-vias in substrate
US9941458B2 (en) 2015-03-30 2018-04-10 International Business Machines Corporation Integrated circuit cooling using embedded peltier micro-vias in substrate

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101930954B (zh) * 2010-08-23 2012-02-15 北京大学 一种soi场效应晶体管的散热结构
US9748340B2 (en) * 2012-03-22 2017-08-29 Quantum Devices, Llc Graphene field effect transistor
US9059269B2 (en) * 2013-01-10 2015-06-16 International Business Machines Corporation Silicon-on-insulator heat sink
US10825752B2 (en) * 2013-06-18 2020-11-03 Intel Corporation Integrated thermoelectric cooling
US9029949B2 (en) 2013-09-25 2015-05-12 International Business Machines Corporation Semiconductor-on-insulator (SOI) structures with local heat dissipater(s) and methods
US9018754B2 (en) 2013-09-30 2015-04-28 International Business Machines Corporation Heat dissipative electrical isolation/insulation structure for semiconductor devices and method of making
TWI695513B (zh) * 2015-03-27 2020-06-01 日商半導體能源研究所股份有限公司 半導體裝置及電子裝置
KR102343223B1 (ko) * 2015-07-16 2021-12-23 삼성전자주식회사 반도체 장치 및 이의 제조 방법
CN107039372B (zh) * 2016-02-04 2019-05-28 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN105870083B (zh) * 2016-05-31 2019-01-18 福州大学 采用微热电发电机的3d芯片及其实现方法
US9773717B1 (en) 2016-08-22 2017-09-26 Globalfoundries Inc. Integrated circuits with peltier cooling provided by back-end wiring

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6674128B1 (en) * 2001-04-27 2004-01-06 Advanced Micro Devices, Inc. Semiconductor-on-insulator device with thermoelectric cooler on surface
US6800933B1 (en) * 2001-04-23 2004-10-05 Advanced Micro Devices, Inc. Integrated circuit cooling device
US7250327B2 (en) * 2004-06-30 2007-07-31 Intel Corporation Silicon die substrate manufacturing process and silicon die substrate with integrated cooling mechanism
US7541644B2 (en) * 2003-05-23 2009-06-02 Renesas Technology Corp. Semiconductor device with effective heat-radiation
CN101930954A (zh) * 2010-08-23 2010-12-29 北京大学 一种soi场效应晶体管的散热结构

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11214598A (ja) * 1998-01-23 1999-08-06 Takeshi Aoki 大規模集積回路（ｌｓｉ）チップの冷却方法
US6034408A (en) * 1998-05-14 2000-03-07 International Business Machines Corporation Solid state thermal switch
US6476483B1 (en) * 1999-10-20 2002-11-05 International Business Machines Corporation Method and apparatus for cooling a silicon on insulator device
DE10052170C2 (de) * 2000-10-20 2002-10-31 Infineon Technologies Ag Mittels Feldeffekt steuerbares Halbleiterbauelement
JP2003101082A (ja) * 2001-09-27 2003-04-04 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP3637388B2 (ja) * 2001-11-01 2005-04-13 独立行政法人産業技術総合研究所 ペルチェ効果を利用した冷却方法及び装置
DE10321222A1 (de) * 2003-05-12 2004-12-23 Infineon Technologies Ag Halbleiterbauelement
JP2009016418A (ja) * 2007-07-02 2009-01-22 Nec Electronics Corp 半導体装置
DE102008049726B4 (de) * 2008-09-30 2012-02-09 Advanced Micro Devices, Inc. Gestapelte Chipkonfiguration mit stromgespeistem Wärmeübertragungssystem und Verfahren zum Steuern der Temperatur in einem Halbleiterbauelement
JP5367413B2 (ja) * 2009-03-02 2013-12-11 ラピスセミコンダクタ株式会社 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6800933B1 (en) * 2001-04-23 2004-10-05 Advanced Micro Devices, Inc. Integrated circuit cooling device
US6674128B1 (en) * 2001-04-27 2004-01-06 Advanced Micro Devices, Inc. Semiconductor-on-insulator device with thermoelectric cooler on surface
US7541644B2 (en) * 2003-05-23 2009-06-02 Renesas Technology Corp. Semiconductor device with effective heat-radiation
US7250327B2 (en) * 2004-06-30 2007-07-31 Intel Corporation Silicon die substrate manufacturing process and silicon die substrate with integrated cooling mechanism
CN101930954A (zh) * 2010-08-23 2010-12-29 北京大学 一种soi场效应晶体管的散热结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9559283B2 (en) 2015-03-30 2017-01-31 International Business Machines Corporation Integrated circuit cooling using embedded peltier micro-vias in substrate
US9941458B2 (en) 2015-03-30 2018-04-10 International Business Machines Corporation Integrated circuit cooling using embedded peltier micro-vias in substrate

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