WO2012023902A1 - Circuit flexible et son procédé de production - Google Patents

Circuit flexible et son procédé de production Download PDF

Info

Publication number
WO2012023902A1
WO2012023902A1 PCT/SG2010/000303 SG2010000303W WO2012023902A1 WO 2012023902 A1 WO2012023902 A1 WO 2012023902A1 SG 2010000303 W SG2010000303 W SG 2010000303W WO 2012023902 A1 WO2012023902 A1 WO 2012023902A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductive
thermoplastic polyimide
polyimide layer
coverlay
Prior art date
Application number
PCT/SG2010/000303
Other languages
English (en)
Inventor
Ravi Palaniswamy
Fong Liang Tan
Original Assignee
3M Innovative Properties Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 3M Innovative Properties Company filed Critical 3M Innovative Properties Company
Priority to PCT/SG2010/000303 priority Critical patent/WO2012023902A1/fr
Priority to TW100129451A priority patent/TW201215264A/zh
Publication of WO2012023902A1 publication Critical patent/WO2012023902A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/281—Applying non-metallic protective coatings by means of a preformed insulating foil
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials

Definitions

  • the present invention relates to methods for producing flexible members, and in particular flexible circuits, such as ones which are suitable for use in printer heads.
  • a common method of forming a flexible circuit is referred to here as a "subtractive process".
  • the starting material is a flexible dielectric layer covered by a layer of adhesive.
  • Various apertures (such as die windows, sprocket holes, tooling holes etc) are formed in the dielectric layer by a punching process.
  • a layer of copper is laminated onto the adhesive. Patterned photo-resist is formed on the copper. Then, the copper is etched through gaps in the photo-resist. Then the photo-resist is removed, leaving a pattern of circuitry ("electrodes"). Then a coverlay is adhered over the electrodes.
  • Each electrode has the same thickness as the laminated copper layer. The thickness of the electrodes is sufficient for low current applications, but not for high current applications, such as printer heads.
  • the electrodes tend to be trapezoidal in cross- section, tapering in the direction away from the flexible dielectric layer. This means that to achieve a given cross-sectional area with a given thickness of copper, the base of the electrodes must be wider than it would be if the electrodes were rectangular in cross- section. This makes it harder to achieve miniaturization.
  • the subtractive process produced electrodes having a thickness of about 30 ⁇ shaped such that, for their lowest 15 ⁇ , the angle between the surface of the dielectric layer and the sides of the electrodes was less than 70 degrees.
  • UPISEL N a material known by the trade designation "UPISEL N”
  • UPISEL N a material known by the trade designation "UPISEL N”
  • UPISEL N a flexible dielectric substrate of the polyimide material known by the trade designation "UPILEX S”, which is also available commercially from Ube-Nitto Kasei Co. Ltd., Japan, having a thickness of approximately 42 ⁇ and made from biphenyldicarboxylicacid dianhydride (BBDA) and phenyl diamine (PDA).
  • BBDA biphenyldicarboxylicacid dianhydride
  • PDA phenyl diamine
  • the UPILEX S sheet is covered, on one or both sides, with approximately 4 pan thermoplastic polyimide layer, onto which a layer of copper has been laminated.
  • the copper on commercially available UPISEL N comes in a variety of thicknesses, e.g., 35 pm , 18 pan , 12 pan , and 3 pan .
  • Using a subtractive etching process with the thicker copper layers would require the removal of a substantial amount of copper, which is inefficient and costly.
  • Using a subtractive process with the 3 pan layer would result in electi des having no greater thickness than 3 pan .
  • Such thin electrodes are only suitable for the production of products such as Liquid Crystal Displays (LCDs) and integrated circuit (IC) packaging for which electrodes of this thickness are acceptable.
  • the present invention aims to produce a new and useful flexible member, such as a flexible circuit.
  • One aspect of the invention provides that a structure comprising a flexible dielectric film supporting a thermoplastic polyimide layer on at least one side, and on it a laminated conductive layer, is treated by a "semi-additive" process.
  • the semi-additive process comprises forming a patterned photo-resist layer, filling gaps in the photo-resist layer with conductive material, removing the photo-resist and exposed portions of the laminated conductive layer, and then adhering a coverlay onto the structure.
  • the present inventors have realized that the process of laminating the conductive layer onto the thermoplastic polyimide layer roughens the surface of the thermoplastic polyimide layer as it conforms to the shape of the surface of the conductive layer during lamination, thus anchoring the conductive layer to the polyimide.
  • UPISEL N An example of a structure on which the semi-additive process can be performed is the form of UPISEL N described above, which has a laminated layer of either rolled copper foil or electro-deposited copper foil. As noted, this material has not previously been used in a semi-additive process, and was designed for use in a subtractive process. Some previous applications of the semi-additive method have employed as a starting material a layer of a polyimide film available under the trade designation "KAPTON E" from DuPont, which does not include a thermoplastic layer. The present inventors have found that certain embodiments of the present invention have lower surface degradation than products formed using KAPTON E because the thermoplastic polyimide provides high resistance to hydrolysis.
  • the embodiments of the present invention provide improved resistance to trace delamination due to corrosion caused by ink ingression.
  • they provide superior dry and wet peel properties over known constructions with KAPTON E film, as well as less waviness and warpage and much better reliability. While the KAPTON E products may be suitable for many
  • embodiments of the present invention can provide an advantage.
  • Figs. 1 A- IF illustrate steps of a method which is an embodiment of the invention.
  • Fig. 2 is a flow diagram of the method of Figs. 1A-1F.
  • the process involves a semi-additive process performed on a product illustrated in cross-sectional view in Fig. 1 A.
  • the structure comprises a flexible dielectric substrate 1 , a thermoplastic polyimide (TPPI) layer 2 and a copper layer 3 laminated onto the TPPI layer 2.
  • the lamination process is performed at a temperature of at least about 350 degrees C and produces surface roughness in the TPPI layer that is the negative image of the copper surface to which the TPPI layer is laminated.
  • the TPPI layer Before the lamination, the TPPI layer may have roughness on the nanometer level (for example, the upper surface of the layer may have a standard deviation from its mean level of less than lOOnm), but afterwards the roughness is on the micrometer level, which may be defined as having a standard deviation from its mean level of at least 0.5 pirn , and more preferably in the range 0.6 ⁇ and 3 ⁇ .
  • the lower surface of the copper layer 3 may have a nodular structure with the same, or a different, degree of roughness.
  • Such a structure can be produced using the commercially available SR and SE series of the product UPISEL N available under the trade designation SE0320YSB or
  • SE0320MSH which include a structure similar to that shown in Fig. 1 A. That is, a flexible polyimide dielectric substrate is covered on one side with a TPPI layer, onto which a rolled or electro-deposited copper foil layer of thickness 3 ⁇ has been laminated. However, in some forms the laminated copper layer is covered by a thick copper carrier layer.
  • the UPISEL N has a carrier layer
  • this carrier layer is removed in a first processing step shown as step 1 1 of Fig. 2, to form the structure of Fig. 1 A.
  • the layer 3 typically has a thickness of 3 ⁇
  • the roughness of the TPPI layer 2 is between 0.6 j in and 3 ⁇ ⁇ ⁇ . This is the standard deviation of portions of the interface from the average level of the interface. It can also be termed the "nominal thickness" of the nodules on the laminated rolled copper foil layer. In different versions of UPISEL N the nominal thickness of the nodules is different, depending upon the intended application.
  • UPISEL N another form of UPISEL N exists in which the flexible polyimide dielectric substrate is covered on both sides by, in order, a TPPI layer, a laminated copper layer, and a thick copper earner layer that form a multilayer structure.
  • the laminated copper layer has a nodular structure.
  • the nominal thickness of the nodules need not be the same on both sides of the structure.
  • This form of UPISEL N can also be employed in the present invention. Specifically, the processing steps described below can be performed as desired on either or both of the sides of the structure. Before performing the processing steps described below on either of the sides of the structure, the copper carrier layer is removed from that side of the structure.
  • apertures may be formed in the structure, but that process, which may be canied out using a conventional punching procedure, or otherwise, will not be described further here.
  • photo-resist 4 is deposited and patterned over the laminated copper layer 3. to give the structure of Fig. I B.
  • step 13 of Fig. 2 copper is deposited by electroplating to a desired thickness, e.g., 40 ⁇ in the illustrated embodiment, into the gaps in the photo-resist 4, covering the thin copper layer 3 in the regions where it is exposed, as shown in Fig. 1 C.
  • the deposited copper 5 is joined to the laminated copper layer 3.
  • step 14 of Fig. 2 the photo-resist 4 is then removed, exposing parts of the thin copper layer 3, as shown in Fig. I D.
  • step 15 the exposed portions of the thin copper layer 3 are etched away, thus exposing corresponding portions of the roughened TPPI layer.
  • the upper portion of deposited copper 5 is also inadvertently etched away.
  • Fig. IE the structure of Fig. IE, in which the TPPI layer is indicated as layer 7 having an exposed rough upper surface in the portions marked by shading.
  • the remaining portions of the copper layer 3 and the deposited copper 5 overlying them together form bodies 6 of copper which have a desired thickness and are well-fixed to the TPPI layer 7 due to the nodular teeth of the lower surface of the bodies 6.
  • an adhesive 8 and cover film 9 are then laminated over the structure, together forming a coverlay.
  • the structure is then cured. This gives the structure of Fig. IF.
  • the coverlay like the remaining copper, is strongly retained on the rough TPPI layer 7.
  • the coverlay may be a Elephane CL-XU4013 from Tomoegawa Industries Ltd in which the adhesive 8 is a polyamide/phenolic adhesive of thickness 40 ⁇ and is coated on a cover film 9 of UPILEX SN which UPILEX SN films are available from Ube-Nitto Kasei Co. Ltd. and which have a thickness of 13 pan prior to the lamination.
  • Ex. 1-5 were made from a 20" (50.80cm) width x 50m length section of UPISEL N available under the trade designation SE0320YSB from Ube-Nitto Kasei Co. Ltd.
  • the section of UPISEL N was first slit into 13.4" (34.04cm) width strips. Following removal of the 18 ⁇ copper carrier layer, apertures were formed in the UPISEL N by a punching process. It was then subjected to a semi-additive process on one of its two sides in the same manner as described above. After the photo-resist was applied and patterned, about 45 pan of copper was electro-deposited onto the exposed portions of the laminated copper.
  • the exposed portions of the laminated copper layer were etched away, to give electrodes of thickness of about 35 ⁇ between exposed portions of the TPPI layer.
  • the electrodes had a generally rectangular cross-section, and the angles between their side-walls and the surface of the TPPI layer was about 81.4 degrees.
  • the UPILEX S has a relatively small coefficient of thermal expansion compared to the copper, which means that it experiences little heat shrinkage, giving good dimensional stability.
  • C. E. A was made using a 14" (35.56cm) width x 50m roll of KAPTON E having a thickness of 50 ⁇ as the starting material.
  • KAPTON E is a flexible polyimide material, but does not carry a surface layer of thermoplastic polyimide.
  • the KAPTON E was processed by first seeding a 2-20nm thin chrome (Cr) tie layer onto one face of the KAPTON E by vacuum deposition, then depositing a thin copper layer of thickness about lOOnm onto the tie layer by vacuum deposition to form a conductive surface. The substrate was then subjected to electroplating to build up the thin copper layer to a thickness of about 3 ⁇ . This provided a structure similar to the UPISEL N starting material of Ex. 1-5.
  • the structure was then subjected to a semi-additive process in the same manner as Ex. 1-5., in which about 45 ⁇ of copper were electro-deposited using a patterned photo-resist. Then after the photo-resist was removed, the exposed portions of the 3 ⁇ copper layer and the underlying nodular copper layer was etched away. This resulted electrodes of thickness 35 ⁇ between exposed portions of the polyimide layer.
  • the 14" (35.56cm) web was then slit down into 7cm width strips and it was then cut into individual patterned circuits.
  • Ex. 6-10 and C.E. B were made, respectively, by applying a coverlay material made of a 13 ⁇ thickness of UPISEL SN cover layer and 40 ⁇ adhesive layer, available under the trade designation Elephane CL-XU 4013 from Tomoegwawa Co. Ltd. Japan, to Ex. l-5 and C.E. A.
  • the coverlay was cut into pieces with respective pattern by a die cut method and was pre-tacked by placing the individual pieces of coverlay manually onto the individual circuit in a 7cm width roll and pressed down using heated flat pins (about 160 degrees C) for about 4secs. Lamination of the pre-tacked coverlay onto the circuits were carried out by applying a pressure of about 200psi (pounds per square inch) (1.38x10° Nm "2 ) at about 180 degrees C temperature for about 6secs.
  • the laminated circuits in a 7cm width reel form were then subjected to a curing process.
  • the curing profile was employed with heating from 30 degrees C to 90 degrees C with increments of 10 degrees C per minute and allowed to stay at about 90 degrees C for about 60mins and then ramped up to 180 degrees C by increments of 10 degrees C per minute. After allowing the circuits to maintain at a temperature of about 1 SO degrees C for about 2hrs, the temperature was slowly reduced to 30 degrees C over a period of 2hrs.
  • the coverlay laminated resulting circuits were cut into individual circuits of 48mm x 27mm and subjected to an ink vapor test in which the circuit samples were suspended in a sealed vessel in a space above alkaline liquid ink at an elevated temperature of 100 degrees C for 3 days.
  • Table 1 shows the results for Ex. 6-10, and their average result.
  • the results for C.E. B are the average of 5 samples.
  • the numbers in Table 1 are the peel strength, measured in pounds (lbs) (one pound is 4.45N).
  • Ex. 1 1 was made by taking a 10cm x 48mm section of UPISEL N available under the trade designation SE0320YSB, completely removing the laminated copper layer, and laminating a coverlay Elephane CL-XU4013 from Tomoegawa Industries Ltd where the coverlay consists of a polyamide/phenolic adhesive of thickness 40 coated on a cover film of 13 ⁇ UPILEX SN where UPILEX SN films are available from Ube- Nitto Kasei Co. Ltd.
  • the laminated structures were then subjected to a curing process.
  • the curing profile was employed with heating from about 30 degrees C to about 90 degrees C with increments of 10 degrees C per minute and allowed to stay at about 90 degrees C for about 60mins.
  • the temperature was later ramped up to about 180 degrees C by increments of 10 degrees C per minute. After allowing the temperature to stay at about 180 degrees C for about 2hrs, the laminated structures were then slowly cooled to about 30 degrees C over a period of 2hrs.
  • C.E. C was made by taking a 0.51 cm x 48mm section of KAPTON 2E known as KAPTON 200E available from DuPont and directly laminating the coverlay to it in the same manner as for Ex. 1 1, and then curing the structure in the same manner as for Ex. 1 1.

Abstract

L'invention concerne une structure comprenant un film diélectrique flexible supportant au moins sur un côté une couche polyimide thermoplastique et une couche conductrice déposée sur ladite couche polyimide thermoplastique, traitée au moyen d'un procédé semi-additif. Ledit procédé consiste : à former une couche de résine photosensible à motifs, à remplir les espaces de la couche de résine photosensible d'un matériau conducteur, à éliminer la résine photosensible et les parties exposées de la couche conductrice stratifiée, et à revêtir la structure d'un revêtement. Les inventeurs ont découvert que le procédé de stratification d'une couche de cuivre sur la couche polyimide thermoplastique rend sa surface rugueuse, permettant ainsi d'ancrer la couche de cuivre sur le polyimide, ce qui signifie que lorsque le matériau conducteur est déposé dans les espaces de la résine photosensible, des corps conducteurs fortement ancrés dans la couche polyimide thermoplastique sont formés, et peuvent être utilisés en tant qu'électrodes dans un circuit flexible.
PCT/SG2010/000303 2010-08-18 2010-08-18 Circuit flexible et son procédé de production WO2012023902A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/SG2010/000303 WO2012023902A1 (fr) 2010-08-18 2010-08-18 Circuit flexible et son procédé de production
TW100129451A TW201215264A (en) 2010-08-18 2011-08-17 A flexible circuit and a method of producing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2010/000303 WO2012023902A1 (fr) 2010-08-18 2010-08-18 Circuit flexible et son procédé de production

Publications (1)

Publication Number Publication Date
WO2012023902A1 true WO2012023902A1 (fr) 2012-02-23

Family

ID=45605355

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2010/000303 WO2012023902A1 (fr) 2010-08-18 2010-08-18 Circuit flexible et son procédé de production

Country Status (2)

Country Link
TW (1) TW201215264A (fr)
WO (1) WO2012023902A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020131514A3 (fr) * 2018-12-17 2020-08-06 Instrumentation Laboratory Company Hématocrite et capteur de niveau de liquide

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415659A2 (fr) * 1989-08-28 1991-03-06 Sumitomo Metal Mining Company Limited Procédé pour fabriquer un support de film à deux couches
US5217849A (en) * 1989-08-28 1993-06-08 Sumitomo Metal Mining Company Limited Process for making a two-layer film carrier
US5721007A (en) * 1994-09-08 1998-02-24 The Whitaker Corporation Process for low density additive flexible circuits and harnesses
EP1519640A1 (fr) * 2003-09-29 2005-03-30 Nitto Denko Corporation Procédé de fabrication d'un panneau à circuit flexible
EP1648209A1 (fr) * 2004-10-13 2006-04-19 Nitto Denko Corporation Procédé de fabrication d'une carte de circuit imprimé
US20090136725A1 (en) * 2006-03-24 2009-05-28 Hiroto Shimokawa Process for producing copper wiring polyimide film, and copper wiring polyimide film

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0415659A2 (fr) * 1989-08-28 1991-03-06 Sumitomo Metal Mining Company Limited Procédé pour fabriquer un support de film à deux couches
US5217849A (en) * 1989-08-28 1993-06-08 Sumitomo Metal Mining Company Limited Process for making a two-layer film carrier
US5721007A (en) * 1994-09-08 1998-02-24 The Whitaker Corporation Process for low density additive flexible circuits and harnesses
EP1519640A1 (fr) * 2003-09-29 2005-03-30 Nitto Denko Corporation Procédé de fabrication d'un panneau à circuit flexible
EP1648209A1 (fr) * 2004-10-13 2006-04-19 Nitto Denko Corporation Procédé de fabrication d'une carte de circuit imprimé
US20090136725A1 (en) * 2006-03-24 2009-05-28 Hiroto Shimokawa Process for producing copper wiring polyimide film, and copper wiring polyimide film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020131514A3 (fr) * 2018-12-17 2020-08-06 Instrumentation Laboratory Company Hématocrite et capteur de niveau de liquide
US11530941B2 (en) 2018-12-17 2022-12-20 Instrumentation Laboratory Company Hematocrit and liquid level sensor

Also Published As

Publication number Publication date
TW201215264A (en) 2012-04-01

Similar Documents

Publication Publication Date Title
KR101377060B1 (ko) 캐리어를 갖는 금속 호일
JP5320502B2 (ja) キャリア付き金属箔
TWI492675B (zh) 可剝離之附銅箔基板及電路基板之製造方法
KR20170104648A (ko) 코어리스 빌드업 지지 기판 및 당해 코어리스 빌드업 지지 기판을 사용하여 제조된 프린트 배선판
JP5266925B2 (ja) 金属化ポリイミドフィルムとその製造方法
US7605048B2 (en) Method for forming a capacitor having a copper electrode and a high surface area aluminum inner layer
JP4301924B2 (ja) 多角形状の剛性フレームと、該フレームに接着されて広がっている誘電体材料で作られた可撓性フィルムとを備える組立体
KR101664993B1 (ko) 캐리어 부착 극박 동박, 동 클래드 적층판 및 코어레스 기판
JP2009090570A (ja) ピーラブル金属箔およびその製造方法
WO2012023902A1 (fr) Circuit flexible et son procédé de production
JP7201405B2 (ja) 多層配線板の製造方法
JP6252988B2 (ja) ２層銅張積層板及びその製造方法、並びにそれを用いたフレキシブル配線板及びその製造方法
WO2016031559A1 (fr) Procédé de fabrication d'une carte de câblage en cuivre, souple, et carte stratifiée cuivrée souple comprenant un film support utilisé dans cette carte de câblage en cuivre
JP4872957B2 (ja) 電子部品の製造方法
JP6341644B2 (ja) キャリヤ付き金属箔および積層基板の製造方法
KR20200060228A (ko) 플렉시블 기판
JP6600985B2 (ja) ロール状積層基板の製造方法及び積層基板
KR102493654B1 (ko) 반도체 패키지용 캐리어 및 이의 제조방법
JP6252989B2 (ja) ２層銅張積層板及びその製造方法、並びにそれを用いたフレキシブル配線板及びその製造方法
JP2008177302A (ja) プリント基板の製造方法
JP5343390B2 (ja) マスクの製造方法
JP2009277810A (ja) 長尺状基板及び基板接合テープ
JP6520818B2 (ja) 金属化樹脂フィルムの製造方法
US20240090138A1 (en) Prepreg with metal layer, method for manufacturing laminate, and method for manufacturing prepreg with metal layer
JP2004330701A (ja) プリント回路形成等に使用される銅箔を備えた複合体とその製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10856225

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10856225

Country of ref document: EP

Kind code of ref document: A1