WO2012023826A3 - 무선통신 시스템에서 디지털 위상 동기 루프 장치 및 방법 - Google Patents

무선통신 시스템에서 디지털 위상 동기 루프 장치 및 방법 Download PDF

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Publication number
WO2012023826A3
WO2012023826A3 PCT/KR2011/006115 KR2011006115W WO2012023826A3 WO 2012023826 A3 WO2012023826 A3 WO 2012023826A3 KR 2011006115 W KR2011006115 W KR 2011006115W WO 2012023826 A3 WO2012023826 A3 WO 2012023826A3
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WO
WIPO (PCT)
Prior art keywords
digital
signal
indicates
generates
wireless communication
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Application number
PCT/KR2011/006115
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English (en)
French (fr)
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WO2012023826A2 (ko
Inventor
이강윤
부영건
박안수
박준성
이재섭
Original Assignee
삼성전자주식회사
건국대학교 산학협력단
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사, 건국대학교 산학협력단 filed Critical 삼성전자주식회사
Priority to EP11818426.6A priority Critical patent/EP2608413B1/en
Priority to US13/817,816 priority patent/US8604851B2/en
Publication of WO2012023826A2 publication Critical patent/WO2012023826A2/ko
Publication of WO2012023826A3 publication Critical patent/WO2012023826A3/ko

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/50All digital phase-locked loop
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

본 발명은 무선통신 시스템에서 디지털 PLL(Phase Loop Lock)에 관한 것으로, PLL은, 입력되는 디지털 튜닝 워드(DTW : Digital Tuning Word)에 따라 주파수 신호를 생성하는 DCO(Digitally Controlled Oscillator)와, 상기 주파수 신호를 정수 비율로 분주하는 분주기와, 분주된 주파수 신호 및 참고 신호의 위상 차를 나타내는 신호를 생성하는 PFD(Phase Frequency Detector)와, 상기 위상 차를 나타내는 신호를 이용하여 상기 위상 차의 시간 간격을 측정하는 TDC(Time to Digital Convertor)와, 상기 TDC에 의해 측정된 값들로부터 상승 엣지가 일치한 경우의 시간 간격을 산출하는 지연 비교기와, 상기 시간 간격을 나타내는 디지털 코드를 이용하여 상기 DCO를 동작시킬 디지털 튜닝 워드를 생성하는 레벨 스케일러를 포함한다.
PCT/KR2011/006115 2010-08-19 2011-08-19 무선통신 시스템에서 디지털 위상 동기 루프 장치 및 방법 WO2012023826A2 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP11818426.6A EP2608413B1 (en) 2010-08-19 2011-08-19 Digital phase locked loop device and method in wireless communication system
US13/817,816 US8604851B2 (en) 2010-08-19 2011-08-19 Digital phase locked loop device and method in wireless communication system

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2010-0080080 2010-08-19
KR1020100080080A KR101729136B1 (ko) 2010-08-19 2010-08-19 무선통신 시스템에서 디지털 위상 동기 루프 장치 및 방법

Publications (2)

Publication Number Publication Date
WO2012023826A2 WO2012023826A2 (ko) 2012-02-23
WO2012023826A3 true WO2012023826A3 (ko) 2012-04-12

Family

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PCT/KR2011/006115 WO2012023826A2 (ko) 2010-08-19 2011-08-19 무선통신 시스템에서 디지털 위상 동기 루프 장치 및 방법

Country Status (4)

Country Link
US (1) US8604851B2 (ko)
EP (1) EP2608413B1 (ko)
KR (1) KR101729136B1 (ko)
WO (1) WO2012023826A2 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103501164A (zh) * 2013-09-24 2014-01-08 中国科学院声学研究所 一种时间放大器

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101729136B1 (ko) * 2010-08-19 2017-04-24 삼성전자주식회사 무선통신 시스템에서 디지털 위상 동기 루프 장치 및 방법
US8890592B2 (en) * 2012-10-13 2014-11-18 Infineon Technologies Ag Multi-output phase detector
US9007105B2 (en) * 2013-01-29 2015-04-14 Perceptia Devices Australia Pty Ltd Hitless switching phase-locked loop
KR20140113216A (ko) * 2013-03-15 2014-09-24 삼성전자주식회사 위상-디지털 컨버터를 이용한 디지털 위상 동기 루프 회로, 그 동작 방법 및 이를 포함하는 장치
JP6351058B2 (ja) * 2013-11-28 2018-07-04 株式会社メガチップス タイムデジタルコンバータ及びこれを用いたpll回路
KR101680935B1 (ko) 2013-12-13 2016-12-12 한양대학교 산학협력단 다중 적분 경로를 이용하는 디지털 위상 고정 루프 및 이의 동작 방법
JP6350120B2 (ja) * 2014-08-27 2018-07-04 富士通株式会社 Pll回路、pll回路の制御方法、及び電子機器
US9429919B2 (en) * 2014-11-17 2016-08-30 Intel Deutschland Gmbh Low power bipolar 360 degrees time to digital converter
US9838026B2 (en) * 2015-09-24 2017-12-05 Analog Devices, Inc. Apparatus and methods for fractional-N phase-locked loops with multi-phase oscillators
US9893875B2 (en) 2016-05-23 2018-02-13 Qualcomm Incorporated Phase continuity technique for frequency synthesis
US10856242B2 (en) 2016-11-21 2020-12-01 Phasorlab, Inc. Wireless time and frequency lock loop system
CN106788424B (zh) * 2016-11-30 2019-12-24 上海华力微电子有限公司 一种基于频率比较的锁定指示器
US10659064B1 (en) 2017-02-24 2020-05-19 Marvell Asia Pte, Ltd. Phase lock loop circuits and methods including multiplexed selection of feedback loop outputs of multiple phase interpolators
US10749534B2 (en) 2017-06-28 2020-08-18 Analog Devices, Inc. Apparatus and methods for system clock compensation
US10425091B2 (en) * 2017-10-31 2019-09-24 Texas Instruments Incorporated Fractional clock generator
US10707879B2 (en) * 2018-04-13 2020-07-07 KaiKuTek Inc. Frequency-modulated continuous-wave radar system and frequency tracking method for calibrating frequency gains of a radio frequency signal to approach wideband flatness frequency responses
CN109639271B (zh) * 2018-12-12 2023-08-11 上海华力集成电路制造有限公司 锁定指示电路及其构成的锁相环
KR102327251B1 (ko) * 2020-07-13 2021-11-17 한국전력공사 위상 보정 기능을 갖는 광 변성기용 머징 장치
US11909405B1 (en) * 2023-01-09 2024-02-20 Infineon Technologies Ag Digital coarse locking in digital phase-locked loops

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008537425A (ja) * 2005-04-18 2008-09-11 エヌエックスピー ビー ヴィ 位相ロックループ回路装置及びこれを利用したクロック信号発生方法
JP2010028452A (ja) * 2008-07-18 2010-02-04 Nikon Corp 画像処理装置および電子カメラ
JP2010098704A (ja) * 2008-10-16 2010-04-30 Renesas Technology Corp Pll回路
KR20100062888A (ko) * 2008-12-02 2010-06-10 한국전자통신연구원 주파수 합성기

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8045670B2 (en) * 2007-06-22 2011-10-25 Texas Instruments Incorporated Interpolative all-digital phase locked loop
US8022849B2 (en) * 2008-04-14 2011-09-20 Qualcomm, Incorporated Phase to digital converter in all digital phase locked loop
JP2010028457A (ja) 2008-07-18 2010-02-04 Sony Corp Pll回路並びに無線通信装置
JP5284131B2 (ja) * 2009-02-04 2013-09-11 株式会社東芝 位相同期回路及びこれを用いた受信機
KR101231743B1 (ko) * 2009-04-24 2013-02-08 한국전자통신연구원 디지털 락 검출장치 및 이를 포함하는 주파수 합성기
JP2012005022A (ja) * 2010-06-21 2012-01-05 Panasonic Corp デジタル位相差検出器およびそれを備えた周波数シンセサイザ
KR101729136B1 (ko) * 2010-08-19 2017-04-24 삼성전자주식회사 무선통신 시스템에서 디지털 위상 동기 루프 장치 및 방법
US8253458B2 (en) * 2011-01-11 2012-08-28 Freescale Semiconductor, Inc. Digital phase locked loop with reduced switching noise
US8634512B2 (en) * 2011-02-08 2014-01-21 Qualcomm Incorporated Two point modulation digital phase locked loop

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008537425A (ja) * 2005-04-18 2008-09-11 エヌエックスピー ビー ヴィ 位相ロックループ回路装置及びこれを利用したクロック信号発生方法
JP2010028452A (ja) * 2008-07-18 2010-02-04 Nikon Corp 画像処理装置および電子カメラ
JP2010098704A (ja) * 2008-10-16 2010-04-30 Renesas Technology Corp Pll回路
KR20100062888A (ko) * 2008-12-02 2010-06-10 한국전자통신연구원 주파수 합성기

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103501164A (zh) * 2013-09-24 2014-01-08 中国科学院声学研究所 一种时间放大器
CN103501164B (zh) * 2013-09-24 2017-01-18 中国科学院声学研究所 一种时间放大器

Also Published As

Publication number Publication date
WO2012023826A2 (ko) 2012-02-23
EP2608413B1 (en) 2018-05-30
EP2608413A4 (en) 2015-04-22
KR101729136B1 (ko) 2017-04-24
US20130147531A1 (en) 2013-06-13
US8604851B2 (en) 2013-12-10
KR20120057706A (ko) 2012-06-07
EP2608413A2 (en) 2013-06-26

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