WO2012023228A1 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
WO2012023228A1
WO2012023228A1 PCT/JP2011/003055 JP2011003055W WO2012023228A1 WO 2012023228 A1 WO2012023228 A1 WO 2012023228A1 JP 2011003055 W JP2011003055 W JP 2011003055W WO 2012023228 A1 WO2012023228 A1 WO 2012023228A1
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internal
semiconductor device
pads
pad
external
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PCT/JP2011/003055
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English (en)
French (fr)
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水谷　篤人
藤本　博昭
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パナソニック株式会社
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Definitions

  • the present disclosure relates to a semiconductor device in which a part of wiring in a semiconductor chip is formed by a bonding wire and a manufacturing method thereof.
  • the supply of the power supply voltage to the semiconductor chip is performed from the pad on the peripheral edge of the semiconductor chip toward the inside of the semiconductor chip via the wiring in the semiconductor chip.
  • increase in chip size and reduction in voltage are progressing.
  • a voltage drop occurs in the semiconductor chip, resulting in performance degradation.
  • Patent Document 1 As an example of a method for dealing with this.
  • pads 22 are provided in a lattice shape on the surface of the semiconductor chip 21, and the lattice-shaped pads 22 are connected to the external pads 23 at the periphery by bonding wires 24. .
  • the voltage of the power source supplied to the external pad 23 can be supplied near the center of the semiconductor chip 21 without causing a drop.
  • the size of the pads 22 arranged in a lattice pattern is the same as that of the external pads 23.
  • it is required to increase the chip size increase the number of wiring layers of the semiconductor chip by one or more.
  • a dedicated layer is used to form a grid pad, it is necessary to increase the wiring layer, and if a grid pad is formed using an existing wiring layer, the chip size must be increased. It is. This causes an increase in cost.
  • an object of the semiconductor device and the manufacturing method thereof of the present disclosure is to realize supply of power supply voltage to the semiconductor chip at low cost.
  • a semiconductor device includes a semiconductor chip, an external pad formed on a peripheral portion of the main surface of the semiconductor chip, and on the main surface and inside the external pad.
  • the plurality of internal pads are smaller than the external pads.
  • the internal pad is made smaller than the external pad.
  • Such a small internal pad can be formed by utilizing a part of the wiring layer provided in the semiconductor chip. Therefore, an increase in chip size can be suppressed, and there is no need to add a wiring layer.
  • the internal pads can be connected by a thin metal wire. As a result, a semiconductor device capable of reliably supplying power to the inside (near the center) of the semiconductor chip without causing a voltage drop can be realized at low cost.
  • one of the internal pads connected by the fine metal wire and the external pad are connected by the wiring in the semiconductor chip. However, since the connection distance is short, the voltage drop at this portion is not a problem.
  • curvature of the surface of the plurality of internal protruding electrodes may be larger than that of the external protruding electrodes.
  • the plurality of internal protruding electrodes may be larger than the internal pad.
  • metal balls connected to the internal protruding electrodes may be provided at both ends of the first fine metal wire, and the metal balls may be larger than the internal protruding electrodes.
  • connection can be made so as to cover the internal protruding electrode with the metal ball, the connection with the first fine metal wire can be more reliably performed.
  • the metal ball may be in contact with the protective film.
  • the bonding strength of the first fine metal wire is improved by bonding the metal ball and the protective film.
  • the protective film may have recesses around the plurality of internal pads, and the metal balls may be formed even in the recesses.
  • the bonding strength is further improved by the metal ball deforming and biting into the recess.
  • a metal ball may be formed so as to cover at least two internal protruding electrodes, and the at least two internal protruding electrodes may be electrically connected by the metal ball.
  • the metal ball functions as a jumper wiring that electrically connects the internal protruding electrodes. Therefore, multilayer wiring can be realized without increasing the number of wiring layers in the high-cost semiconductor chip.
  • a power supply potential or a ground potential may be supplied to at least one of the plurality of internal pads.
  • the power supply potential or the ground potential can be supplied into the semiconductor chip.
  • an in-chip wiring that electrically connects at least one of the plurality of internal pads electrically connected by the first metal thin wire and the external pad may be provided.
  • the voltage of the power supplied to the external pad is sequentially supplied to one of the external pad, the in-chip wiring, the internal pad, the first metal thin wire, and the other of the internal pad in order. It can be supplied to the vicinity of the center.
  • circuit elements may be formed on the semiconductor chip.
  • wiring may be formed in a layer in which a plurality of internal pads are formed in the semiconductor chip.
  • the internal pad when the internal pad is formed using the wiring layer, the internal pad can be realized without providing a new layer.
  • a wiring board on which a semiconductor chip is mounted may be further provided, and the semiconductor chip may be mounted on the wiring board.
  • the semiconductor chip and the wiring board may be electrically connected by a second thin metal wire.
  • the height of the uppermost portion of the first fine metal wire may be lower than the height of the uppermost portion of the second fine metal wire.
  • the internal protruding electrode may include at least a Ni layer and a noble metal layer formed thereon.
  • a method for manufacturing a semiconductor device includes a step (a) of forming an external pad on a peripheral portion of a main surface of a semiconductor chip, and a plurality of internal portions on the main surface and inside the external pad.
  • a step (b) of forming a pad, a step (c) of forming a protective film covering the main surface and having an opening on the external pad and the plurality of internal pads, and the internal pads are separated by a first metal wire. Electrically connecting step (d), and the internal pad is smaller than the external pad.
  • the method further includes a step (e) of forming an internal protruding electrode on each of the plurality of internal pads between the step (c) and the step (d).
  • the internal protruding electrodes are connected to each other. You may connect by the metal fine wire.
  • an external protruding electrode may be formed on the external pad, and the internal protruding electrode and the external protruding electrode may be formed using an electroless plating method.
  • the external protruding electrode can be used for electrical connection. Further, the internal protruding electrode and the external protruding electrode can be formed in the same process.
  • the step (d) includes a step of forming a first metal ball on the first internal protruding electrode among the plurality of internal protruding electrodes by a wire bonding method, and a plurality of internal protruding electrodes by the wire bonding method. And forming a thin metal wire from the second metal ball to the first metal ball after forming the second metal ball on the second internal protruding electrode. This may be done as a method of connection using a fine metal wire.
  • the internal pad formed using the wiring layer of the semiconductor chip can be remarkably reduced, and an increase in chip size due to the formation of the internal pad can be suppressed.
  • an additional wiring layer in a semiconductor chip that has been necessary in the past is not necessary, and a low-cost and highly reliable semiconductor device can be realized.
  • FIG. 1 is a plan view illustrating a semiconductor chip used in the exemplary semiconductor device according to the first embodiment of the present disclosure.
  • 2A to 2C are views showing a manufacturing process for the exemplary semiconductor device of the first embodiment.
  • FIG. 3 is a diagram illustrating the provision of a recess in the protective film around the protruding electrode in the exemplary semiconductor device of the first embodiment.
  • FIG. 4 is a plan view illustrating a state in which wire bonding is completed with respect to the exemplary semiconductor device of the first embodiment.
  • FIG. 5 is a plan view illustrating a semiconductor chip used in the exemplary semiconductor device according to the second embodiment of the present disclosure.
  • FIG. 6 is a diagram illustrating an exemplary semiconductor device according to the second embodiment.
  • FIG. 7 is a diagram showing a related-art semiconductor chip.
  • FIG. 1 is a plan view of a semiconductor chip 4 used in the exemplary semiconductor device 25 (see FIG. 2C) of this embodiment.
  • External pads 7 for electrically connecting the circuit in the semiconductor chip 4 and the outside are formed on the peripheral portion of the main surface of the semiconductor chip 4 in which elements and the like are formed.
  • a first internal pad 8 and a second internal pad 9 for electrical connection inside the semiconductor chip 4 are formed inside the external pad 7 on the main surface.
  • the external pad 7, the first internal pad 8, and the second internal pad 9 are formed using Al, Cu, or the like.
  • the first internal pad 8 is electrically connected to the pad supplied with the power supply potential or the pad supplied with the ground potential among the external pads 7 by wiring (in-chip wiring) provided in the semiconductor chip 4. It is connected to the.
  • the internal pads 8 and 9 (hereinafter, the first internal pad 8 and the second internal pad 9 may be referred to as such) and the external pad 7 are the same as the wiring layer in the semiconductor chip 4. Formed in layers. As shown in FIG. 1, the internal pads 8 and 9 are sufficiently smaller than the external pad 7. Thus, an increase in chip size due to the formation of the internal pads 8 and 9 can be suppressed. Further, the internal pads 8 and 9 can be provided by using an existing wiring layer (for example, a wiring layer including an in-chip wiring that electrically connects the first internal pad 8 and the external pad 7). No additional wiring layer is required. Therefore, a low-cost and highly reliable semiconductor device can be realized.
  • an existing wiring layer for example, a wiring layer including an in-chip wiring that electrically connects the first internal pad 8 and the external pad 7. No additional wiring layer is required. Therefore, a low-cost and highly reliable semiconductor device can be realized.
  • the external pad 7 has a square shape with a side length of about 50 ⁇ m to 100 ⁇ m
  • the first internal pad 8 and the second internal pad 9 are Each side has a square shape with a length of 0.5 ⁇ m to 15 ⁇ m.
  • the planar shape may be another polygon, a circle, an ellipse, or the like.
  • FIGS. 2A to 2C are cross-sectional views schematically showing steps for obtaining the semiconductor device 25 by mounting the semiconductor chip 4 on the package substrate (wiring substrate) 1.
  • one surface of the package substrate 1 is a mounting surface, and the package electrode 2 is provided on the surface and the semiconductor chip 4 is mounted thereon.
  • the external electrode 3 of the package substrate 1 is provided on the surface of the package substrate 1 opposite to the mounting surface.
  • the semiconductor chip 4 is fixed to the package substrate 1 using a resin 5.
  • a resin 5 a conductive resin such as an Ag paste may be used, or an insulating resin made of epoxy, polyimide, or the like may be used.
  • the semiconductor chip 4 includes the external pads 7 and the internal pads 8 and 9 on the upper surface. Further, a glass-based or resin-based protective film 6 such as polyimide is formed so as to cover the semiconductor chip 4.
  • the protective film 6 has openings on the external pad 7 and the internal pads 8 and 9.
  • internal protruding electrodes 11 and 12 are formed by, for example, electroless plating. Further, an external protruding electrode 10 is formed on the external pad 7 by electroless plating or the like.
  • Each of these protruding electrodes 10 to 12 (external protruding electrode 10, internal protruding electrodes 11 and 12) has a structure including, for example, a layer made of Ni, Cu or the like, and a layer formed thereon and made of Au, Pd or the like. is there.
  • the protruding electrodes 10 to 12 are formed by electroless plating at the wafer stage before the semiconductor chip 4 is cut into pieces. That is, by immersing the wafer in an electroless plating solution, a metal such as Ni in the plating solution is deposited on the external pad 7 and the internal pads 8 and 9 in the portion where the protective film 6 is opened, and each protruding electrode 10 to 12.
  • the protruding electrodes 10 to 12 are formed to have a thickness that reaches at least the surface of the protective film 6.
  • the thickness is about 1 ⁇ m to 10 ⁇ m.
  • the sectional shape having a large curvature (especially compared with the external protruding electrode 10 on the external pad 7). It becomes. That is, the upper surface of the external pad 7 is substantially flat (because the curvature is sufficiently small), whereas the internal pads 8 and 9 are more prominently projected (the surface has a large curvature).
  • a first metal ball 15 is bonded onto the internal protruding electrode 11 provided on the first internal pad 8.
  • a method called a ball bumping method, a stud bump method or the like can be used. That is, in the wire bonding step, the first metal ball 15 formed at the tip of the bonding wire is bonded onto the internal protruding electrode 11, and then the bonding wire is cut at the upper portion of the first metal ball 15. In this way, only the first metal ball 15 is left on the internal protruding electrode 11.
  • the first metal ball 15 is made of, for example, Au, Cu, Al or the like.
  • the size is, for example, about 15 ⁇ m to 150 ⁇ m in diameter, and can be controlled by the diameter of the bonding wire used.
  • the diameter of the bonding wire is, for example, about 10 ⁇ m to 50 ⁇ m.
  • the first metal ball 15 is joined by heating, pressurization, ultrasonic application, or the like.
  • the pressure is about 5 gf to 100 gf (0.049 N to 0.98 N), and the heating temperature is about 100 ° C. to 300 ° C.
  • the first metal ball 15 is made of Au, it is metal-bonded to Au or Pd, which is the surface metal of the protruding electrode 11. At this time, the size of the first metal ball 15 is set so as to cover the protruding electrode 11 on the first internal pad 8. Further, the first metal ball 15 may be in contact with the protective film 6 of the semiconductor chip 4.
  • the second metal ball 14 is formed on the second inner pad 9 and bonding for connecting the second metal ball 14 and the first metal ball 15 is performed.
  • a wire 16 is formed.
  • wire bonding using a wire ultrasonic thermocompression bonding method may be used.
  • ball bonding is performed with metal balls on the internal protruding electrodes 12 on the second internal pads 9, and other than bonding wires 16 on the metal balls 15 on the first internal pads 8.
  • edge bonding is performed. If it does in this way, only the metal ball of a wire bonding process will be used as a metal ball. As a result, any bonding can be performed by the same wire bonder, and the cost can be reduced.
  • the bonding of the second metal ball 14 to the internal protruding electrode 12 on the second internal pad 9 is performed in the same manner as the bonding of the first metal ball 15 to the internal protruding electrode 11 on the first internal pad 8. Good.
  • the first internal pad 8 and the second internal pad 9 are electrically connected via the bonding wire 16.
  • the first internal pad 8 is electrically connected to the external pad 7. Therefore, the power supply system circuit provided near the center of the semiconductor chip 4 is electrically connected to the power supply system pad of the external pad 7.
  • irregularities in the example of FIG. 3, concave portions 21 may be provided on the surface of the protective film 6 around the internal protruding electrodes 11 and 12. If it does in this way, since metal balls 14 and 15 (the 1st metal ball 15 and the 2nd metal ball 14) will change according to unevenness, and will be in a shape to bite in, joint strength will improve by an anchor effect.
  • the bonding surface area with respect to the metal balls 14 and 15 increases even if the size is small, so that the bonding strength is improved. That is, since the protruding electrode having a shape with a large curvature (for example, it may be considered as a sharp shape) is in a state of being bitten into the metal ball (compared to a state in which flat objects are in contact with each other), bonding is strengthened. .
  • a circuit element such as a transistor or a wiring may be provided in a region below the metal balls 14 and 15 in the semiconductor chip 4. Since the internal electrode is small, a wiring can be formed in the same layer as the internal electrode, and a transistor connected to the wiring can also be arranged.
  • the diameter of the bonding wire 16 is about 10 ⁇ m to 50 ⁇ m, and is selected based on the value of current flowing through the bonding wire 16.
  • the diameter of the metal ball generally increases when a thick bonding wire is used.
  • the size of the semiconductor chip 4 can be reduced because the small internal pads 8 and 9 are used.
  • the height of the uppermost portion of the bonding wire 16 can be reduced. Specifically, for example, the height can be set to about 20 ⁇ m to 50 ⁇ m from the upper surface of the second metal ball 14, and the bonding wire 16 can be shortened.
  • the height of the bonding wire 17 is, for example, about 100 ⁇ m to 300 ⁇ m.
  • the external protruding electrode 10 on the external pad 7 of the semiconductor chip 4 and the package electrode 2 of the package substrate 1 are connected by wire bonding using the bonding wire 17.
  • a third metal ball 13 is formed on the external protruding electrode 10.
  • the external pad 7 and the package electrode 2 are electrically connected. However, this order may be reversed.
  • FIG. 4 shows a plan view of the semiconductor chip 4 mounted on the package substrate 1 in a state where the wire bonding by the bonding wire 16 and the bonding wire 17 is completed.
  • the first internal pad 8 is provided below the metal ball 15 and is electrically connected to the external pad 7 by wiring in the semiconductor chip 4 (not shown). Accordingly, the circuit elements and the like in the semiconductor chip 4 connected to the second internal pad 9 below the metal ball 14 are electrically connected to the external pad 7.
  • the semiconductor chip 4 and the bonding wires 16 and 17 are molded using a sealing resin 18 so as to cover them.
  • the sealing resin 18 is made of a thermosetting epoxy resin or the like, and uses, for example, a transfer mold method. Thus, the semiconductor device 25 is manufactured.
  • FIG. 5 is a plan view of the semiconductor chip 4a used in the exemplary semiconductor device 25a of the present embodiment.
  • FIG. 6 shows the mounting of the semiconductor chip 4a on the package substrate 1, electrical connection using bonding wires, and resin sealing. It is sectional drawing which shows the semiconductor device 25a which completed up to.
  • the same components as those in the first embodiment are denoted by the same reference numerals, and differences will be mainly described below.
  • the semiconductor chip 4a has a structure that further includes a third internal pad 19 in the vicinity of the second internal pad 9 in addition to the same configuration as the semiconductor chip 4 of the first embodiment (see FIG. 1).
  • the first internal pad 8 is electrically connected to a power supply pad or a ground pad among the external pads 7 by wiring in the semiconductor chip 4.
  • the second internal pad 9 is connected to the first power supply circuit in the semiconductor chip 4a, and the third internal pad 19 is connected to the second power supply circuit in the semiconductor chip 4a.
  • the second inner pad 9 and the third inner pad 19 are arranged so as not to be in direct contact with each other.
  • the wiring of the semiconductor chip 4a is formed between the second internal pad 9 and the third internal pad 19 (so as not to be connected to the second internal pad 9 and the third internal pad 19). (Illustration omitted).
  • each internal pad may be the same as in the first embodiment.
  • a protruding electrode 20 is formed.
  • the second metal ball 14 is bonded to the internal protruding electrode 20 on the third internal pad 19 in addition to the internal protruding electrode 12 on the second internal pad 9 so as to cover them together. Is formed. As a result, the second internal pad 9 and the third internal pad 19 are electrically connected via the second metal ball 14.
  • the wiring is formed in the semiconductor chip 4 a between the second internal pad 9 and the third internal pad 19, the wiring is partially jumpered by the metal balls 14.
  • multilayer wiring can be realized without using a multilayer wiring layer in the high-cost semiconductor chip 4a, and the cost can be reduced.
  • the semiconductor device and the manufacturing method thereof of the present disclosure it is possible to realize high functionality and low cost while suppressing an increase in chip size. For example, in a large-scale system LSI used in the field of digital television and the like Useful.

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Abstract

　半導体装置（２５）は、半導体チップ（４）と、半導体チップ（４）の主面の周縁部上に形成された外部パッド（７）と、主面上であって、外部パッド（７）よりも内側に形成された複数の内部パッド（８及び９）と、主面上を覆い、外部パッド（７）上及び複数の内部パッド（８及び９）上に開口を有する保護膜（６）と、内部パッド同士を電気的に接続する第１の金属細線（１６）とを備える。複数の内部パッド（８及び９）は、外部パッド（７）よりも小さい。

Description

半導体装置及びその製造方法
　本開示は、半導体チップ内の配線の一部をボンディングワイヤにて行う半導体装置及びその製造方法に関するものである。
　従来、半導体チップに対する電源電圧の供給は、半導体チップの周縁部のパッドから半導体チップの内部に向かって、半導体チップ内の配線を介して行われている。しかしながら、最近の半導体の微細化の進展、回路規模の増大等により、チップサイズの大型化、低電圧化が進んでいる。この結果、半導体チップ内配線のみによる電源供給では半導体チップ内において電圧ドロップが生じ、性能低下が発生する。
　そこで、半導体チップをフリップチップボンディングにてパッケージングし、パッケージの基板配線から半導体チップの中央部に電源供給する方法が用いられる。しかし、パッケージ基板はコストが高い。
　これに対処する方法の例として、特許文献１がある。特許文献１によると、例えば図７に示すように、半導体チップ２１の表面に格子状にパッド２２を設けると共に、ボンディングワイヤ２４によって、格子状のパッド２２と周縁部にある外部パッド２３を接続する。これにより、外部パッド２３に供給された電源の電圧を、ドロップを生じることなく、半導体チップ２１の中央付近に供給することができる。
特開２００５－８５８２９号公報
　しかしながら、特許文献１に示された半導体装置の場合、格子状に配置したパッド２２の大きさが外部パッド２３と同一である。この結果、格子状パッド２２を配置するためには、チップサイズを大きくする、半導体チップの配線層数を１層以上増やす等が要求される。つまり、格子状パッドを形成するために専用の層を用いると、配線層を増やすことが必要であり、既存の配線層を利用して格子状パッドを形成すると、チップサイズを大きくすることが必要である。これは、コスト上昇の原因となる。
　以上に鑑み、本開示の半導体装置及びその製造方法の目的は、半導体チップ内に対する電源電圧の供給を低コストに実現することである。
　前記の目的を達成するために、本開示の半導体装置は、半導体チップと、半導体チップの主面の周縁部上に形成された外部パッドと、主面上であって、外部パッドよりも内側に形成された複数の内部パッドと、主面上を覆い、外部パッド上及び複数の内部パッド上に開口を有する保護膜と、内部パッド同士を電気的に接続する第１の金属細線とを備え、複数の内部パッドは、外部パッドよりも小さい。
　以上のような半導体装置によると、内部パッドを外部パッドよりも小さくしている。このような小さな内部パッドは、半導体チップ内に設けられる配線層の一部を利用して形成することができる。従って、チップサイズの増大を抑制でき、且つ、配線層を追加する必要も生じない。また、内部パッド同士を金属細線によって接続することができる。これらの結果、半導体チップの内部（中央付近）に対し、電圧ドロップを生じることなく確実に電源供給が可能な半導体装置を低コストに実現できる。尚、本開示の構造においても、金属細線により接続された内部パッドのうちの一方と、外部パッドとは、半導体チップ内配線により接続されている。しかしながら、接続距離が短いので当該部分における電圧ドロップは問題にはならない。
　尚、複数の内部パッド上に各々設けられた複数の内部突起電極を更に備えていても良い。
　このようにすると、金属細線による内部パッド同士の電気的接続をより確実に行なうことができる。
　また、複数の内部突起電極の表面の曲率は、外部突起電極よりも大きくても良い。
　これにより、金属細線を用いて内部突起電極同士の接続を行なう際に、内部突起電極と金属細線との接合表面積が大きくなるので、より確実な接続を行なうことができる。
　また、複数の内部突起電極は、内部パッドよりも大きくても良い。
　このようにすると、内部パッドを小さくすることによりチップサイズの増大を抑えながら、金属細線による電気的接続をより確実に行なうことができる。
　また、第１の金属細線の両端に、それぞれ内部突起電極と接続される金属ボールを備え、金属ボールは、内部突起電極よりも大きくても良い。
　このようにすると、金属ボールによって内部突起電極を覆うようにして接続することができるので、第１の金属細線による接続をより確実に行なうことができる。
　また、金属ボールは、保護膜と接していても良い。
　このようにすると、金属ボールと保護膜との接合により第１の金属細線の接合強度が向上する。
　更に、保護膜は、複数の内部パッドの周囲に凹部を有し、金属ボールは、凹部内にまで形成されていても良い。
　このようにすると、金属ボールが凹部に合わせて変形して食い込むことにより、接合強度が更に向上する。
　また、少なくとも２つの内部突起電極を覆うように金属ボールが形成され、当該金属ボールによって、前記の少なくとも２つの内部突起電極の電気的接続が行なわれていても良い。
　このようにすると、金属ボールが内部突起電極同士を電気的に接続するジャンパー配線として機能する。よって、コストの高い半導体チップ内の配線層を増加させることなく多層配線を実現することができる。
　また、複数の内部パッドの少なくとも１つには、電源電位又はグランド電位が供給されていても良い。
　これにより、半導体チップ内に電源電位又はグランド電位を供給できる。
　また、半導体チップ内に、第１の金属細線により電気的に接続された複数の内部パッドの少なくとも一つと、外部パッドとを電気的に接続するチップ内配線を備えてもよい。
　このようにすると、外部パッド、チップ内配線、内部パッドのうちの一方、第１の金属細線、内部パッドのうちの他方、と順に介して、外部パッドに供給された電源の電圧を半導体チップの中央付近にまで供給することができる。
　また、半導体チップには、回路素子が形成されていても良い。
　また、半導体チップ内において、複数の内部パッドが形成されている層に、配線が形成されていても良い。
　このように、配線層を利用して内部パッドを形成すると、新たな層を設けることなく内部パッドを実現できる。
　また、半導体チップを搭載する配線基板を更に備え、半導体チップは、配線基板上に搭載されていても良い。
　また、半導体チップと配線基板とは第２の金属細線により電気的に接続されていても良い。
　また、第１の金属細線の最上部の高さは、前記第２の金属細線の最上部の高さよりも低くなっていても良い。
　また、内部突起電極は、Ｎｉ層及びその上に形成された貴金属層を少なくとも含んでいても良い。
　次に、本開示の半導体装置の製造方法は、半導体チップの主面の周縁部上に外部パッドを形成する工程（ａ）と、主面上であって、外部パッドよりも内側に複数の内部パッドを形成する工程（ｂ）と、主面上を覆い、外部パッド上及び複数の内部パッド上に開口を有する保護膜を形成する工程（ｃ）と、内部パッド同士を第１の金属細線により電気的に接続する工程（ｄ）とを備え、内部パッドは、外部パッドよりも小さい。
　このような半導体装置の製造方法によると、半導体チップの内部（中央付近）に対して確実に電源供給できると共に、内部パッドを設けることによるチップサイズの増大を抑制可能な半導体装置を製造できる。更に、内部パッドによる電源供給のために、配線層を追加する必要も無い。
　また、工程（ｃ）と工程（ｄ）との間に、複数の内部パッド上に各々内部突起電極を形成する工程（ｅ）を更に備え、工程（ｄ）において、内部突起電極同士を第１の金属細線により接続しても良い。
　このようにすると、第１の金属細線による内部パッド同士の電気的接続をより確実に行なうことができる。
　また、工程（ｅ）において、内部突起電極に加えて、外部パッド上に外部突起電極を形成し、内部突起電極及び外部突起電極は、無電解めっき法を用いて形成しても良い。
　このようにすると、外部突起電極を電気的接続に利用できる。また、内部突起電極と外部突起電極とを同じ工程において形成できる。
　また、工程（ｄ）は、ワイヤボンディング法により、複数の内部突起電極のうちの第１の内部突起電極上に第１の金属ボールを形成する工程と、ワイヤボンディング法により、複数の内部突起電極のうちの第２の内部突起電極上に第２の金属ボールを形成した後、第２の金属ボールから第１の金属ボールに向けて金属細線を形成する工程とを含んでいても良い。金属細線による接続の方法として、このようにしても良い。
　以上の通り、本開示の半導体装置及びその製造方法によると、半導体チップの配線層を使って形成する内部パッドを著しく小さくでき、内部パッド形成によるチップサイズの増大を抑制できる。また、従来は必要であった半導体チップにおける追加の配線層は不要となり、低コスト且つ高信頼性の半導体装置を実現できる。
図１は、本開示の第１の実施形態の例示的半導体装置に用いる半導体チップを示す平面図である。 図２（ａ）～（ｃ）は、第１の実施形態の例示的半導体装置に関し、製造工程を示す図である。 図３は、第１の実施形態の例示的半導体装置に関し、突起電極の周囲の保護膜に凹部を設けることについて示す図である。 図４は、第１の実施形態の例示的半導体装置に関し、ワイヤボンディングが完了した状態を示す平面図である。 図５は、本開示の第２の実施形態の例示的半導体装置に用いる半導体チップを示す平面図である。 図６は、第２の実施形態の例示的半導体装置を示す図である。 図７は、関連技術の半導体チップについて示す図である。
　本開示の各実施形態について、図面を参照しながら説明する。尚、各図は理解を容易にするために模式的に示したものであり、各部材の形状、寸法等については必ずしも正確ではない。
　　（第１の実施形態）
　第１の実施形態について説明する。図１は、本実施形態の例示的半導体装置２５（図２（ｃ）を参照）に用いられる半導体チップ４の平面図である。内部に素子等の形成された半導体チップ４の主面の周縁部上には、半導体チップ４における回路と外部とを電気的に接続するための外部パッド７が形成されている。また、主面における外部パッド７よりも内側に、半導体チップ４の内部に電気的な接続をするための第１の内部パッド８及び第２の内部パッド９が形成されている。外部パッド７、第１の内部パッド８及び第２の内部パッド９は、Ａｌ、Ｃｕ等を用いて形成される。
　第１の内部パッド８は、外部パッド７のうちの電源電位が供給されたパッド又はグランド電位が供給されたパッドに対して、半導体チップ４内に設けられた配線（チップ内配線）により電気的に接続されている。
　また、内部パッド８及び９（以下、第１の内部パッド８及び第２の内部パッド９をあわせてこのように呼ぶことがある）と、外部パッド７とは、半導体チップ４における配線層と同じ層に形成されている。また、図１にも示す通り、内部パッド８及び９は、外部パッド７よりも十分に小さい。このことから、内部パッド８及び９を形成することによるチップサイズの増大を抑えることができる。また、既存の配線層（例えば、第１の内部パッド８と外部パッド７とを電気的に接続するチップ内配線を含む配線層）を利用して内部パッド８及び９を設けることが可能であり、追加の配線層は不要である。従って、低コストで且つ信頼性の高い半導体装置を実現することができる。
　尚、各パッドのサイズ及び平面形状について、例えば、外部パッド７が一辺の長さが５０μｍ～１００μｍ程度の四角形状であるのに対し、第１の内部パッド８及び第２の内部パッド９は、一辺の長さが０．５μｍ～１５μｍの四角形状である。但し、このような値には限定されず、また、平面形状についても、他の多角形、円形、楕円形等であっても良い。
　次に、半導体チップ４内の素子と、半導体チップ４の外部との電気的接続について更に説明する。
　図２（ａ）～（ｃ）は、半導体チップ４をパッケージ基板（配線基板）１上に搭載して半導体装置２５を得るための工程を模式的に示す断面図である。
　図２（ａ）にも示すように、パッケージ基板１の一方の面が搭載面であり、当該面に、パッケージ電極２を備えると共に半導体チップ４が搭載される。パッケージ基板１における搭載面とは反対側の面に、パッケージ基板１の外部電極３が設けられている。
　半導体チップ４は、樹脂５を用いてパッケージ基板１に固定される。樹脂５としては、Ａｇペースト等の導電性樹脂を用いても良いし、エポキシ、ポリイミド等からなる絶縁性樹脂を用いても良い。
　半導体チップ４は、前述の通り、外部パッド７と、内部パッド８及び９とを上面に備える。更に、半導体チップ４上を覆うように、ガラス系又はポリイミド等の樹脂系の保護膜６が形成されている。保護膜６は、外部パッド７、内部パッド８及び９上に開口を有している。
　更に、内部パッド８及び９上には、例えば無電解めっきにより、内部突起電極１１及び１２がそれぞれ形成されている。更に、外部パッド７上には、同じく無電解めっき等により、外部突起電極１０が形成されている。これらの各突起電極１０～１２（外部突起電極１０、内部突起電極１１及び１２）は、例えばＮｉ、Ｃｕ等からなる層と、その上に形成されＡｕ、Ｐｄ等からなる層とを含む構造である。
　尚、無電解めっきによる各突起電極１０～１２の形成は、半導体チップ４が個片にされる前のウエハ段階にて行なう。つまり、無電解めっき液にウエハを浸漬することにより、保護膜６が開口された部分の外部パッド７、内部パッド８及び９上に、めっき液中のＮｉ等の金属を析出させて各突起電極１０～１２とする。
　また、各突起電極１０～１２は、少なくとも保護膜６の表面に達する厚さに形成されている。例えば、１μｍ～１０μｍ程度の厚さである。
　ここで、内部突起電極１１及び１２については、内部パッド８及び９上の保護膜６の開口サイズが小さいので、（特に、外部パッド７上の外部突起電極１０に比べると）曲率の大きな断面形状となる。つまり、外部パッド７の上面は（曲率が十分に小さいので）概ね平面になるのに対し、内部パッド８及び９は、より顕著に突起した（表面の曲率が大きい）形状となる。
　次に、図２（ａ）に示しているように、第１の内部パッド８上に設けられた内部突起電極１１上に、第１の金属ボール１５を接合する。このためには、ボールバンビング法、スタッドバンプ法等と呼ばれる方法を用いることができる。つまり、ワイヤボンディングの工程において、ボンディングワイヤの先端に形成した第１の金属ボール１５を内部突起電極１１上に接合し、その後、ボンディングワイヤを第１の金属ボール１５の上部にて切断する。このようにして、内部突起電極１１上に第１の金属ボール１５のみが残された状態とする方法である。
　ここで、第１の金属ボール１５は、例えばＡｕ、Ｃｕ、Ａｌ等からなる。大きさは、例えば直径が１５μｍ～１５０μｍ程度であり、用いるボンディングワイヤの径によって制御することができる。ボンディングワイヤの径は、例えば、１０μｍ～５０μｍ程度である。また、第１の金属ボール１５の接合は、加熱、加圧、超音波印加等によって行なう。例えば、加圧は５ｇｆ～１００ｇｆ（０．０４９Ｎ～０．９８Ｎ）程度、加熱温度は１００℃～３００℃程度である。
　第１の金属ボール１５がＡｕからなる場合、突起電極１１の表面金属であるＡｕ又はＰｄと金属接合する。このとき、第１の内部パッド８上の突起電極１１を覆うように、第１の金属ボール１５の大きさを設定しておく。また、第１の金属ボール１５は、半導体チップ４の保護膜６にも接していて構わない。
　次に、図２（ｂ）に示すように、第２の内部パッド９上に第２の金属ボール１４を形成すると共に、第２の金属ボール１４と第１の金属ボール１５とを接続するボンディングワイヤ１６を形成する。この際、ワイヤ超音波熱圧着方式を用いたワイヤボンディングを用いても良い。
　また、ボンディングの方法として、第２の内部パッド９上の内部突起電極１２に対して金属ボールによるボールボンディングを行ない、第１の内部パッド８上の金属ボール１５上に対してボンディングワイヤ１６の他端によるウェッジボンディングを行なうのが好ましい。このようにすると、金属ボールとしては、ワイヤーボンディング工程の金属ボールのみを用いることになる。この結果、同じワイヤボンダーによりいずれのボンディングも行なうことができ、コストを低減することができる。
　第２の内部パッド９上の内部突起電極１２に対する第２の金属ボール１４の接合については、第１の内部パッド８上の内部突起電極１１に対する第１の金属ボール１５の接合と同様に行なえばよい。
　以上により、ボンディングワイヤ１６を介して、第１の内部パッド８と、第２の内部パッド９とが電気的に接続される。また、第１の内部パッド８は外部パッド７と電気的に接続されている。従って、半導体チップ４の中央付近に設けられている電源系回路が、外部パッド７の電源系パッドと電気的に接続されたことになる。
　ここで、図３に示すように、内部突起電極１１及び１２の周囲において、保護膜６の表面に、凹凸（図３の例では凹部２１）を設けておいても良い。このようにすると、金属ボール１４及び１５（第１の金属ボール１５及び第２の金属ボール１４）は凹凸に従って変形し、食い込む形状となるので、アンカー効果により接合強度が向上する。
　更に、内部突起電極１１及び１２が大きな曲率の断面形状を有する場合、サイズが小さくても金属ボール１４及び１５に対する接合表面積が大きくなるので、接合強度が向上する。つまり、曲率の大きな形状（たとえば、尖った形状と考えてもよい）の突起電極が金属ボールに食い込んだ状態になるので（平坦なもの同士が接触している状態に比べて）接合が強くなる。
　また、半導体チップ４における金属ボール１４及び１５の下方の領域には、トランジスタ、配線等の回路素子を備えていても良い。内部電極が小さいので、内部電極と同一の層に配線も形成することができ、当該配線に接続するトランジスタも配置できる。
　尚、ボンディングワイヤ１６の径は、１０μｍ～５０μｍ程度であり、このボンディングワイヤ１６に通電する電流値に基づいて選択する。
　大電流を通電する場合、太いボンディングワイヤを用いると、金属ボールの径は一般に大きくなる。しかしながら、半導体チップの配線層を用いて金属ボールよりも大きなパッドを形成する背景技術の構造とは異なり、小さな内部パッド８及び９を用いるので、半導体チップ４のサイズを小さくすることができる。
　また、同じボンディングワイヤによって接続される箇所、つまり内部突起電極１１及び１２は同一の面に位置しているので、ボンディングワイヤ１６の最上部の高さを低くすることができる。具体的に、例えば第２の金属ボール１４の上面から２０μｍ～５０μｍ程度の高さにすることができ、ボンディングワイヤ１６を短くすることができる。尚、ボンディングワイヤ１７の高さは、例えば１００μｍ～３００μｍ程度である。
　次に、ボンディングワイヤ１７を用いたワイヤボンディングにより、半導体チップ４の外部パッド７上の外部突起電極１０と、パッケージ基板１のパッケージ電極２とを接続する。この際、外部突起電極１０上には第３の金属ボール１３が形成される。尚、本実施形態では内部パッド８及び９を電気的に接続した後に、外部パッド７とパッケージ電極２との電気的接続を行なっているが、この順序は逆にしても良い。
　図４には、パッケージ基板１に搭載された半導体チップ４について、ボンディングワイヤ１６及びボンディングワイヤ１７によるそれぞれのワイヤボンディングが完了した状態の平面図を示している。既に述べた通り、金属ボール１５下方には第１の内部パッド８があり、半導体チップ４内の配線により外部パッド７と電気的に接続されている（図示は省略する）。従って、金属ボール１４下方の第２の内部パッド９に接続された半導体チップ４内における回路素子等は、外部パッド７と電気的に接続されていることになる。
　この後、図２（ｃ）に示すように、半導体チップ４、ボンディングワイヤ１６及び１７を覆うように、封止樹脂１８を用いて成型する。封止樹脂１８は熱硬化性エポキシ樹脂等からなり、例えばトランスファーモールド方式等を利用する。以上により、半導体装置２５が製造される。
　　（第２の実施形態）
　次に、本開示の第２の実施形態について説明する。図５は、本実施形態の例示的半導体装置２５ａに用いられる半導体チップ４ａの平面図であり、図６は、パッケージ基板１への半導体チップ４ａの搭載、ボンディングワイヤによる電気的接続及び樹脂封止までを完了した半導体装置２５ａを示す断面図である。各図において、第１の実施形態における図と同じ構成要素については同じ符号を付しており、以下には主に相違点を説明する。
　半導体チップ４ａは、第１の実施形態の半導体チップ４（図１を参照）と同じ構成に加えて、第２の内部パッド９の近くに、第３の内部パッド１９を更に備える構造である。
　第１の内部パッド８は、外部パッド７のうち、電源のパッド又はグランドのパッドに対して半導体チップ４内の配線により電気的に接続されている。
　第２の内部パッド９は、半導体チップ４ａにおける第１の電源系回路と接続されており、また、第３の内部パッド１９は、半導体チップ４ａにおける第２の電源系回路と接続されている。第２の内部パッド９と、第３の内部パッド１９とは、直接には接しないように配置されている。
　また、第２の内部パッド９と第３の内部パッド１９との間に、半導体チップ４ａの配線が（第２の内部パッド９及び第３の内部パッド１９には接続されないように）形成されている（図示は省略）。
　各内部パッドの大きさ、材料等についても、第１の実施形態と同様であっても良い。
　図６に示すように、第１の内部パッド８上及び第２の内部パッド９上にそれぞれ内部突起電極１１及び１２が形成されていることに加えて、第３の内部パッド１９上には内部突起電極２０が形成されている。
　また、第２の金属ボール１４が、第２の内部パッド９上の内部突起電極１２に加えて、第３の内部パッド１９上の内部突起電極２０に対しても接合し、これらを共に覆うように形成されている。この結果、第２の内部パッド９と第３の内部パッド１９とは、第２の金属ボール１４を介して電気的に接続される。
　ここで、第２の内部パッド９と第３の内部パッド１９との間には半導体チップ４ａ内において配線が形成されているので、金属ボール１４によって配線を一部ジャンパーした構成となる。この結果、コストの高い半導体チップ４ａ内の多層配線層を用いること無しに、多層配線を実現することができ、コストを低減できる。
　本開示の半導体装置及びその製造方法によると、チップサイズの増大を抑制しながら高機能化及び低コスト化を実現することができ、例えばデジタルテレビ等の分野において用いる大規模なシステムＬＳＩ等にも有用である。
　１　　　パッケージ基板
　２　　　パッケージ電極
　３　　　外部電極（パッケージ基板の）
　４　　　半導体チップ
　４ａ　　半導体チップ
　５　　　樹脂
　６　　　保護膜
　７　　　外部パッド
　８　　　第１の内部パッド
　９　　　第２の内部パッド
１０　　　外部突起電極
１１　　　内部突起電極
１２　　　内部突起電極
１３　　　第３の金属ボール
１４　　　第２の金属ボール
１５　　　第１の金属ボール
１６　　　ボンディングワイヤ
１７　　　ボンディングワイヤ
１８　　　封止樹脂
１９　　　第３の内部パッド
２０　　　内部突起電極
２１　　　凹部
２５　　　半導体装置
２５ａ　　半導体装置

Claims (20)

  1. 　半導体チップと、
    　前記半導体チップの主面の周縁部上に形成された外部パッドと、
    　前記主面上であって、前記外部パッドよりも内側に形成された複数の内部パッドと、
    　前記主面上を覆い、前記外部パッド上及び前記複数の内部パッド上に開口を有する保護膜と、
    　前記内部パッド同士を電気的に接続する第１の金属細線とを備え、
    　前記複数の内部パッドは、前記外部パッドよりも小さいことを特徴とする半導体装置。
  2. 　請求項１の半導体装置において、
    　前記複数の内部パッド上に各々設けられた複数の内部突起電極を更に備えることを特徴とする半導体装置。
  3. 　請求項２の半導体装置において、
    　前記複数の内部突起電極の表面の曲率は、前記外部突起電極よりも大きいことを特徴とする半導体装置。
  4. 　請求項２の半導体装置において、
    　前記複数の内部突起電極は、前記内部パッドよりも大きいことを特徴とする半導体装置。
  5. 　請求項１の半導体装置において、
    　前記第１の金属細線の両端に、それぞれ前記内部突起電極と接続される金属ボールを備え、
    　前記金属ボールは、前記内部突起電極よりも大きいことを特徴とする半導体装置。
  6. 　請求項５の半導体装置において、
    　前記金属ボールは、前記保護膜と接していることを特徴とする半導体装置。
  7. 　請求項６の半導体装置において、
    　前記保護膜は、前記複数の内部パッドの周囲に凹部を有し、
    　前記金属ボールは、前記凹部内にまで形成されていることを特徴とする半導体装置。
  8. 　請求項５の半導体装置において、
    　少なくとも２つの前記内部突起電極を覆うように前記金属ボールが形成され、当該金属ボールによって、前記少なくとも２つの前記内部突起電極の電気的接続が行なわれていることを特徴とする半導体装置。
  9. 　請求項１～８のいずれか１つの半導体装置において、
    　前記複数の内部パッドの少なくとも１つには、電源電位又はグランド電位が供給されていることを特徴とする半導体装置。
  10. 　請求項１の半導体装置において、
    　前記半導体チップ内に、前記第１の金属細線により電気的に接続された前記複数の内部パッドの少なくとも一つと、前記外部パッドとを電気的に接続するチップ内配線を備えることを特徴とする半導体装置。
  11. 　請求項１の半導体装置において、
    　前記半導体チップには、回路素子が形成されていることを特徴とする半導体装置。
  12. 　請求項１の半導体装置において、
    　前記半導体チップ内において、前記複数の内部パッドが形成されている層に、配線が形成されていることを特徴とする半導体装置。
  13. 　請求項１の半導体装置において、
    　前記半導体チップを搭載する配線基板を更に備え、
    　前記半導体チップは、前記配線基板上に搭載されていることを特徴とする半導体装置。
  14. 　請求項１３の半導体装置において、
    　前記半導体チップと前記配線基板とは第２の金属細線により電気的に接続されていることを特徴とする半導体装置。
  15. 　請求項１４の半導体装置において、
    　前記第１の金属細線の最上部の高さは、前記第２の金属細線の最上部の高さよりも低いことを特徴とする半導体装置。
  16. 　請求項２の半導体装置において、
    　前記内部突起電極は、Ｎｉ層及びその上に形成された貴金属層を少なくとも含むことを特徴とする半導体装置。
  17. 　半導体チップの主面の周縁部上に外部パッドを形成する工程（ａ）と、
    　前記主面上であって、前記外部パッドよりも内側に複数の内部パッドを形成する工程（ｂ）と、
    　前記主面上を覆い、前記外部パッド上及び前記複数の内部パッド上に開口を有する保護膜を形成する工程（ｃ）と、
    　前記内部パッド同士を第１の金属細線により電気的に接続する工程（ｄ）とを備え、
    　前記内部パッドは、前記外部パッドよりも小さいことを特徴とする半導体装置の製造方法。
  18. 　請求項１７の半導体装置の製造方法において、
    　前記工程（ｃ）と前記工程（ｄ）との間に、前記複数の内部パッド上に各々内部突起電極を形成する工程（ｅ）を更に備え、
    　前記工程（ｄ）において、前記内部突起電極同士を前記第１の金属細線により接続することを特徴とする半導体装置の製造方法。
  19. 　請求項１８の半導体装置の製造方法において、
    　前記工程（ｅ）において、前記内部突起電極に加えて、前記外部パッド上に外部突起電極を形成し、
    　前記内部突起電極及び前記外部突起電極は、無電解めっき法を用いて形成することを特徴とする半導体装置の製造方法。
  20. 　請求項１７の半導体装置の製造方法において、
    　前記工程（ｄ）は、
    　ワイヤボンディング法により、前記複数の内部突起電極のうちの第１の内部突起電極上に第１の金属ボールを形成する工程と、
    　ワイヤボンディング法により、前記複数の内部突起電極のうちの第２の内部突起電極上に第２の金属ボールを形成した後、前記第２の金属ボールから前記第１の金属ボールに向けて前記金属細線を形成する工程とを含むことを特徴とする半導体装置の製造方法。
PCT/JP2011/003055 2010-08-18 2011-05-31 半導体装置及びその製造方法 WO2012023228A1 (ja)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653413A (ja) * 1992-07-29 1994-02-25 Nec Corp 半導体集積回路
JP2005085829A (ja) * 2003-09-05 2005-03-31 Renesas Technology Corp 半導体装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0653413A (ja) * 1992-07-29 1994-02-25 Nec Corp 半導体集積回路
JP2005085829A (ja) * 2003-09-05 2005-03-31 Renesas Technology Corp 半導体装置

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