WO2012000301A1 - 一种半导体器件及其形成方法 - Google Patents

一种半导体器件及其形成方法 Download PDF

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Publication number
WO2012000301A1
WO2012000301A1 PCT/CN2011/000337 CN2011000337W WO2012000301A1 WO 2012000301 A1 WO2012000301 A1 WO 2012000301A1 CN 2011000337 W CN2011000337 W CN 2011000337W WO 2012000301 A1 WO2012000301 A1 WO 2012000301A1
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Prior art keywords
gate
dielectric layer
layer
compressive stress
forming
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English (en)
French (fr)
Inventor
朱慧珑
梁擎擎
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/119,577 priority Critical patent/US20120217592A1/en
Publication of WO2012000301A1 publication Critical patent/WO2012000301A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/671—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor having lateral variation in doping or structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/015—Manufacture or treatment removing at least parts of gate spacers, e.g. disposable spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0177—Manufacturing their gate conductors the gate conductors having different materials or different implants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0181—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method of forming the same. Background technique
  • the step of forming a gate electrode includes: First, as shown in FIG. 1, a dummy gate stacked structure including a gate dielectric layer 12, a dummy gate 14 and a sidewall spacer 16 is formed.
  • the gate dielectric layer 12 is formed on the semiconductor substrate 10 (the P ⁇ region 1802, the N well region 1804, the source and drain regions 20, the isolation region 22, and the contact region 24 have been formed on the semiconductor substrate 10, the isolation region 22 is used to isolate the NMOS device region 1 1 and the PMOS device region 13 ), the dummy gate 14 is formed on the gate dielectric layer 12 , and the sidewall spacer 16 surrounds the dummy gate 14 and covers the gate dielectric layer 12 .
  • the side wall 16 may also surround the dummy gate 14 and the gate dielectric layer 12, not shown);
  • a barrier layer 26 and an interlayer dielectric layer 28 are formed.
  • the barrier layer 26 is formed on the semiconductor substrate 10 and covers the dummy gate stacked structure, and the barrier layer 26 material and the sidewall spacer 16 is the same material, the interlayer dielectric layer 28 covers the barrier layer 24; as shown in FIG. 3, the barrier layer 26 and the interlayer dielectric layer 28 are planarized to expose the dummy gate 14, a side wall 16 and the barrier layer 26;
  • the dummy gate 14 is replaced by a gate electrode including a new gate dielectric layer 30, a work function metal layer 32, and a main metal layer 34.
  • the main metal layer 34 material is TiAl, and the TiAl has compressive stress. It has been found in practice that the compressive stress will generate tensile stress on the channel regions of the NMOS device and the PMOS device, and applying tensile stress to the channel region of the PMOS device tends to cause deterioration in device performance. Summary of the invention
  • the present invention provides a semiconductor device and a method of forming the same, which are advantageous for improving device performance.
  • the present invention provides a method of forming a semiconductor device, the semiconductor device includes a PMOS device, and the step of forming the PMOS device includes: Forming a gate stack structure, the gate stack structure including a gate dielectric layer, a gate and a sidewall, the gate dielectric layer being formed on the semiconductor substrate, the gate being formed on the gate dielectric layer, the sidewall surrounding The gate and the gate dielectric layer or surround the gate and cover the gate dielectric layer;
  • the cavity is filled with an auxiliary layer having a first compressive stress.
  • the auxiliary layer material is silicon nitride.
  • the step of forming the gate stack structure comprises:
  • a dummy gate stack structure including a gate dielectric layer, a dummy gate and a sidewall spacer, the gate dielectric layer being formed on the semiconductor substrate, the dummy gate being formed on the gate dielectric layer of the gate dielectric cover ;
  • barrier layer Forming a barrier layer and an interlayer dielectric layer, the barrier layer being formed on the semiconductor substrate and covering the dummy gate stack structure, the interlayer dielectric layer covering the barrier layer;
  • the dummy gate is replaced with a gate material having a second compressive stress, and the second compressive stress and the first compressive stress generate compressive stress to a channel region formed in the PMOS device.
  • the gate material is TiAl.
  • the barrier layer material is the same as the sidewall material, and the exposed barrier layer is also removed when the sidewall spacer is removed.
  • the present invention provides a method of forming a semiconductor device, the semiconductor device comprising a PMOS device, and the step of forming the PMOS device comprises:
  • the gate stack structure including a gate dielectric layer, a gate and a sidewall, the gate dielectric layer being formed on the semiconductor substrate, the gate being formed on the gate dielectric layer, and the gate material Having a second compressive stress, the sidewall surrounding the gate and the gate dielectric layer or surrounding the gate and covering the gate dielectric layer;
  • the cavity is filled with an auxiliary layer.
  • the auxiliary layer has a first compressive stress, and the first compressive stress and the second compressive stress generate compressive stress on a channel region formed in the PMOS device.
  • the auxiliary layer material is silicon nitride.
  • the step of forming the gate stack structure comprises:
  • a dummy gate stack structure including a gate dielectric layer, a dummy gate and a sidewall spacer, the gate dielectric layer being formed on the semiconductor substrate, the dummy gate being formed on the gate dielectric layer of the gate dielectric cover ;
  • barrier layer Forming a barrier layer and an interlayer dielectric layer, the barrier layer being formed on the semiconductor substrate and covering the dummy gate stack structure, the interlayer dielectric layer covering the barrier layer;
  • the dummy gate is replaced with a gate material.
  • the gate material is TiAl.
  • the barrier layer material is the same as the sidewall material, and the exposed barrier layer is also removed when the sidewall spacer is removed.
  • the invention provides a semiconductor device, the semiconductor device comprises a PMOS device, and the PMOS device comprises:
  • the gate dielectric layer being formed on the semiconductor substrate
  • the gate is formed on the gate dielectric layer
  • An auxiliary layer, the auxiliary layer is formed on the semiconductor substrate, the auxiliary layer surrounds the gate and the gate dielectric layer or surrounds the gate and covers the gate dielectric layer;
  • a compressive stress, or the auxiliary layer has a first compressive stress and the gate has a second compressive stress to generate a compressive stress on a channel region formed in the PMOS device.
  • the auxiliary layer material is silicon nitride.
  • the gate material is TiAl.
  • the technical solution provided by the present invention has the following advantages:
  • the main metal layer When forming a gate, considering the influence of process maturity, the main metal layer usually has compressive stress (and thus the gate has compressive stress)
  • the compressive stress will generate tensile stress on the channel region of the device through the sidewall spacer, and for the PMOS device, tensile stress is generated in the channel region of the device, which may easily deteriorate the device performance; and the PMOS device is removed.
  • the compressive stress of the gate in the PMOS device can be released, thereby reducing the tensile stress experienced by the channel region in the PMOS device, which is advantageous for improving device properties
  • a cavity is formed, an auxiliary layer is filled in the cavity, and the auxiliary layer is subjected to compressive stress, and the compressive stress is conducted to the channel region, and Producing compressive stress to the channel region facilitates further improvement of device performance; by making the auxiliary layer material the same as the sidewall material, the technical solution provided by the present invention is compatible with the prior art.
  • FIG. 1 is a schematic structural view of a prior art forming a dummy gate stack structure
  • FIG. 2 is a schematic structural view of the prior art in which an interlayer dielectric layer is formed
  • FIG. 3 is a schematic diagram of performing planarization in the prior art. Schematic diagram of the structure after operation
  • FIG. 4 is a schematic structural view of the prior art after forming a gate
  • FIG. 5 is a schematic structural view of a semiconductor substrate in an embodiment of a method of forming a semiconductor device according to the present invention.
  • FIG. 6 is a schematic structural view showing a sacrificial layer formed in an embodiment of a method for forming a semiconductor device according to the present invention
  • FIG. 7 is a schematic structural view showing a pseudo gate formed in an embodiment of a method for forming a semiconductor device according to the present invention.
  • FIG. 8 is a schematic structural view showing a side wall formed in an embodiment of a method for forming a semiconductor device according to the present invention.
  • FIG. 9 is a schematic structural view showing the formation of an interlayer dielectric layer in an embodiment of a method for forming a semiconductor device according to the present invention.
  • FIG. 10 is a schematic structural view showing a method of forming a semiconductor device according to an embodiment of the present invention.
  • FIG. 11 is a schematic structural view showing a gate electrode formed in an embodiment of a method for forming a semiconductor device according to the present invention.
  • FIG. 12 is a schematic structural view of the embodiment of the method for forming a semiconductor device according to the present invention after removing the sidewall;
  • FIG. 13 is a schematic structural view of the embodiment of the method for forming a semiconductor device according to the present invention after the auxiliary layer is filled.
  • the present invention may repeat reference numerals and/or letters in different embodiments. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides a method of forming a semiconductor device, including:
  • a wafer is pre-cleaned, and an isolation region 102 (such as STI) and a well region are formed in the wafer to form a semiconductor substrate 100 (the semiconductor substrate 100 includes an NMOS device region 101 and a PMOS device region 103, an NMOS device is formed on the NMOS device region 101, and a PMOS device is formed on the PMOS device region 103; in the NMOS device region 101, the well region 1042 is a p-well at the PMOS The well region 1044 in the device region 103 is an n-well).
  • the semiconductor substrate 100 includes an NMOS device region 101 and a PMOS device region 103, an NMOS device is formed on the NMOS device region 101, and a PMOS device is formed on the PMOS device region 103; in the NMOS device region 101, the well region 1042 is a p-well at the PMOS
  • the well region 1044 in the device region 103 is an n-well).
  • the wafer may comprise a silicon wafer (this embodiment) or other compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide; further, the wafer preferably comprises an epitaxial layer; the wafer may also comprise Silicon-on-insulator (SOI) structure.
  • silicon wafer this embodiment
  • other compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide
  • the wafer preferably comprises an epitaxial layer
  • the wafer may also comprise Silicon-on-insulator (SOI) structure.
  • SOI Silicon-on-insulator
  • the gate dielectric layer 120 and the sacrificial layer 140 are sequentially formed on the semiconductor substrate 100.
  • the gate dielectric layer 120 may be selected from a germanium-based material such as one of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO or HfZrO or a combination thereof.
  • the sacrificial layer 140 may be polysilicon or amorphous silicon, preferably polysilicon.
  • the sacrificial layer 140 is patterned to form a dummy gate 142.
  • the dummy gate 142 may be formed by a photolithography or etching process.
  • a sidewall spacer 144 surrounding the dummy gate 142 and covering the gate dielectric layer 120 is formed, and the exposed gate dielectric layer 120 is removed to expose the sheep conductor substrate 100.
  • the sidewall 144 may include one of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or a combination thereof, and the sidewall 144 may further have a multi-layer structure; in this embodiment, the sidewall spacer 144 is preferably silicon nitride (in this case, an interface layer is further formed between the sidewall spacer 144 and the dummy gate 142, and the interface layer is preferably an oxide layer, not shown).
  • the spacer 144 may be formed using an inverse engraving process.
  • the exposed gate dielectric layer 120 may also be removed after the dummy gate 142 is formed, before the sidewall spacers 144 are formed; at this time, the sidewall spacers 144 surround the dummy gates 142 and the The gate dielectric layer 120 (in this document, the dummy gate 142, the sidewall spacer 144, and the gate dielectric layer 120 carrying the dummy gate 142 or the dummy gate 142 and the sidewall 144 are simultaneously referred to It is a dummy gate stack structure) to help reduce the parasitic capacitance of the device.
  • the source and drain regions 106 are formed in the semiconductor substrate 100 by using the dummy gate 142 and the sidewall spacers 144 as a mask, and the source/drain regions 106 may be formed by an ion implantation process or an epitaxial process, which will not be described again.
  • a metal layer is formed, the metal layer covers the dummy gate stack structure and the semiconductor substrate 100, and a heat treatment operation (such as RTA) is performed on the semiconductor substrate 100 carrying the metal layer to A contact region 108 is formed on the gate 142 and the exposed semiconductor substrate 100.
  • the metal layer material may be NiPt, Ni, Co or Ti, etc., preferably NiPt, and the heat treatment operation may have a temperature of 300. ⁇ 500. , such as 350. 400. Or 450°; Subsequently, the unreacted metal layer is removed.
  • a barrier layer 160 and an interlayer dielectric layer 162 are formed on the semiconductor substrate subjected to the above operation, and the barrier layer 160 and the interlayer dielectric layer 162 cover the dummy gate stacked structure.
  • the barrier layer 160 serves to block dopant ions in the interlayer dielectric layer 162 from entering the semiconductor substrate 100.
  • the barrier layer 1.60 material may be silicon nitride. In other embodiments, the barrier layer 160 may also be made of other materials.
  • the interlayer dielectric layer 162 material may be undoped or doped silica glass (such as fluorosilicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, silicon oxycarbide or silicon oxycarbonitride) or One or a combination of low dielectric constant dielectric materials (eg, black diamond, coral, etc.).
  • silica glass such as fluorosilicate glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, silicon oxycarbide or silicon oxycarbonitride
  • low dielectric constant dielectric materials eg, black diamond, coral, etc.
  • the barrier layer 160 and the interlayer dielectric layer 162 are planarized to expose the dummy gate 142, the sidewall spacers 144, and the barrier layer 160.
  • the planarization operation can be performed using a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • the NMOS device region is covered with a mask 180 (such as a silicon oxide layer), and the dummy gate 142 is replaced with a gate material in the PMOS device region; specifically: removing the dummy gate 142, to form a groove; and filling the groove with the gate material.
  • the gate material filling the recess can be reversed in part.
  • the gate material includes a stacked work function metal layer 146 (the work function metal layer
  • the work function metal layer 146 is a P-type material
  • the work function metal layer 146 provides a difference between a work function and a valence band of Si of less than 0.2 eV
  • the work function metal layer 146 material may include MoNx, a combination of any one or more of TiSiN, TiCN, TaAlC, TiAlN>TaN, PtSix, Ni 3 Si, Pt, Ru, Ir, Mo, HfRu, RuOx) and a main metal layer 148, the main metal layer 148
  • One or a combination of Al, Ti, TiAl, Ta, W or Cu may be included, preferably TiAl.
  • the gate dielectric layer 120 exposed by the recess may be removed to form a new gate dielectric layer 150, and the new gate dielectric layer 150 covers the recess. The bottom and side walls of the trough.
  • the PMOS device region is covered with a mask (such as a silicon oxide layer) to form a gate in the NMOS device region, and the gate located in the NMOS device region and the gate in the PMOS device region are different in:
  • the work function metal layer is an N-type material, and the work function metal layer provides a work function different from a conduction band of Si of less than 0.2 eV, and the work function metal layer Materials may include TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax or NiTax.
  • the NMOS device region is covered with a mask 180 (such as a silicon oxide layer), and exposed.
  • a mask 180 such as a silicon oxide layer
  • the sidewall spacers 144 are removed to form a cavity 182.
  • the exposed barrier layer 160 (not covered by the interlayer dielectric layer 162) is removed when the sidewall spacer 144 is removed. It will also be removed.
  • the material of the barrier layer 160 may be different from the material of the sidewall spacer 144.
  • the removal operation can be performed by dry etching or wet etching.
  • the main metal layer usually has compressive stress (and thus the gate has compressive stress), and the compressive stress will pass through the sidewall spacer to the channel region of the device.
  • the tensile stress is generated, and for the PMOS device, tensile stress is generated in the channel region of the device, which is likely to cause deterioration of device performance; and removing the sidewall spacer in the PMOS device is equivalent to cutting off conduction to the channel region.
  • the compressive stress acts to generate the tensile stress, that is, the compressive stress of the gate in the PMOS device can be released, thereby reducing the tensile stress experienced by the channel region in the PMOS device, which is beneficial to Improve device performance.
  • the cavity 182 is filled with the auxiliary layer 184.
  • the auxiliary layer 184 may have a compressive stress.
  • the auxiliary layer 184 material may be silicon nitride.
  • the auxiliary layer 184 is filled in 182, and the auxiliary layer 184 is subjected to compressive stress, which will be conducted to the channel region, and compressive stress is generated in the channel region, thereby further improving device performance;
  • the material of the auxiliary layer 184 is the same as the material of the side wall 144, which is beneficial to the technical solutions provided by the present invention and compatible with the prior art.
  • the compressive stress remaining in the gate may be formed by the process control so that the residual compressive stress and the compressive stress pair of the auxiliary layer 184 are formed.
  • the channel region within the PMOS device produces compressive stress. It should be emphasized that, at this time, even if the auxiliary layer 184 does not exhibit its stress, the gate exhibits a compressive stress, although tensile stress will be generated in the channel region of the pmos device due to the compressive stress provided by the gate. However, after removing the sidewall spacers to release all or part of the compressive stress, the tensile stress will still be reduced, which is beneficial to improve device performance.
  • auxiliary layer 184 having compressive stress may be formed separately by using various conventional processes described below, or may be directly used to form an underlying interlayer dielectric layer (ILD, in practice, mostly doped or undoped.
  • ILD interlayer dielectric layer
  • the etch stop layer formed in the past in practice, mostly silicon nitride, except that the etch stop layer also has compressive stress.
  • the gate dielectric layer 120, the sacrificial layer may be formed by pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other suitable process.
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • 140. The barrier layer 160, the interlayer dielectric layer 162, and the auxiliary layer 184.
  • the present invention also provides a semiconductor device including the semiconductor device
  • a PMOS device comprising:
  • the gate dielectric layer being formed on the semiconductor substrate
  • the gate is formed on the gate dielectric layer
  • the semiconductor substrate is obtained by forming a well region and an isolation region in the wafer.
  • the wafer may comprise a silicon wafer (this embodiment) or other compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide; further, the wafer preferably comprises an epitaxial layer; the wafer may also comprise Silicon-on-insulator (SOI) structure.
  • the gate dielectric layer may be selected from a ruthenium-based material such as one of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO or HfZrO or a combination thereof.
  • the gate includes a stacked work function metal layer (for a PMOS device, the work function metal layer is a P-type material, and a difference between a work function provided by the work function metal layer and a valence band of Si is less than 0.2 eV
  • the work function metal layer material may include a combination of any one or more of MoNx, TiSiN, TiCN, TaAlC TiAlN, TaN, PtSix, Ni 3 Si, Pt, Ru, Ir, Mo, HfRu RuOx) and a main
  • the metal layer, the main metal layer may comprise one or a combination of Al, Ti, TiAK Ta, W or Cu, preferably TiAl.
  • the auxiliary layer material may be silicon nitride.
  • each part in each embodiment of the semiconductor device may be the same as those described in the foregoing method for forming a semiconductor device, and are not described herein.

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Description

一种半导体器件及其形成方法 技术领域
本发明涉及半导体技术领域， 具体来说， 涉及一种半导体器件及 其形成方法。 背景技术
通常， 在半导体器件的形成方法中， 形成栅极的步骤包括： 首先， 如图 1所示， 形成伪栅堆叠结构， 所述伪栅堆叠结构包括栅介质层 12、 伪栅 14和侧墙 16, 所述栅介质层 12形成于半导体基底 10上（所述半 导体基底 10上已形成有 P ^区 1802、 N阱区 1804、 源漏区 20、 隔离 区 22和接触区 24,所述隔离区 22用以隔离 NMOS器件区 1 1和 PMOS 器件区 13 ) ， 所述伪栅 14形成于所述栅介质层 12上， 所述侧墙 16环 绕所述伪栅 14且覆盖所述栅介质层 12 (所述侧墙 16也可环绕所述伪 栅 14及所述栅介质层 12, 图未示） ；
如图 2所示， 形成阻挡层 26及层间介质层 28 , 所述阻挡层 26形 成于所述半导体基底 10 上且覆盖所述伪栅堆叠结构， 所述阻挡层 26 材料与所述侧墙 16材料相同，所述层间介质层 28覆盖所述阻挡层 24; 如图 3所示， 平坦化所述阻挡层 26及所述层间介质层 28 , 以暴露 所述伪栅 14、 所述侧墙 16和所述阻挡层 26;
如图 4所示， 以栅极（包括新栅介质层 30、 功函数金属层 32和主 金属层 34 ) 替代所述伪栅 14。
通常， 对于 NMOS器件和 PMOS器件， 所述主金属层 34材料均 采用 TiAl， 且所述 TiAl具有压应力。 实践发现， 所述压应力将对所述 NMOS器件和 PMOS器件的沟道区产生拉应力， 而对所述 PMOS器件 的沟道区施加拉应力易于导致器件性能的恶化。 发明内容
为了解决上述问题， 本发明提供了一种半导体器件及其形成方法， 利于改善器件性能。
本发明提供的一种半导体器件的形成方法， 所述半导体器件包括 PMOS器件， 形成所述 PMOS器件的步骤包括： 形成栅堆叠结构， 所述栅堆叠结构包括栅介质层、 栅极和侧墙， 所述栅介质层形成于半导体基底上， 所述栅极形成于所述栅介质层上， 所述侧墙环绕所述栅极及所述栅介质层或者环绕所述栅极且覆盖所述 栅介质层；
去除所述侧墙， 以形成空腔；
以辅助层填充所述空腔， 所述辅助层具有第一压应力。
可选地， 所述辅助层材料为氮化硅。
可选地， 形成所述栅堆叠结构的步骤包括：
形成伪栅堆叠结构， 所述伪栅堆叠结构包括栅介质层、 伪栅和侧 墙， 所述栅介质层形成于半导体基底上， 所述伪栅形成于所述栅介质 盖所述栅介质层；
形成阻挡层及层间介质层， 所述阻挡层形成于所述半导体基底上 且覆盖所述伪栅堆叠结构， 所述层间介质层覆盖所述阻挡层；
平坦化所述阻挡层及所述层间介质层， 以暴露所述伪栅、 所述侧 墙和所述阻挡层；
以栅极材料替代所述伪栅， 所述栅极材料具有第二压应力， 所述 第二压应力及所述第一压应力对形成于所述 PMOS器件内的沟道区产 生压应力。
可选地， 所述栅极材料为 TiAl。
可选地， 所述阻挡层材料与所述侧墙材料相同， 在去除所述侧墙 时， 也去除暴露的所述阻挡层。
本发明提供的一种半导体器件的形成方法， 所述半导体器件包括 PMOS器件， 形成所述 PMOS器件的步骤包括：
形成栅堆叠结构， 所述栅堆叠结构包括栅介质层、 栅极和侧墙， 所述栅介质层形成于半导体基底上， 所述栅极形成于所述栅介质层上 且所述栅极材料具有第二压应力， 所述侧墙环绕所述栅极及所述栅介 质层或者环绕所述栅极且覆盖所述栅介质层；
去除所述侧墙， 以形成空腔；
以辅助层填充所述空腔。
可选地， 所述辅助层具有第一压应力， 所述第一压应力及所述第 二压应力对形成于所述 PMOS器件内的沟道区产生压应力。 可选地， 所述辅助层材料为氮化硅。
可选地， 形成所述栅堆叠结构的步骤包括：
形成伪栅堆叠结构， 所述伪栅堆叠结构包括栅介质层、 伪栅和侧 墙， 所述栅介质层形成于半导体基底上， 所述伪栅形成于所述栅介质 盖所述栅介质层；
形成阻挡层及层间介质层， 所述阻挡层形成于所述半导体基底上 且覆盖所述伪栅堆叠结构， 所述层间介质层覆盖所述阻挡层；
平坦化所述阻挡层及所述层间介质层， 以暴露所述伪栅、 所述侧 墙和所述阻挡层；
以栅极材料替代所述伪栅。
可选地， 所述栅极材料为 TiAl。
可选地， 所述阻挡层材料与所述侧墙材料相同， 在去除所述侧墙 时， 也去除暴露的所述阻挡层。
本发明提供的一种半导体器件， 所述半导体器件包括 PMOS器件， 所述 PMOS器件包括：
栅介质层， 所述栅介质层形成于半导体基底上；
栅极， 所述栅极形成于所述栅介质层上；
辅助层， 所述辅助层形成于所述半导体基底上， 所述辅助层环绕 所述栅极及所述栅介质层或者环绕所述栅极且覆盖所述栅介质层； 所 述辅助层具有第一压应力、 或所述辅助层具有第一压应力且所述栅极 具有第二压应力， 以对形成于所述 PMOS器件内的沟道区产生压应力。
可选地， 所述辅助层材料为氮化硅。
可选地， 所述栅极材料为 TiAl。
与现有技术相比， 采用本发明提供的技术方案具有如下优点： 在形成栅极时， 考虑工艺成熟度的影响， 其中的主金属层通常具 有压应力 （进而使所述栅极具有压应力） ， 所述压应力将经所述侧墙 对器件的沟道区产生拉应力， 而对于 PMOS器件而言， 在器件的沟道 区产生拉应力， 易导致器件性能的恶化； 而去除 PMOS 器件中的所述 的途径， 即， 可释放 PMOS器件中所述栅极具有的所述压应力， 进而 减少 PMOS器件内所述沟道区所承受的所述拉应力， 利于改善器件性 去除 PMOS器件中的所述侧墙后， 将形成空腔， 在所述空腔中填 充辅助层， 且使所述辅助层具有压应力， 所述压应力将传导至所述沟 道区， 并对所述沟道区产生压应力， 利于进一步改善器件性能； 通过 使所述辅助层材料与所述侧墙材料相同， 利于本发明提供的技术方案 与现有工艺的兼容。 附图说明
图 1所示为现有技术中形成伪栅堆叠结构后的结构示意图； 图 2所示为现有技术中形成层间介质层后的结构示意图； 图 3所示为现有技术中执行平坦化操作后的结构示意图； 图 4所示为现有技术中形成栅极后的结构示意图；
图 5 所示为本发明提供的半导体器件的形成方法实施例中半导体 基底的结构示意图；
图 6 所示为本发明提供的半导体器件的形成方法实施例中形成牺 牲层后的结构示意图；
图 7 所示为本发明提供的半导体器件的形成方法实施例中形成伪 栅后的结构示意图；
图 8 所示为本发明提供的半导体器件的形成方法实施例中形成侧 墙后的结构示意图；
图 9 所示为本发明提供的半导体器件的形成方法实施例中形成层 间介质层后的结构示意图；
图 10所示为本发明提供的半导体器件的形成方法实施例中执行平 坦化操作后的结构示意图；
图 1 1所示为本发明提供的半导体器件的形成方法实施例中形成栅 极后的结构示意图；
图 12所示为本发明提供的半导体器件的形成方法实施例中去除侧 墙后的结构示意图；
图 13所示为本发明提供的半导体器件的形成方法实施例中填充辅 助层后的结构示意图。 具体实施方式 下文的公开提供了许多不同的实施例或例子用来实现本发明提供 的技术方案。 虽然下文中对特定例子的部件和设置进行了描述， 但是， 它们仅仅为示例， 并且目的不在于限制本发明。
此外， 本发明可以在不同实施例中重复参考数字和 /或字母。 这种 重复是为了简化和清楚的目的， 其本身不指示所讨论的各种实施例和 / 或设置之间的关系。
本发明提供了各种特定工艺和 /或材料的例子， 但是， 本领域普通 技术人员可以意识到的其他工艺和 /或其他材料的替代应用， 显然未脱 离本发明要求保护的范围。 需强调的是， 本文件内所述的各种区域的 边界包含由于工艺或制程的需要所作的必要的延展。
本发明提供了一种半导体器件的形成方法， 包括：
首先， 如图 5所示， 预清洗晶片 （wafer ) , 并在所述晶片内形成 隔离区 102 (如 STI ) 及阱区， 以形成半导体基底 100 (所述半导体基 底 100包含 NMOS器件区 101和 PMOS器件区 103 ,在所述 NMOS器 件区 101上形成 NMOS器件， 在所述 PMOS器件区 103上形成 PMOS 器件；在所述 NMOS器件区 101中所述阱区 1042为 p阱，在所述 PMOS 器件区 103中所述阱区 1044为 n阱） 。 所述晶片可以包括硅片 （本实 施例） 或其他化合物半导体， 如碳化硅、 砷化镓、 砷化铟或磷化铟； 此外， 所述晶片优选地包括外延层； 所述晶片也可以包括绝缘体上硅 ( SOI ) 结构。
随后， 如图 6所示， 在所述半导体基底 100上顺次形成栅介质层 120和牺牲层 140。 所述栅介质层 120可以选用铪基材料， 如 Hf02、 HfSiO、 HfSiON, HfTaO、 HfTiO或 HfZrO中的一种或其组合。 所述牺 牲层 140可以为多晶硅或非晶硅， 优选为多晶硅。
再后， 如图 7所示， 图形化所述牺牲层 140, 以形成伪栅 142。 可 采用光刻、 刻蚀工艺形成所述伪栅 142。 然后， 如图 8所示， 形成环绕 所述伪栅 142并覆盖所述栅介质层 120的侧墙 144，并去除暴露的所述 栅介质层 120， 以暴露所述羊导体基底 100。 所述侧墙 144可以包括氮 化硅、 氧化硅、 氮氧化硅、 碳化硅中的一种或其组合， 所述侧墙 144 还可以具有多层结构； 在本实施例中， 所述侧墙 144优选为氮化硅（此 时， 所述侧墙 144和所述伪栅 142之间还形成有交界层， 所述交界层 优选为氧化层， 图未示）。 可采用反刻工艺形成所述侧墙 144。 在其他 实施例中， 也可在形成所述伪栅 142之后、 形成所述侧墙 144之前， 去除暴露的所述栅介质层 120; 此时， 所述侧墙 144环绕所述伪栅 142 和所述栅介质层 120 (本文件中， 将所述伪栅 142、 所述侧墙 144和承 载所述伪栅 142或同时承载所述伪栅 142和所述侧墙 144的所述栅介 质层 120称为伪栅堆叠结构） ， 以利于减小器件的寄生电容。
随后， 以所述伪栅 142和所述侧墙 144为掩膜， 在所述半导体基 底 100中形成源漏区 106,可采用离子注入工艺或外延工艺形成源漏区 106, 不再赘述。 继而， 形成金属层， 所述金属层覆盖所述伪栅堆叠结 构和所述半导体基底 100， 再对承载所述金属层的所述半导体基底 100 执行热处理操作 （如 RTA ) ， 以在所述伪栅 142和暴露的所述半导体 基底 100上形成接触区 108。 所述金属层材料可为 NiPt 、 Ni、 Co或 Ti等， 优选为 NiPt, 所述热处理操作的温度可为 300。 ~ 500。， 如 350。、 400。或 450°; 随后， 再去除未反应的所述金属层。
随后， 如图 9 所示， 在经历上述操作的所述半导体基底上形成阻 挡层 160和层间介质层 162,所述阻挡层 160和所述层间介质层 162覆 盖所述伪栅堆叠结构。 所述阻挡层 160 用以阻挡所述层间介质层 162 中的掺杂离子进入所述半导体基底 100 中。 本实施例中， 所述阻挡层 1.60材料可为氮化硅。 在其他实施例中， 所述阻挡层 160还可选用其他 材料。 所述层间介质层 162 材料可为未掺杂或掺杂的氧化硅玻璃 （如 氟硅玻璃、 硼硅玻璃、 磷硅玻璃、 硼磷硅玻璃、 碳氧化硅或碳氮氧化 硅等） 或者低介电常数介质材料 （如黑钻石、 coral等） 中的一种或其 组合。
再后，如图 10所示，平坦化所述阻挡层 160及所述层间介质层 162， 以暴露所述伪栅 142、 所述侧墙 144和所述阻挡层 160。 可采用化学机 械研磨 （CMP ) 工艺执行所述平坦化操作。 然后， 如图 1 1所示， 以掩 膜 180 (如氧化硅层） 覆盖所述 NMOS器件区， 在 PMOS器件区内以 栅极材料替代所述伪栅 142; 具体为： 去除所述伪栅 142, 以形成凹槽； 再以所述栅极材料填充所述凹槽。 填充所述凹槽的所述栅极材料可被 反刻一部分。
所述栅极材料包括层叠的功函数金属层 146 (所述功函数金属层
146为 P型材料， 所述功函数金属层 146提供的功函数与 Si的价带之 间的差值小于 0.2eV, 所述功函数金属层 146 材料可以包括 MoNx、 TiSiN、 TiCN、 TaAlC、 TiAlN> TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu、 RuOx中的任一种或多种的组合）和主金属层 148 , 所述主金属 层 148可以包括 Al、 Ti、 TiAl、 Ta、 W或 Cu中的一种或其组合， 优 选为 TiAl。 在形成所述功函数金属层 146之前， 还可先去除由所述凹 槽暴露的所述栅介质层 120, 而形成新栅介质层 150, 此时所述新栅介 质层 150覆盖所述凹槽的底壁和侧壁。 随后， 以掩膜 （如氧化硅层） 覆盖所述 PMOS 器件区， 在 NMOS 器件区内形成栅极， 位于 NMOS 器件区的所述栅极和位于 PMOS器件区的所述栅极的区别在于： 位于 NMOS器件区的所述栅极中， 功函数金属层为 N型材料， 所述功函数 金属层提供的功函数与 Si 的导带之间的差值小于 0.2eV， 所述功函数 金属层材料可以包括 TaC、 TiN、 TaTbN、 TaErN、 TaYbN、 TaSiN、 HfSiN、 MoSiN, RuTax或 NiTax。 其中， 位于 NMOS 器件区的所述 主金属层 148 和位于 PMOS 器件区的所述主金属层 148 均可优选为 TiAl , 且考虑到工艺的成熟度的影响， 所述 TiAl通常具有压应力。
再后， 以掩膜 180 (如氧化硅层）覆盖所述 NMOS器件区， 暴露
PMOS器件区的所述栅极、 所述侧墙 144和所述阻挡层 160。 如图 12 所示， 去除所述侧墙 144, 以形成空腔 182。 需说明的是， 由于所述阻 挡层 160材料与所述侧墙 144材料相同， 在去除所述侧墙 144时， 暴 露的 （未被所述层间介质层 162覆盖的） 所述阻挡层 160也将被去除。 当然， 在其他实施例中， 所述阻挡层 160材料与所述侧墙 144材料可 不相同， 则在去除所述侧墙 144时， 暴露的所述阻挡层 160将被保留 (图未示） 。 可采用干法刻蚀或湿法刻蚀执行所述去除操作。
在形成栅极时， 考虑工艺成熟度的影响， 其中的主金属层通常具 有压应力 （进而使所述栅极具有压应力） ， 所述压应力将经所述侧墙 对器件的沟道区产生拉应力， 而对于 PMOS器件而言， 在器件的沟道 区产生拉应力， 易导致器件性能的恶化； 而去除 PMOS 器件中的所述 侧墙， 相当于切断了向所述沟道区传导所述压应力以产生所述拉应力 的途径， 即， 可释放 PMOS器件中所述栅极具有的所述压应力， 进而 减少 PMOS器件内所述沟道区所承受的所述拉应力， 利于改善器件性 能。
然后， 如图 13所示， 以辅助层 184填充所述空腔 182。 所述辅助 层 184可具有压应力。 所述辅助层 184材料可为氮化硅。 在所述空腔 182中填充辅助层 184, 且使所述辅助层 184具有压应力， 所述压应力 将传导至所述沟道区， 并对所述沟道区产生压应力， 利于进一步改善 器件性能； 通过使所述辅助层 184材料与所述侧墙 144材料相同， 利 于本发明提供的技术方案与现有工艺的兼容。 实践中， 在释放全部或 部分压应力后， 所述栅极中仍可能残留的压应力， 可通过工艺控制使 所述残留的压应力与所述辅助层 184 具有的压应力对形成于所述 PMOS 器件内的沟道区产生压应力。 需强调的是， 此时， 即使所述辅 助层 184 不表现其应力， 而所述栅极表现压应力， 虽然由于所述栅极 提供的压应力仍将在 pmos器件沟道区中产生拉应力，但在去除侧墙以 释放全部或部分压应力后， 所述拉应力仍将被减小， 而利于改善器件 性能。
此外， 需说明的是， 在其他实施例中， 即使所述栅极不具有压应 力， 即， 对于 PMOS器件而言， 不会由于所述栅极具有压应力， 而在 PMOS器件的沟道区产生拉应力，通过去除所述侧墙 144，以形成空腔， 进而在所述空腔中填充具有压应力的辅助层 184,所述压应力将传导至 所述沟道区， 并对所述沟道区产生压应力， 而利于改善器件性能。
另， 所述具有压应力的辅助层 184 既可以采用下述各种传统工艺 单独形成， 也可直接利用在形成下一层层间介质层（ILD, 实践中， 多 为掺杂或未掺杂的氧化硅玻璃） 之前而形成的刻蚀停止层 （实践中， 多为氮化硅） ， 只是此时所述刻蚀停止层也具有压应力。
在上述实施例中，可采用脉冲激光沉积（ PLD )、原子层淀积（ ALD )、 等离子体增强原子层淀积 （PEALD ) 或其他适合的工艺形成所述栅介 质层 120、 所述牺牲层 140、 所述阻挡层 160、 所述层间介质层 162和 所述辅助层 184。
此外， 本发明还提供了一种半导体器件， 所述半导体器件包括
PMOS器件， 所述 PMOS器件包括：
栅介质层， 所述栅介质层形成于半导体基底上；
栅极， 所述栅极形成于所述栅介质层上；
辅助层， 所述辅助层形成于所述半导体基底上， 所述辅助层环绕 所述栅极及所述栅介质层或者环绕所述栅极且覆盖所述栅介质层； 所 述辅助层具有第一压应力、 或所述辅助层具有第一压应力且所述栅极 具有第二压应力， 以对形成于所述 PMOS器件内的沟道区产生压应力。 所述半导体基底经由在所述晶片内形成阱区及隔离区后获得。 所 述晶片可以包括硅片 （本实施例） 或其他化合物半导体， 如碳化硅、 砷化镓、 砷化铟或磷化铟； 此外， 所述晶片优选地包括外延层； 所述 晶片也可以包括绝缘体上硅（SOI ) 结构。 所述栅介质层可以选用铪基 材料， 如 Hf02、 HfSiO、 HfSiON、 HfTaO, HfTiO或 HfZrO中的一种 或其组合。
所述栅极包括层叠的功函数金属层 （对于 PMOS器件， 所述功函 数金属层为 P型材料， 所述功函数金属层提供的功函数与 Si的价带之 间的差值小于 0.2eV， 所述功函数金属层材料可以包括 MoNx、 TiSiN、 TiCN、 TaAlC TiAlN、 TaN、 PtSix、 Ni3Si、 Pt、 Ru、 Ir、 Mo、 HfRu RuOx中的任一种或多种的组合）和主金属层， 所述主金属层可以包括 Al、 Ti、 TiAK Ta、 W或 Cu中的一种或其组合， 优选为 TiAl。 所述辅 助层材料可为氮化硅。
其中， 对半导体器件各实施例中各部分的结构组成、 材料及形成 方法等均可与前述半导体器件的形成方法实施例中描述的相同， 不在 赘述。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的 工艺、 结构、 制造、 物质组成、 手段、 方法及步骤。 根据本发明的公 开内容， 本领域技术人员将容易地理解， 对于目前已存在或者以后即 将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 它们 在执行与本发明描述的对应实施例大体相同的功能或者获得大体相同 的结果时， 依照本发明的教导， 可以对它们进行应用， 而不脱离本发 明所要求保护的范围。

Claims

权 利 要 求
1、一种半导体器件的形成方法，所述半导体器件包括 PMOS器件， 其特征在于， 形成所述 PMOS器件的步骤包括：
形成栅堆叠结构， 所述栅堆叠结构包括栅介质层、 栅极和侧墙， 所述栅介质层形成于半导体基底上， 所述栅极形成于所述栅介质层上， 所述侧墙环绕所述栅极及所述栅介质层或者环绕所述栅极且覆盖所述 栅介质层；
去除所述侧墙， 以形成空腔；
以辅助层填充所述空腔， 所述辅助层具有第一压应力。
2、 根据权利要求 1所述的方法， 其特征在于： 所述辅助层材料为 氮化硅。
3、 根据权利要求 1或 2所述的方法， 其特征在于， 形成所述栅堆 叠结构的步骤包括：
形成伪栅堆叠结构， 所述伪栅堆叠结构包括栅介质层、 伪栅和侧 墙， 所述栅介质层形成于半导体基底上， 所述伪栅形成于所述栅介质 盖所述栅介质层；
形成阻挡层及层间介质层， 所述阻挡层形成于所述半导体基底上 且覆盖所述伪栅堆叠结构， 所述层间介质层覆盖所述阻挡层；
平坦化所述阻挡层及所述层间介质层， 以暴露所述伪栅、 所述侧 墙和所述阻挡层；
以栅极材料替代所述伪栅， 所述栅极材料具有第二压应力， 所述 第二压应力及所述第一压应力对形成于所述 PMOS器件内的沟道区产 生压应力。
4、根据权利要求 3所述的方法，其特征在于：所述栅极材料为 TiAl。
5、 根据权利要求 3所述的方法， 其特征在于： 所述阻挡层材料与 所述侧墙材料相同， 在去除所述侧墙时， 也去除暴露的所述阻挡层。
6、一种半导体器件的形成方法，所述半导体器件包括 PMOS器件， 其特征在于， 形成所述 PMOS器件的步骤包括：
形成栅堆叠结构， 所述栅堆叠结构包括栅介质层、 栅极和侧墙， 所述栅介质层形成于半导体基底上， 所述栅极形成于所述栅介质层上 且所述栅极材料具有第二压应力， 所述侧墙环绕所述栅极及所述栅介 质层或者环绕所述栅极且覆盖所述栅介质层；
去除所述侧墙， 以形成空腔；
以辅助层填充所述空腔。
7、 根据权利要求 6所述的方法， 其特征在于： 所述辅助层具有第 一压应力， 所述第一压应力及所述第二压应力对形成于所述 PMOS器 件内的沟道区产生压应力。
8、 根据权利要求 7所述的方法， 其特征在于： 所述辅助层材料为 氮化硅。
9、 根据权利要求 6所述的方法， 其特征在于， 形成所述栅堆叠结 构的步骤包括：
形成伪栅堆叠结构， 所述伪栅堆叠结构包括栅介质层、 伪栅和侧 • 墙， 所述栅介质层形成于半导体基底上， 所述伪栅形成于所述栅介质 层上， 所述侧墙环绕所述伪栅及所述栅介质层或者环绕所述伪栅且覆 盖所述栅介质层；
形成阻挡层及层间介质层， 所述阻挡层形成于所述半导体基底上 且覆盖所述伪栅堆叠结构， 所述层间介质层覆盖所述阻挡层；
平坦化所述阻挡层及所述层间介质层， 以暴露所述伪栅、 所述侧 墙和所述阻挡层；
以栅极材料替代所述伪栅。
10、 根据权利要求 6 所述的方法， 其特征在于： 所述栅极材料为 TiAh
1 1、 根据权利要求 6 所述的方法， 其特征在于： 所述阻挡层材料 与所述侧墙材料相同， 在去除所述侧墙时, 也去除暴露的所述阻挡层。
12、 一种半导体器件， 所述半导体器件包括 PMOS 器件， 其特征 在于， 所述 PMOS器件包括：
栅介质层， 所述栅介质层形成于半导体基底上；
栅极， 所述栅极形成于所述栅介质层上；
辅助层， 所述辅助层形成于所述半导体基底上， 所述辅助层环绕 所述栅极及所述栅介质层或者环绕所述栅极且覆盖所述栅介质层； 所 述辅助层具有第一压应力、 或所述辅助层具有第一压应力且所述栅极 具有第二压应力， 以对形成于所述 PMOS器件内的沟道区产生压应力。
13、 根据权利要求 12所述的半导体器件， 其特征在于： 所述辅助 层材料为氮化硅。
14、 根据权利要求 12或 13所述的半导体器件， 其特征在于： 所 述栅极材料为 TiAl。
PCT/CN2011/000337 2010-07-01 2011-03-02 一种半导体器件及其形成方法 Ceased WO2012000301A1 (zh)

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