WO2011160422A1 - 一种半导体器件及其形成方法 - Google Patents

一种半导体器件及其形成方法 Download PDF

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Publication number
WO2011160422A1
WO2011160422A1 PCT/CN2011/000684 CN2011000684W WO2011160422A1 WO 2011160422 A1 WO2011160422 A1 WO 2011160422A1 CN 2011000684 W CN2011000684 W CN 2011000684W WO 2011160422 A1 WO2011160422 A1 WO 2011160422A1
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Prior art keywords
layer
gate stack
stack structure
interlayer material
region
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English (en)
French (fr)
Inventor
钟汇才
梁擎擎
尹海洲
朱慧珑
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to GB1202153.1A priority Critical patent/GB2484249B/en
Priority to US13/266,555 priority patent/US8637935B2/en
Publication of WO2011160422A1 publication Critical patent/WO2011160422A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/822—Heterojunctions comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method of forming the same.
  • a method of forming a semiconductor device includes: first, as shown in FIG. 1, a recess 30 is formed in the semiconductor substrate 10 (a hard mask 20 may be formed on a surface of the semiconductor substrate 10, Then, as shown in FIG. 2, the recess 30 is filled with an insulating material such as silicon oxide to form an isolation region 32 (such as STI) on the semiconductor substrate 10 and by the isolation region 32. Surrounded by the active region 12; then, as shown in FIG.
  • At least one gate stack structure (and source and drain regions 60) is formed on the active region 12 and sandwiched between each of the gate stack structures (including the gate dielectric) a layer 44, an interlayer dielectric layer 50 (such as doped or undoped) between the gate 40 formed on the gate dielectric layer 44 and the sidewall spacer 42 surrounding the gate dielectric layer 44 and the gate 40
  • the semiconductor device can be externally connected.
  • the gate stack structure is formed after the isolation region 32.
  • the industry has always desired to reduce the area of the isolation regions to increase the area of the active regions, thereby increasing the number of devices formed on the semiconductor substrate per unit area.
  • various microscopic effects have begun to appear. It is becoming more and more difficult to reduce the area of the isolation region under the constraints of the design rules of the semiconductor device.
  • the present invention provides a semiconductor device and a method of forming the same, which can reduce the area of the isolation region.
  • a method of forming a semiconductor device provided by the present invention includes:
  • the semiconductor substrate carrying the gate stack structure in the region is removed; the recess is filled with an insulating material.
  • the interlayer material layers are of the same material.
  • the interlayer material layer is a semiconductor layer.
  • the method further includes:
  • a heat treatment operation is performed to form the interlayer material layer to form a conductive layer.
  • a method of forming a semiconductor device provided by the present invention includes:
  • the interlayer material layers are of the same material.
  • the interlayer material layer is a semiconductor layer.
  • the method further includes:
  • a heat treatment operation is performed to form the interlayer material layer to form a conductive layer.
  • the present invention provides a semiconductor device in which each of the semiconductor devices is isolated by an isolation region, the isolation region being embedded in a semiconductor substrate, the semiconductor device comprising: an interlayer material layer and at least one gate stack structure, the gate a stacked structure is formed on the semi-conductive substrate, a partial region of the gate stack structure is located on the isolation region; and a portion located on the isolation region
  • the upper surface of the gate stack structure is lower than the upper surface of the gate stack structure located in the isolation region; the interlayer material layer is sandwiched between each of the gate stack structures.
  • the interlayer material layer is formed on an upper surface of the gate stack structure on the isolation region.
  • the interlayer material layers are of the same material.
  • the interlayer material layer is a semiconductor layer or a conductive layer.
  • the technical solution provided by the present invention has the following advantages: Since the minimum size required in the design rule is larger than the minimum size allowed in the process of exposure, etching, etc., the isolation region is formed at the beginning to form a gate. After stacking the structure, fully utilizing the precision advantages of exposure, etching, etc., forming the groove, and then forming an isolation region, which can reduce the area of the isolation region;
  • the conductive layer By forming the interlayer material layer as a semiconductor layer, and further forming the metal layer on the semiconductor layer to form the conductive layer after undergoing a heat treatment operation, the conductive layer can be utilized as a contact hole, which facilitates a process .
  • FIG. 1 to FIG. 3 are schematic diagrams showing the intermediate structure of each step of the method for forming a semiconductor device in the prior art
  • FIG. 4 and FIG. 5 are a plan view and a cross-sectional view showing the formation of each material layer on the semiconductor substrate in the embodiment of the method for forming a semiconductor device according to the present invention
  • FIG. 6 and FIG. 7 are top and cross-sectional views showing the patterned barrier layer, the gate base layer and the gate dielectric layer in the embodiment of the method for forming a semiconductor device of the present invention
  • FIGS. 8 and 9 are a plan view and a cross-sectional view showing a protective layer formed in an embodiment of a method of forming a semiconductor device of the present invention.
  • FIG. 10 is a plan view showing a photoresist pattern formed in an embodiment of a method of forming a semiconductor device according to the present invention.
  • FIG. 11 and FIG. 12 are a plan view and a cross-sectional view showing the first side wall formed in the embodiment of the method for forming a semiconductor device of the present invention
  • FIG. 13 is a plan view showing the photoresist removal process in the embodiment of the method for forming a semiconductor device according to the present invention
  • FIG. 14 and FIG. 15 are a plan view and a cross-sectional view showing a trench formed in an embodiment of a method for forming a semiconductor device according to the present invention
  • FIG. 16 and FIG. 17 are a plan view and a cross-sectional view showing a first semiconductor layer formed in an embodiment of a method of forming a semiconductor device according to the present invention
  • FIG. 18 and FIG. 19 are a plan view and a cross-sectional view showing a first interlayer material layer formed in an embodiment of a method of forming a semiconductor device according to the present invention.
  • FIG. 20 and FIG. 21 are a plan view and a cross-sectional view showing a second interlayer material layer in an embodiment of a method of forming a semiconductor device according to the present invention
  • Figure 22 is a plan view showing the planarization of the interlayer material layers and the removal of the barrier layer in the embodiment of the method for forming a semiconductor device of the present invention
  • FIG. 23 and FIG. 24 are cross-sectional views of FIG. 22 taken along AA, and BB, respectively, after cutting the formed structure;
  • Figure 25 is a plan view showing a groove in the embodiment of the method for forming a semiconductor device of the present invention.
  • 26 and 27 are cross-sectional views showing the structure formed by cutting the formed structures along AA, and BB' in Fig. 25, respectively;
  • FIG. 28 and FIG. 29 are a plan view and a cross-sectional view showing, in the embodiment of the method for forming a semiconductor device of the present invention, without removing the silicon substrate under the isolation stack from the substrate of the gate stack structure;
  • Figure 30 is a cross-sectional view showing the embodiment of the method of forming a semiconductor device of the present invention in which the silicon substrate under the isolation stack is placed under the substrate of the gate stack structure;
  • Figure 31 is a plan view showing the embodiment of the method for forming a semiconductor device of the present invention after filling the groove;
  • Figure 32 and Figure 33 are cross-sectional views of Figure 31 taken along AA, and BB, respectively, after cutting the formed structure;
  • Figure 34 is a plan view showing a structure in which a gate stack structure is formed in an embodiment of a method of forming a semiconductor device of the present invention
  • Fig. 35 and Fig. 36 are cross-sectional views showing the structure in Fig. 34 taken along AA, and BB, respectively, after cutting the formed structure.
  • the present invention may repeat reference numerals and/or letters in different embodiments. This repetition is for the purpose of simplification and clarity, and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the method for forming the semiconductor device includes:
  • a gate dielectric layer 102, a gate base layer 104, and a barrier layer 1042 are sequentially deposited on the semiconductor substrate 100, and the barrier layer 1042 is used to pattern the gate substrate.
  • the semiconductor substrate 100 is a silicon substrate.
  • the semiconductor substrate 100 may further include other compound semiconductors such as silicon carbide, gallium arsenide, indium arsenide or phosphating. Indium; further, the semiconductor substrate 100 preferably includes an epitaxial layer; the semiconductor substrate 100 may also include a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • the gate dielectric layer 102 may be selected from a germanium-based material such as Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO or HfZrO or a combination thereof; when the gate is formed by a gate first process, the gate
  • the base layer 104 may be a polysilicon layer or a laminated metal layer (the stacked metal layer includes a work function metal layer, a first metal layer, and a second metal layer, and the work function metal layer may include TiN, TiAlN, TaN, or TaAIN) One or a combination thereof; the first metal layer and the second metal layer may include one or a combination of Al, Ti, Ta, W, or Cu); when a gate is formed by a gate last process, The gate base layer 104 can be a polysilicon layer or an amorphous silicon layer.
  • the barrier layer 1042 may be selected from silicon nitride.
  • the barrier layer 1042 is patterned, and the gated layer 104 and the gate dielectric layer 102 are patterned by using the patterned barrier layer 1042 as a mask.
  • the gate base layer 104 and the gate dielectric layer 102 extend in a first direction (shown as XX in the figure), and the patterning operation can be performed using an etching process.
  • a protective layer 106 is formed.
  • the protective layer 106 covers the barrier layer 1042 and covers the exposed patterned gate substrate layer 104 and the gate dielectric layer 102.
  • the protective layer 106 may be formed using a deposition process.
  • the protective layer 106 can It is silicon nitride.
  • a photoresist 108 is coated on the protective layer 106, and the first region (such as a PMOS device region) is exposed, that is, a photoresist pattern is formed, and the surface of the first region is still
  • the protective layer 106, the other regions of the silicon substrate (such as the second region, that is, the NMOS device region) are covered by the photoresist 108.
  • the protective layer 106 is etched, and in the first region, a first sidewall spacer 1062 is formed, and the second region is covered by the photoresist 108. Etched, at this point, a gate stack structure substrate in the first region is formed.
  • the source and drain regions in the first region may be formed: First, as shown in FIG. 13, the photoresist 108 may be removed to expose the protective layer 106 covered on the second region, which may be followed When the silicon substrate of a portion of the height in the first region is removed, the second region is protected from damage by the protective layer 106, and the photoresist residue is reduced in a subsequent step.
  • a trench 120 is formed in the silicon substrate in the first region, and the trench 120 is located on both sides of the gate stack structure substrate, and may be etched.
  • the process forms the trench 120. Since the silicon substrate is different from the material of the protective layer 106, a suitable etchant may be selected such that the protective layer 106 is removed when a portion of the height of the silicon substrate is removed. The loss is less; therefore, after the trench 120 is formed, the second region is still covered with the protective layer 106. After the trenches 120 are formed, an ion implantation operation (in the direction indicated by the arrow in the figure) can be continued to perform halo implantation in the silicon substrate.
  • a first semiconductor layer 140 is formed in the trench 120; the first semiconductor layer 140 may be made of Si; and for the PMOS device, the first semiconductor layer 140 may also be made of a material For Si 1-x Ge x (the atomic percentage of Ge can be 40%, the content of Ge can be flexibly adjusted according to the process requirements, for example, X can be any value from 10% to 70%, specifically, X can be 20%, 30%, 40%, 50% or 60%, where there is no special description in this document, the atomic percentage of Ge is the same, and will not be described again);
  • the channel region of the PMOS device provides compressive stress to improve CMOS device performance.
  • the first semiconductor layer 140 may be formed by epitaxial method in which the silicon substrate is a seed crystal.
  • the first semiconductor layer 140 may be a semiconductor material that has completed ion doping, for example, may be N-type or P-type Si or Si 1-x Ge x .
  • the ion doping operation may be formed directly during the process of generating the first semiconductor layer 140 (eg, at a generation site)
  • the reactant of the first semiconductor layer 140 is doped with a reactant containing a doping ion component; or may be formed by an ion implantation process after the first semiconductor layer 140 is formed, and any conventional ion implantation process may be employed.
  • the ion doping operation is performed and will not be described again.
  • the source and drain regions may be formed without first forming the trench to refill the semiconductor material, and an ion implantation operation may be directly performed into the silicon substrate by a conventional method to form the source and drain. Area.
  • first interlayer material layer 160 sandwiched between the respective gate stack structure substrates is formed, and the first interlayer material layer 160 covers the source and drain regions;
  • the first interlayer material layer 160 may be the same material as the first semiconductor layer 140, and the first interlayer material layer 160 may be formed by epitaxial formation of the first semiconductor layer 140 as a seed crystal. .
  • the first interlayer material layer 160 may be a conventional interlayer dielectric layer, and the interlayer dielectric layer may be doped or undoped vitreous silica (such as fluorosilicate glass, borosilicate).
  • a low dielectric constant dielectric material such as black diamond, coral, etc.
  • the first interlayer material layer 160 may be formed by chemical vapor deposition (CVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or other suitable process.
  • CVD chemical vapor deposition
  • PLD pulsed laser deposition
  • ALD atomic layer deposition
  • PEALD plasma enhanced atomic layer deposition
  • a photoresist 108 is coated on the silicon substrate subjected to the above operation, exposing the protective layer 106 located in the second region (the photoresist 108 remains on the first region), Etching the protective layer 106 to form a second spacer 1064 (so far, forming a gate stack structure in the second region), and etching the silicon by using the second spacer 1064 as a mask Forming a trench 120 to form a second semiconductor layer 142 to fill the trench 120 to form source and drain regions in the second region, thereby forming a substrate sandwiched between each of the gate stack structures
  • the second semiconductor layer 162 may be Si or Si: C (the atomic percentage of C may be 0-2%, such as 0.5%, 1% or 1.5%, and the content of C may be flexibly adjusted according to process requirements, Unless otherwise specified in the document, the atomic percentage of C is the same as that of the above, and will not be described again; the second semiconductor layer 162 may be provided with tensile stress to the channel region of the NMOS device, which is advantageous for improving the performance of the CMOS device. .
  • the second semiconductor layer 162 can The silicon substrate is formed by epitaxy for the seed crystal.
  • the second semiconductor layer 162 may also be a semiconductor material that has been ion-doped, or may be formed by an ion implantation process after the second semiconductor layer 162 is formed.
  • the ion doping operation is performed using any conventional ion implantation process and will not be described again.
  • an ion implantation operation may be performed directly into the silicon substrate by a conventional method to form the source and drain regions.
  • the second interlayer material layer 162 is the same material as the second semiconductor layer 142, and the second interlayer material layer 162 may be formed by epitaxial formation of the second semiconductor layer 142 as a seed crystal. .
  • first interlayer material layer 160 and the second interlayer material layer 162 may be the same material, for example, may be Si, 8 ⁇ ) 4 06 5 ( or 8 ⁇ C; for PMOS devices and NMOS devices) The device performs subsequent operations synchronously.
  • the silicon substrate of the above structure is obtained by planarization, and the barrier layer 1042 is removed, and the planarization operation may be performed by a chemical mechanical polishing (CMP) process;
  • CMP chemical mechanical polishing
  • a dummy gate a gate substrate made of polysilicon or amorphous silicon
  • a replacement gate which may be a laminated metal layer
  • isolation is determined.
  • the region and the portion of the interlayer material layer and the portion of the silicon substrate located in the region are removed to form the recess 180; the recess 180 may be formed by an etching process.
  • the gate stack structure is in the matrix Only a portion of the material of the gate substrate 104 (such as metal) is removed (when the gate gate process 104 is made of polysilicon or amorphous silicon, the material is approximately the same as the silicon substrate material, and the removed portion is removed. The degree of material is slightly heavier), forming a recess 182, and as shown in FIGS.
  • the silicon substrate under the substrate of the gate stack structure (indicated by a dashed box in the figure) Is removed, whereby the devices that should be isolated by the isolation region can be turned on via the silicon substrate that is not removed by this portion; to achieve the isolation effect, as shown in FIG. 30, the removal is located in the region.
  • the silicon substrate carrying the gate stack structure substrate is located in the region.
  • An isotropic etching process (such as a wet etching process may be employed, in which the silicon substrate carrying the gate stack structure substrate in the isolation region is removed and holes are formed, and the holes are formed Filled with a recess or a passivation process (such as an oxidation process), the silicon liner carrying the gate stack structure in the isolation region when the process is applied N2011/000684 The bottom is passivated to an insulating material)
  • the removal operation is performed. After the removal operation, the area indicated by the dashed box is engraved or passivated into an insulating material. Thereafter, as shown in FIGS. 31 to 33, the recess 180 is filled with an insulating material (which may be silicon oxide) to form an isolation region 184.
  • a replacement gate can also be formed after the isolation region 184 is formed.
  • a metal layer is further formed on the first interlayer material layer 160 and the second interlayer material layer 162, and then a heat treatment operation (such as rapid thermal annealing) is performed to make the first interlayer material layer 160 and
  • the second interlayer material layer 162 forms a conductive layer (such as a metal silicide layer), and the conductive layer can be utilized as a contact hole, which is advantageous for simplifying the process.
  • the gate stack structure substrate is cut in a second direction to form a gate stack structure, and the second direction yy is different from the first direction (in this embodiment, The second direction is perpendicular to the first direction).
  • the gap formed after cutting the gate stack structure substrate will be filled with the subsequent interlayer dielectric layer 186 material.
  • the gate may be formed by a gate first process or a gate last process, and the recess 180 may be formed after the gate stack structure substrate is formed, and the gate stack structure substrate is cut. Before (this embodiment); may also be formed after cutting the gate stack structure substrate (other embodiments), at this time, the slit formed after cutting the gate stack structure substrate needs to be filled with insulation before forming the groove 180 A material to prevent the exposed silicon substrate from being removed (ie, preventing the exposed silicon substrate from forming an insulating medium, which in turn changes device performance).
  • the recess 180 may be formed after the dummy gate, before the gate is replaced (this embodiment), or after the gate is replaced, before the gate stack structure is cut. (Other embodiments).
  • the isolation region is formed, and a second embodiment of the method of forming the semiconductor device provided by the present invention can be constructed.
  • the method includes:
  • At least one gate stack structure and an interlayer material layer sandwiched between each of the gate stack structures are formed on a silicon substrate;
  • the isolation region region is determined and the interlayer material layer and a portion of the height of the silicon substrate located in the region are removed to form a recess;
  • the silicon substrate carrying the gate stack structure in the region is removed; finally, the recess is filled with an insulating material.
  • the second embodiment of the method of forming the semiconductor device is equivalent to, in the embodiment after the recess is formed in the substrate after cutting the gate stack structure, the gate stack is not formed first.
  • the stacked structure substrate forms the gate stack structure by cutting the gate stack structure substrate, but directly forms the gate stack structure, and then forms the recess to form the isolation region. Conducive to compatibility with existing processes.
  • the present invention also provides a semiconductor device. As shown in FIG. 35, each of the semiconductor devices is isolated by an isolation region 184, and the isolation region 184 is embedded in the semiconductor substrate 100.
  • the semiconductor device includes: an interlayer material layer And at least one gate stack structure, the gate stack structure is formed on the semiconductor substrate 100, a partial region of the gate stack structure is located on the isolation region 184; the gate on the isolation region 184 The upper surface of the stacked structure is lower than the upper surface of the gate stack structure located within the isolation region 184; the interlayer material layer is sandwiched between each of the gate stack structures.
  • the interlayer material layer is formed on an upper surface of the gate stack structure on the isolation region.
  • the interlayer material layers are of the same material.
  • the interlayer material layer is a semiconductor layer or a conductive layer.
  • the substrate is a silicon substrate.
  • the substrate may further include other compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide or indium phosphide;
  • the substrate preferably includes an epitaxial layer; the substrate may also include a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • the gate stack structure includes a gate dielectric layer, a gate formed on the gate dielectric layer, and a sidewall surrounding the gate dielectric layer and the gate.
  • the gate dielectric layer may be selected from a germanium-based material such as one or a combination of Hf0 2 , HfSiO, HfSiON, HfTaO, HfTiO or HfZrO; the gate may be a polysilicon layer or a laminated metal layer, the laminated metal layer
  • the work function metal layer, the first metal layer and the second metal layer are included, and the work function metal layer may include one or a combination of TiN, TiAlN, TaN or TaAIN; the first metal layer and the second metal layer
  • One or a combination of Al, Ti, Ta, W, or Cu may be included;
  • the sidewall spacer may be silicon nitride or stacked silicon nitride-silicon oxide-silicon nitride.
  • the semiconductor layer material may be Si or Si 1-x Ge x ;
  • the semiconductor layer can be made to provide compressive stress to the channel region of the PMOS device, which is advantageous for improving the performance of the CMOS device.
  • the semiconductor layer may be Si or Si: C; when Si: C is selected, the semiconductor layer may be subjected to tensile stress to a channel region of the NMOS device, which is advantageous for improving CMOS device performance.
  • the conductive layer may be a metal silicide layer.
  • the first interlayer material layer may be a conventional interlayer dielectric layer, and the interlayer dielectric layer may be doped or undoped vitreous silica (such as fluorosilicate glass, boron).
  • the interlayer dielectric layer may be doped or undoped vitreous silica (such as fluorosilicate glass, boron).
  • a silicon glass, a phosphosilicate glass, a borophosphosilicate glass, a silicon oxycarbide or a silicon oxycarbonitride, or a low dielectric constant dielectric material such as black diamond, coral, or the like.

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Description

一种半导体器件及其形成方法
优先权要求
本申请要求了 2010年 6月 22日提交的、申请号为 201010215165.2、 发明名称为 "一种半导体器件及其形成方法" 的中国专利申请的优先 权， 其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域， 具体来说， 涉及一种半导体器件及 其形成方法。
背景技术
现有技术中， 半导体器件的形成方法， 包括： 首先， 如图 1所示， 在所述半导体衬底 10内形成凹槽 30 (可在所述半导体衬底 10表面预 先形成硬掩膜 20， 如氧化硅） ； 随后， 如图 2所示， 以绝缘材料 （如 氧化硅） 填充所述凹槽 30, 以在半导体衬底 10上形成隔离区 32 (如 STI ) 和被所述隔离区 32包围的有源区 12; 再后， 如图 3所示， 在所 述有源区 12上形成至少一个栅堆叠结构（以及源漏区 60 )和夹于各所 述栅堆叠结构 （包括栅介质层 44、 形成于所述栅介质层 44 上的栅极 40及环绕所述栅介质层 44和所述栅极 40的侧墙 42 )之间的层间介质 层 50 (如掺杂或未掺杂的氧化硅） ， 在所述层间介质层 50内形成接触 孔后， 可对所述半导体器件实现外连。 换言之， 所述栅堆叠结构形成 在所述隔离区 32之后。
出于各种 （如成本） 考虑， 业界总是希望减小所述隔离区的面积， 以增加所述有源区的面积， 进而增加在单位面积的所述半导体衬底上 形成器件的数目。 但是， 随着半导体器件临界尺寸的逐渐减小， 各种 微观效应开始显现。 在半导体器件的设计规则限制下， 减小所述隔离 区的面积变得越来越困难。
发明内容
为了解决上述问题， 本发明提供了一种半导体器件及其形成方法， 可减小隔离区的面积。
本发明提供的一种半导体器件的形成方法， 包括：
在半导体衬底上形成至少一个栅堆叠结构和夹于各所述栅堆叠结 构之间的层间材料层； 确定隔离区区域并去除位于所述区域内的所述层间材料层和部分 高度的所述半导体衬底， 以形成凹槽；
去除位于所述区域内承载所述栅堆叠结构的所述半导体衬底； 以绝缘材料填充所述凹槽。 可选地， 对于 PMOS器件和 NMOS器件， 所述层间材料层材质相 同。
可选地， 所述层间材料层为半导体层。
可选地， 还包括：
形成金属层， 所述金属层覆盖所述层间材料层；
执行热处理操作， 使所述层间材料层形成导电层。
本发明提供的一种半导体器件的形成方法， 包括：
在半导体衬底上形成至少一个沿第一方向延伸的栅堆叠结构基体 和夹于各所述栅堆叠结构基体之间的层间材料层；
确定隔离区区域并去除位于所述区域内的所述层间材料层和部分 高度的所述半导体衬底， 以形成凹槽；
去除位于所述区域内承载所述栅堆叠结构基体的所述半导体衬 底；
以绝缘材料填充所述凹槽；
利用所述栅堆叠结构基体形成栅堆叠结构， 并沿第二方向切割所 述栅堆叠结构， 所述第二方向异于所述第一方向。 可选地， 对于 PMOS器件和 NMOS器件， 所述层间材料层材料相 同。
可选地， 所述层间材料层为半导体层。
可选地， 还包括：
形成金属层， 所述金属层覆盖所述层间材料层；
执行热处理操作， 使所述层间材料层形成导电层。
本发明提供的一种半导体器件， 各所述半导体器件被隔离区隔离， 所述隔离区嵌于半导体衬底内， 所述半导体器件包括： 层间材料层和 至少一个栅堆叠结构， 所述栅堆叠结构形成于所述半导休衬底上， 所 述栅堆叠结构的部分区域位于所述隔离区上； 位于所述隔离区上的所 述栅堆叠结构的上表面低于位于所述隔离区内的所述栅堆叠结构的上 表面； 所述层间材料层夹于各所述栅堆叠结构之间。
可选地， 在位于所述隔离区上的所述栅堆叠结构的上表面上形成 有所述层间材料层。
可选地， 对于 PMOS器件和 NMOS器件， 所述层间材料层材质相 同。
可选地， 所述层间材料层为半导体层或导电层。
与现有技术相比， 采用本发明提供的技术方案具有如下优点： 由于设计规则中要求的最小尺寸大于曝光、 刻蚀等工艺中允许的 最小尺寸， 通过使所述隔离区形成于开始形成栅堆叠结构之后， 充分 利用曝光、 刻蚀等工艺的精度优势， 形成所述凹槽， 继而形成隔离区， 可减小所述隔离区的面积；
通过使所述层间材料层为半导体层， 进而在所述半导体层上形成 所述金属层， 以在经历热处理操作后形成所述导电层， 可利用所述导 电层作为接触孔， 利于简化工艺。
附图说明
下列图 4 至图 21 中各剖视图均为沿对应的俯视图中给出的剖线 ( AA， ） 切割已形成的结构后获得。
图 1 至图 3所示为现有技术中施行半导体器件的形成方法各步骤 时的中间结构示意图；
图 4和图 5所示为本发明半导体器件的形成方法实施例中在半导 体村底上形成各材料层后的俯视图和剖视图；
图 6和图 7所示为本发明半导体器件的形成方法实施例中图形化 阻挡层、 栅极基体层和栅介质层后的俯视图和剖视图；，
图 8和图 9所示为本发明半导体器件的形成方法实施例中形成保 护层后的俯视图和剖视图；
图 10所示为本发明半导体器件的形成方法实施例中形成光刻胶图 形后的俯视图；
图 11和图 12所示为本发明半导体器件的形成方法实施例中形成 第一侧墙后的俯视图和剖视图；
图 13所示为本发明半导体器件的形成方法实施例中去除光刻胶后 的俯视图； 2011/000684 图 14和图 15所示为本发明半导体器件的形成方法实施例中形成 沟槽后的俯视图和剖视图；
图 16和图 17所示为本发明半导体器件的形成方法实施例中形成 第一半导体层后的俯视图和剖视图；
图 18和图 19所示为本发明半导体器件的形成方法实施例中形成 第一层间材料层后的俯视图和剖视图；
图 20和图 21 所示为本发明半导体器件的形成方法实施例中形成 第二层间材料层后的俯视图和剖视图；
图 22所示为本发明半导体器件的形成方法实施例中平坦化各层间 材料层并去除阻挡层后的俯视图；
图 23和图 24所示为图 22中分别沿 AA， 和 BB， 切割已形成的 结构后获得的剖视图；
图 25所示为本发明半导体器件的形成方法实施例中形成凹槽后的 俯视图；
图 26和图 27所示为图 25中分别沿 AA， 和 BB' 切割已形成的 结构后获得的剖视图；
图 28和图 29所示为本发明半导体器件的形成方法实施例中未去 除隔离区内位于所述栅堆叠结构基体之下的硅衬底时的俯视图和剖视 图；
图 30所示为本发明半导体器件的形成方法实施例中去除隔离区内 位于所述栅堆叠结构基体之下的硅衬底后的剖视图；
图 31所示为本发明半导体器件的形成方法实施例中填充回槽后的 俯视图；
图 32和图 33所示为图 31 中分别沿 AA， 和 BB， 切割已形成的 结构后获得的剖视图；
图 34所示为本发明半导体器件的形成方法实施例中形成栅堆叠结 构后的俯视图；
图 35和图 36所示为图 34中分别沿 AA， 和 BB， 切割已形成的 结构后获得的剖视图。
具体实施方式
下文的公开提供了许多不同的实施例或例子用来实现本发明提供 的技术方案。 虽然下文中对特定例子的部件和设置进行了描述， 但是， 它们仅仅为示例， 并且目的不在于限制本发明。
此外， 本发明可以在不同实施例中重复参考数字和 /或字母。 这种 重复是为了简化和清楚的目的， 其本身不指示所讨论的各种实施例和 / 或设置之间的关系。
本发明提供了各种特定工艺和 /或材料的例子， 但是， 本领域普通 技术人员可以意识到的其他工艺和 /或其他材料的替代应用， 显然未脱 离本发明要求保护的范围。 需强调的是， 本文件内所述的各种区域的 边界包含由于工艺或制程的需要所作的必要的延展。
在本发明提供的半导体器件的形成方法第一实施例中， 所述半导 体器件的形成方法包括：
首先， 如图 4和图 5所示， 在半导体衬底 100上顺次沉积栅介质 层 102、 栅极基体层 104和阻挡层 1042， 所述阻挡层 1042用以作为图 形化所述栅极基体层 104、 栅介质层 102的掩膜层。
在本实施例中， 所述半导体衬底 100为硅村底， 在其他实施例中， 所述半导体衬底 100还可以包括其他化合物半导体， 如碳化硅、 砷化 镓、 砷化铟或磷化铟； 此外， 所述半导体村底 100优选地包括外延层； 所述半导体衬底 100也可以包括绝缘体上硅（ SOI ) 结构。 所述栅介质 层 102可以选用铪基材料， 如 Hf02、 HfSiO、 HfSiON、 HfTaO, HfTiO 或 HfZrO中的一种或其组合； 采用先栅工艺 （gate first ) 形成栅极时， 所述栅极基体层 104 可为多晶硅层或层叠金属层 （所述层叠金属层包 括功函数金属层、 第一金属层和第二金属层， 所述功函数金属层可以 包括 TiN、 TiAlN、 TaN或 TaAIN中的一种或其组合； 所述第一金属层 和第二金属层可以包括 Al、 Ti、 Ta、 W或 Cu中的一种或其组合） ； 采用后栅工艺 （gate last ) 形成栅极时， 所述栅极基体层 104可为多晶 硅层或非晶硅层。 所述阻挡层 1042可选用氮化硅。
随后， 如图 6和图 7所示， 图形化所述阻挡层 1042， 再以图形化 后的阻挡层 1042为掩膜， 图形化所述栅极基体层 104和栅介质层 102, 图形化后的所述栅极基体层 104和栅介质层 102沿第一方向延伸 （如 图中 XX， 所示） ， 可采用刻蚀工艺执行所述图形化操作。
再后， 如图 8和图 9所示， 形成保护层 106， 所述保护层 106覆盖 所述阻挡层 1042, 并覆盖暴露的图形化后的所述栅极基体层 104和栅 介质层 102， 可采用沉积工艺形成所述保护层 106。 所述保护层 106可 为氮化硅。
然后， 如图 10所示， 在所述保护层 106上涂覆光刻胶 108， 并暴 露第一区 （如 PMOS器件区） ， 即， 形成光刻胶图形， 所述第一区表 面仍为所述保护层 106， 所述硅衬底的其他区域（如第二区， 即 NMOS 器件区）表面被光刻胶 108覆盖。
继而， 如图 11和图 12所示， 刻蚀所述保护层 106, 在所述第一区 内， 形成第一侧墙 1062， 所述第二区由于覆盖有所述光刻胶 108而未 受刻蚀， 至此， 形成所述第一区内的栅堆叠结构基体。
随后， 可形成所述第一区内的源漏区： 首先， 如图 13所示， 可去 除所述光刻胶 108， 暴露所述第二区上覆盖的所述保护层 106, 可在后 续去除所述第一区内的部分高度的所述硅衬底时，利用所述保护层 106 保护所述第二区不受损伤， 且利于在后续步骤中减少光刻胶残留。
继而， 如图 14和图 15所示， 在位于所述第一区内的所述硅衬底 内形成沟槽 120, 所述沟槽 120位于所述栅堆叠结构基体两侧， 可采用 刻蚀工艺形成所述沟槽 120， 由于所述硅衬底与所述保护层 106材料不 同， 可选择适当的刻蚀剂， 使得在去除部分高度的所述硅衬底时， 对 所述保护层 106损失较少； 因此， 在形成所述沟槽 120后， 所述第二 区上仍覆盖有所述保护层 106。 形成所述沟槽 120后， 可继续执行离子 注入操作 （如图中箭头所示方向） ， 以在所述硅衬底内进行晕环离子 注入 ( halo implantation ) 。
再如图 16和图 17所示，在所述沟槽 120内形成第一半导体层 140; 所述第一半导体层 140材料可以为 Si; 对于 PMOS器件， 所述第一半 导体层 140材料还可以为 Si1-xGex ( Ge的原子数百分比 x可以为 40%, Ge的含量可以根据工艺需要灵活调节，如 X可为 10%-70%中的任一值， 具体地， X可为 20%、 30%、 40%、 50%或 60%, 本文件内未作特殊说 明处， Ge的原子数百分比均与此相同， 不再赘述） ； 可使所述第一半 导体层 140对所述 PMOS器件的沟道区提供压应力， 利于改善 CMOS 器件性能。 所述第一半导体层 140 可以所述硅衬底为籽晶采用外延法 形成。
需说明的是， 所述第一半导体层 140 可以是已完成离子掺杂的半 导体材料， 如， 可以是 N型或 P型的 Si或 Si1-xGex。 所述离子掺杂操 作可以在生成所述第一半导体层 140 的过程中直接形成 （如在生成所 述第一半导体层 140 的反应物中掺入包含掺杂离子成分的反应物） ； 也可以在生成所述第一半导体层 140后， 再经由离子注入工艺形成， 可采用任何传统的离子注入工艺执行所述离子掺杂操作， 不再赘述。 在其他实施例中， 也可以不采用先形成所述沟槽再填充半导体材料的 方式形成源漏区， 可以采用传统方法直接向所述硅衬底内执行离子注 入操作， 以形成所述源漏区。
继而， 如图 18和图 19所示， 形成夹于各所述栅堆叠结构基体之 间的第一层间材料层 160, 所述第一层间材料层 160覆盖所述源漏区； 在本实施例中， 所述第一层间材料层 160 可与所述第一半导体层 140 的材料相同， 所述第一层间材料层 160可以所述第一半导体层 140为 籽晶采用外延法形成。
在其他实施例中， 所述第一层间材料层 160 可以为传统的层间介 质层， 所述层间介质层可以为掺杂或未掺杂的氧化硅玻璃 （如氟硅玻 璃、 硼硅玻璃、 磷硅玻璃、 硼磷硅玻璃、 碳氧化硅或碳氮氧化硅等） 或者低介电常数介质材料 （如黑钻石、 coral等） 中的一种或其组合。 所述第一层间材料层 160可以采用化学气相沉积 （CVD ) 、 脉冲激光 沉积（ PLD )、原子层淀积（ ALD )、等离子体增强原子层淀积（ PEALD ) 或其他适合的工艺形成。 此时， 为使所述器件实现外连， 需在所述第 一层间材料层 160中形成接触孔。
随后， 在经历上述操作的所述硅衬底上涂覆光刻胶 108， 暴露位于 所述第二区内的所述保护层 106 (在所述第一区上仍保留光刻胶 108 )， 刻蚀所述保护层 106, 以形成第二侧墙 1064 (至此， 在所述第二区内 形成栅堆叠结构基体） ， 并以所述第二侧墙 1064为掩膜， 刻蚀所述硅 衬底， 以形成沟槽 120,进而形成第二半导体层 142填充所述沟槽 120, 以形成所述第二区内的源漏区， 进而形成夹于各所述栅堆叠结构基体
^J¾_0i第 ϋ村 _ L62 操作 鱼_历 迷—操_ _后形成 i々结构—如一图 20和图 21所示。
其中， 所述第二半导体层 162可以为 Si或 Si: C ( C的原子数百 分比可以为 0-2%， 如 0.5%、 1%或 1.5%, C的含量可以根据工艺需要 灵活调节， 本文件内未作特殊说明处， C的原子数百分比均与此相同， 不再赘述） ； 可使所述第二半导体层 162对所述 NMOS器件的沟道区 提供拉应力， 利于改善 CMOS器件性能。 所述第二半导体层 162可以 所述硅村底为籽晶采用外延法形成。 与所述第一半导体层 160 类似， 所述第二半导体层 162 也可以是已完成离子掺杂的半导体材料， 也可 以在生成所述第二半导体层 162后， 再经由离子注入工艺形成， 可采 用任何传统的离子注入工艺执行所述离子掺杂操作， 不再赘述。 在其 他实施例中， 也可以采用传统方法直接向所述硅村底内执行离子注入 操作， 以形成所述源漏区。
在本实施例中，所述第二层间材料层 162与所述第二半导体层 142 材料相同， 所述第二层间材料层 162可以所述第二半导体层 142为籽 晶采用外延法形成。
特别地， 所述第一层间材料层 160和所述第二层间材料层 162材 质可相同，如，可为 Si、 8^)4 065(或 8^ C; 利于对 PMOS器件和 NMOS 器件同步执行后续操作。
随后， 如图 22至图 24所示， 平坦化获得上述结构的所述硅衬底， 并去除所述阻挡层 1042, 可采用化学机械研磨 （CMP ) 工艺执行所述 平坦化操作； 在采用后栅工艺时， 可在此步骤中去除伪栅 （材质为多 晶硅或非晶硅的栅极基体） 而形成替代栅（可为层叠金属层） ； 继而， 如图 25至图 27所示， 确定隔离区区域并去除位于所述区域内的各所 述层间材料层和部分高度的所述硅衬底， 以形成凹槽 180; 可采用刻蚀 工艺形成所述凹槽 180。 可见， 由于所述栅堆叠结构基体和所述层间材 料层 160和 162、 半导体层 140和 142以及硅衬底的材料不同， 在形成 所述凹槽 180后，所述栅堆叠结构基体中的所述栅极基体 104(如金属） 只有部分材料被去除 （采用后栅工艺时， 由于所述栅极基体 104 为多 晶硅或非晶硅， 材质与所述硅衬底材料近似相同， 被去除部分材料的 程度稍重）， 形成凹陷 182, 而如图 28和图 29所示， 在所述隔离区内， 位于所述栅堆叠结构基体之下的硅衬底 （如图中虚框标示） 并未被去 除， 由此， 本应由所述隔离区隔离的器件之间可经此部分未被去除的 硅村底而导通； 为实现隔离效果， 需如图 30所示， 去除位于所述区域 内承载所述栅堆叠结构基体的所述硅村底。 可以采用各向同性刻蚀工 艺 （如湿法刻蚀工艺， 应用此工艺时， 位于所述隔离区内承载所述栅 堆叠结构基体的所述硅衬底被去除， 并形成孔洞， 所述孔洞在后续以 绝缘材料填充所述凹槽 180 时被填充） 或钝化工艺 （如氧化工艺， 应 用此工艺时， 位于所述隔离区内承载所述栅堆叠结构基体的所述硅衬 N2011/000684 底被钝化为绝缘材料） 执行所述去除操作。 经历所述去除操作后， 虛 框所示区域被刻掉或被钝化为绝缘材料。 再后， 如图 31至图 33所示， 以绝缘材料 （可为氧化硅） 填充所述凹槽 180, 形成隔离区 184。 采用 后栅工艺时， 也可在形成所述隔离区 184后， 形成替代栅。 随后， 继 续在所述第一层间材料层 160和所述第二层间材料层 162上形成金属 层， 再执行热处理操作（如快速热退火） ， 使所述第一层间材料层 160 和所述第二层间材料层 162 形成导电层 （如金属硅化物层） ， 可利用 所述导电层作为接触孔， 利于简化工艺。
最后， 如图 34至图 36所示， 沿第二方向切割所述栅堆叠结构基 体， 以形成栅堆叠结构， 所述第二方向 yy， 异于所述第一方向 （本实 施例中， 所述第二方向垂直于所述第一方向） 。 切割所述栅堆叠结构 基体后形成的缝隙将被后续层间介质层 186材料填充。
上述实施例中，栅极可采用先栅工艺（gate first )或后栅工艺（gate last ) 形成， 所述凹槽 180可形成于形成所述栅堆叠结构基体之后、 切 割所述栅堆叠结构基体之前 （本实施例） ； 也可形成于切割所述栅堆 叠结构基体之后 （其他实施例） ， 此时， 切割所述栅堆叠结构基体之 后形成的缝隙需在形成所述凹槽 180之前填充绝缘材料， 以防止暴露 的所述硅衬底被去除 （即， 防止暴露的所述硅衬底形成绝缘介质， 继 而改变器件性能） 。 在采用后栅工艺形成所述栅极时， 所述凹槽 180 既可形成于伪栅之后、 替代栅之前 （本实施例） ， 也可以形成于替代 栅之后、 切割所述栅堆叠结构基体之前 （其他实施例） 。
此外， 利用现行工艺形成栅堆叠结构后， 再形成所述隔离区， 可 构成本发明提供的半导体器件的形成方法的第二实施例。 所述方法包 括：
首先， 在硅衬底上形成至少一个栅堆叠结构和夹于各所述栅堆叠 结构之间的层间材料层；
随后， 确定隔离区区域并去除位于所述区域内的所述层间材料层 和部分高度的所述硅衬底， 以形成凹槽；
再后， 去除位于所述区域内承载所述栅堆叠结构的所述硅衬底； 最后， 以绝缘材料填充所述凹槽。
此半导体器件的形成方法的第二实施例相当于， 在上述凹槽形成 于切割所述栅堆叠结构基体之后的实施例中， 不采用先形成所述栅堆 叠结构基体再切割所述栅堆叠结构基体的方式形成所述栅堆叠结构， 而是直接形成所述栅堆叠结构， 再形成所述凹槽， 进而形成所述隔离 区。 利于与现有工艺的兼容。
本发明还提供了一种半导体器件， 如图 35所示， 各所述半导体器 件被隔离区 184隔离， 所述隔离区 184嵌于半导体衬底 100内， 所述 半导体器件包括： 层间材料层和至少一个栅堆叠结构， 所述栅堆叠结 构形成于所述半导体衬底 100 上， 所述栅堆叠结构的部分区域位于所 述隔离区 1 84上； 位于所述隔离区 184上的所述栅堆叠结构的上表面 低于位于所述隔离区 1 84 内的所述栅堆叠结构的上表面； 所述层间材 料层夹于各所述栅堆叠结构之间。
其中， 在位于所述隔离区上的所述栅堆叠结构的上表面上形成有 所述层间材料层。 对于 PMOS器件和 NMOS器件， 所述层间材料层材 质相同。 所述层间材料层为半导体层或导电层。
在本实施例中， 所述衬底为硅衬底， 在其他实施例中， 所述衬底 还可以包括其他化合物半导体， 如碳化硅、 砷化镓、 砷化铟或磷化铟； 此外， 所述衬底优选地包括外延层； 所述衬底也可以包括绝缘体上硅 ( SOI )结构。 所述栅堆叠结构包括栅介质层、 形成于所述栅介质层上 的栅极和环绕所述栅介质层和所述栅极的侧墙。 所述栅介质层可以选 用铪基材料， 如 Hf02、 HfSiO、 HfSiON, HfTaO、 HfTiO或 HfZrO中 的一种或其组合； 所述栅极可为多晶硅层或层叠金属层， 所述层叠金 属层包括功函数金属层、 第一金属层和第二金属层， 所述功函数金属 层可以包括 TiN、 TiAlN、 TaN或 TaAIN中的一种或其组合； 所述第一 金属层和第二金属层可以包括 Al、 Ti、 Ta、 W或 Cu中的一种或其组 合； 所述侧墙可为氮化硅或堆叠的氮化硅 -氧化硅-氮化硅。
对于 PMOS器件， 所述半导体层材料可以为 Si或 Si1-xGex; 选用
Si^Gex时，可使所述半导体层对所述 PMOS器件的沟道区提供压应力， 利于改善 CMOS 器件性能。 对于 NMOS 器件， 所述半导体层可以为 Si或 Si: C; 选用 Si: C时， 可使所述半导体层对所述 NMOS器件的 沟道区提供拉应力， 利于改善 CMOS器件性能。 所述导电层可为金属 硅化物层。
在其他实施例中， 所述第一层间材料层可以为传统的层间介质层， 所述层间介质层可以为掺杂或未掺杂的氧化硅玻璃 （如氟硅玻璃、 硼 硅玻璃、 磷硅玻璃、 硼磷硅玻璃、 碳氧化硅或碳氮氧化硅等） 或者低 介电常数介质材料 （如黑钻石、 coral等） 中的一种或其组合。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的 工艺、 结构、 制造、 物质组成、 手段、 方法及步骤。 根据本发明的公 开内容， 本领域技术人员将容易地理解， 对于目前已存在或者以后即 将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 它们 在执行与本发明描述的对应实施例大体相同的功能或者获得大体相同 的结果时， 依照本发明的教导， 可以对它们进行应用， 而不脱离本发 明所要求保护的范围。

Claims

权 利 要 求
1. 一种半导体器件的形成方法， 其特征在于， 包括：
在半导体衬底上形成至少一个栅堆叠结构和夹于各所述栅堆叠结 构之间的层间材料层；
确定隔离区区域并去除位于所述区域内的所述层间材料层和部分 高度的所述半导体衬底， 以形成凹槽；
去除位于所述区域内承载所述栅堆叠结构的所述半导体村底； 以绝缘材料填充所述凹槽。
2. 根据权利要求 1 所述的方法， 其特征在于： 以各向同性刻蚀工 艺或钝化工艺执行所述去除操作。
3. 根据权利要求 1所述的方法， 其特征在于： 对于 PMOS器件和 NMOS器件， 所述层间材料层材质相同。
4. 根据权利要求 1 所述的方法， 其特征在于： 所述层间材料层为 半导体层。
5. 根据权利要求 4所述的方法， 其特征在于， 还包括：
形成金属层， 所述金属层覆盖所述层间材料层；
执行热处理操作， 使所述层间材料层形成导电层。
6. —种半导体器件的形成方法， 其特征在于， 包括：
在半导体衬底上形成至少一个沿第一方向延伸的栅堆叠结构基体 和夹于各所述栅堆叠结构基体之间的层间材料层；
确定隔离区区域并去除位于所述区域内的所述层间材料层和部分 高度的所述半导体衬底， 以形成凹槽；
去除位于所述区域内承载所述栅堆叠结构基体的所述半导体衬 底；
^ 缘才 i料填^所^槽—；
利用所述栅堆叠结构基体形成栅堆叠结构， 并沿第二方向切割所 述栅堆叠结构， 所述第二方向异于所述第一方向。
7. 根据权利要求 6所述的方法， 其特征在于： 以各向同性刻蚀工 艺或钝化工艺执行所述去除操作。
8. 根据权利要求 6所述的方法， 其特征在于： 对于 PMOS器件和 NMOS器件， 所述层间材料层材料相同。
9. 根据权利要求 6所述的方法， 其特征在于： 所述层间材料层为 半导体层。
10. 根据权利要求 9所述的方法， 其特征在于， 还包括：
形成金属层， 所述金属层覆盖所述层间材料层；
执行热处理操作， 使所述层间材料层形成导电层。
1 1. 一种半导体器件， 各所述半导体器件被隔离区隔离， 所述隔离 区嵌于半导体衬底内， 其特征在于， 所述半导体器件包括： 层间材料 层和至少一个栅堆叠结构， 所述栅堆叠结构形成于所述半导体衬底上， 所述栅堆叠结构的部分区域位于所述隔离区上； 位于所述隔离区上的 所述栅堆叠结构的上表面低于位于所述隔离区内的所述栅堆叠结构的 上表面； 所述层间材料层夹于各所述栅堆叠结构之间。
12. 根据权利要求 1 1所述的半导体器件， 其特征在于： 在位于所 述隔离区上的所述栅堆叠结构的上表面上形成有所述层间材料层。
13. 根据权利要求 11所述的半导体器件，其特征在于：对于 PMOS 器件和 NMOS器件， 所述层间材料层材质相同。
14. 根据权利要求 11所述的半导体器件， 其特征在于： 所述层间 材料层为半导体层或导电层。
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