WO2011159001A1 - Dispositif de mémoire non volatile comprenant une couche de piégeage de charge dans un nanomotif, et son procédé de fabrication - Google Patents

Dispositif de mémoire non volatile comprenant une couche de piégeage de charge dans un nanomotif, et son procédé de fabrication Download PDF

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Publication number
WO2011159001A1
WO2011159001A1 PCT/KR2010/008324 KR2010008324W WO2011159001A1 WO 2011159001 A1 WO2011159001 A1 WO 2011159001A1 KR 2010008324 W KR2010008324 W KR 2010008324W WO 2011159001 A1 WO2011159001 A1 WO 2011159001A1
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layer
charge trapping
trapping layer
nano
pattern
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PCT/KR2010/008324
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English (en)
Korean (ko)
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김태근
안호명
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고려대학교 산학협력단
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Publication of WO2011159001A1 publication Critical patent/WO2011159001A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

Definitions

  • the present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device including a charge trapping layer in which a nanopattern is formed and a method of manufacturing the same.
  • semiconductor memory devices may be classified into volatile memory devices and nonvolatile memory devices.
  • Volatile memory devices such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) are fast memory inputs and outputs, but lose their stored data when power is lost.
  • DRAM Dynamic Random Access Memory
  • SRAM Static Random Access Memory
  • a nonvolatile memory device is a memory device that retains stored data even when power is cut off.
  • Flash memory devices are a type of nonvolatile memory device that can be programmed and erased, and can be programmed and erased electrically (EPROM) and electrically programmable and erased electrically (EEPROM). It is a highly integrated device developed by combining the advantages of Read Only Memory. Flash memory devices are classified into floating gate type flash memory devices and floating trap type flash memory devices according to types of data storage layers constituting a unit cell.
  • a charge trapping flash memory device stores charge in a trap formed in a non-conductive charge trapping layer.
  • the memory cell of the charge trapping memory device has a stacked structure of a gate insulating film formed on a silicon substrate, a silicon nitride film as a charge trapping layer, a blocking insulating film and a conductive film.
  • FIG. 1 is a cross-sectional view of a nonvolatile memory device 10 having a silicon oxide nitride (SONOS) structure according to the prior art.
  • a memory cell of the memory device 10 includes an oxide film 12, a nitride film 13, and an oxide film on a channel region 18 between regions of source / drain 17 formed in a substrate 11.
  • the ONO film 15 made of 14) and the polysilicon 16 are stacked in this order.
  • This memory cell has a single bit structure showing either a logic '0' or a logic '1' state depending on the presence or absence of charge trapped in the nitride film 13 of the ONO film 15.
  • the conventional non-volatile memory device of the conventional SONOS structure is also less than 45 nm. It is being scaled down to the size of.
  • An object of the present invention is to provide a miniaturized nonvolatile memory device and a method of manufacturing the same, while being capable of capturing a charge amount sufficient to secure a memory window margin of a nonvolatile memory device.
  • a nonvolatile memory device of the present invention for solving the above problems is a semiconductor substrate; A tunnel insulating film formed on the semiconductor substrate; A charge trap layer formed on the tunnel insulating layer and having a nano pattern formed on an upper surface thereof; A blocking insulating film formed on the charge trapping layer; And a gate electrode layer formed on the blocking insulating layer.
  • the nano-pattern is preferably an uneven pattern.
  • the blocking insulating layer may be formed of an oxide film
  • the charge trapping layer may be formed of a nitride film.
  • the nonvolatile memory device manufacturing method of the present invention for solving the above problems, (a) forming a tunnel insulating film on a semiconductor substrate; (b) forming a charge trapping layer on the tunnel insulating film; (c) forming a nano pattern on an upper surface of the charge trapping layer; (d) forming a blocking insulating layer on the charge trapping layer in which the nanopattern is formed; And (e) forming a gate electrode layer on the blocking insulating film.
  • a plurality of beads may be disposed on the charge trap layer, and the upper surface of the charge trap layer may be etched using the plurality of beads as an etching mask to form a nano pattern.
  • step (c) coating a plurality of beads in a single layer on the charge trapping layer; (c2) etching the plurality of beads to adjust the size of the beads; (c3) etching the exposed regions between the beads in the charge trap layer to form a nano pattern; And (c4) removing the beads remaining in the charge trapping layer.
  • the nano-pattern formed on the nano stamp may be transferred to the charge trapping layer using a nanoimprinting method to form a nano-pattern on the charge trapping layer.
  • the method may include removing the resist layer.
  • the nano-pattern is preferably an uneven pattern.
  • the blocking insulating layer may be formed of an oxide film
  • the charge trapping layer may be formed of a nitride film.
  • the present invention reduces the amount of charge trapped in the charge trapping layer as the nonvolatile memory device of the conventional SONOS structure becomes smaller, thereby reducing the memory window margin for recognizing the program state and the program erase state of the memory device.
  • a nano pattern such as an uneven pattern is formed on the junction surface of the charge trapping layer and the blocking insulating layer, which are mainly charge trapping regions, to further expand the space in which the charge is trapped.
  • the present invention extends the interface with the blocking insulating layer, which is a region where charge is trapped in the charge trapping layer, by adding only a process of forming a nanopattern in the conventional SONOS process without adding a complicated process, thereby increasing charge per unit length. Since the area to be captured can be increased, a large memory window margin can be ensured even in a micro memory device of 45 nm or less, thereby providing a more reliable nonvolatile memory device.
  • FIG. 1 is a cross-sectional view of a nonvolatile memory device having a silicon oxide nitride (SONOS) structure according to the prior art.
  • SONOS silicon oxide nitride
  • FIG. 2 is a diagram illustrating a structure of a nonvolatile memory device including a charge trap layer in which a nanopattern is formed according to a preferred embodiment of the present invention.
  • 3A to 3D illustrate a method of manufacturing a nonvolatile memory device including a charge trapping layer having a nano pattern formed thereon according to an exemplary embodiment of the present invention.
  • 4A to 4C illustrate a process of forming a nano pattern on a charge trap layer using polystyrene beads.
  • 5A to 5D illustrate a method of forming a nanopattern on a charge trapping layer using a nanoimprinting method according to another exemplary embodiment of the present invention.
  • FIG. 2 is a diagram illustrating a structure of a nonvolatile memory device including a charge trap layer 230 having a nano pattern formed thereon according to an exemplary embodiment of the present invention.
  • FIG. 2 a structure of a nonvolatile memory device including a charge trap layer 230 in which a nanopattern is formed according to an exemplary embodiment of the present invention will be described.
  • a source region 212 and a drain region 214 are formed on a semiconductor substrate 210, and a channel region is formed between the source region 212 and the drain region 214.
  • the memory layer in which the tunnel insulation layer 220, the charge trapping layer 230, and the blocking insulation layer 240 are sequentially formed is formed on the channel region, and the gate electrode layer 250 is formed on the blocking insulation layer 240.
  • An insulating film spacer 260 is formed around the memory device.
  • a nano pattern having a concave-convex structure is formed on a contact surface with the blocking insulating layer 240.
  • the nano-pattern may be a concave-convex pattern regularly formed as shown in FIG. 2, or an arbitrary pattern (roughness) may be formed simply to increase the surface area at the interface with the blocking insulating film 240.
  • a region where charge is mainly captured is a region directly below the interface that is in contact with the blocking insulating layer 240 in the charge trapping layer 230 formed of a silicon nitride film.
  • the length of the interface between the charge trapping layer 230 and the blocking insulating film 240 becomes shorter, resulting in a decrease in the amount of accumulated charge.
  • the present invention forms a nano-pattern on the charge trapping layer 230 to extend the length of the interface between the charge trapping layer 230 and the blocking insulating layer 240, whereby charge is trapped.
  • 3A to 3D are diagrams illustrating a method of manufacturing a nonvolatile memory device including a charge trapping layer 230 having a nano pattern formed thereon according to an exemplary embodiment of the present invention.
  • the tunnel insulating layer 220 and the charge trapping layer 230 are sequentially formed on the semiconductor substrate 210. .
  • the tunnel insulating film 220 may be formed of a silicon oxide film (SiO 2) as an oxide film formed on the channel region with a thickness of several nm through a thermal oxidation process or a known thin film deposition process. As the thickness of the tunnel insulating layer 220 is thinner, a lower program voltage may be applied to the gate electrode layer 250, and the programming and erasing can be performed quickly, and there is an advantage in that the program and erasing operation is more successful. There is a low problem. Therefore, the thickness of the tunnel insulating film 220 is preferably selected as thin as possible at an appropriate level in accordance with variables such as program and erase voltage and speed, in a preferred embodiment of the present invention is formed to a thickness of 1 to 10 nm.
  • SiO 2 silicon oxide film
  • the charge trap layer 230 is formed on the tunnel insulating film 220 to a thickness of 3 to 150nm.
  • a silicon nitride film Si 3 N 4
  • the charge trapping layer 230 is not only a nitride film but all materials capable of storing charge Can be used.
  • the charge trapping layer 230 may be formed of any one of a material having a high-k and an amorphous polysilicon material.
  • the charge trapping layer 230 may be formed of a metal such as tungsten, molybdenum, cobalt, nickel, platinum, rhodium, palladium, and iridium, a mixture thereof, or an alloy thereof.
  • the charge trapping layer 230 may be formed of silicon, germanium, a mixture of silicon and germanium, a group III-V compound (combination of Al, Ga, In of group III and P, As, Sb of group V), or group II-VI.
  • the charge trapping layer 230 may be formed of an insulator having a high trapping density against charges such as aluminum oxide (Al 2 O 3), hafnium oxide (HfO), hafnium aluminum oxide (HfAlO), and hafnium silicon oxide (HfSio). have.
  • a nano pattern is formed on the charge trap layer 230.
  • various methods may be applied.
  • the nano-pattern on the charge trapping layer 230 may be applied by various methods such as a method using polystyrene beads, a photolithography method, a laser holography method, a method using nanoimprinting, and an AAO mask method.
  • an uneven pattern can be formed.
  • photolithography method, laser holography method, and AAO mask method are generally used to form irregularities on the surface of the semiconductor layer. Therefore, the method will be described in detail, and a method using polystyrene beads and nanoimprinting will be described. The method of use will be described later with reference to FIGS. 4A to 5D.
  • the blocking insulating layer 240 is formed on the charge trapping layer 230, the gate electrode layer 250 is formed thereon, and the gate electrode layer is formed on the charge trapping layer 230.
  • the hard mask film pattern 300 is formed in the region where the memory device is to be formed.
  • the blocking insulating film 240 is preferably formed to be at least thicker than the tunnel insulating film 220 in order to prevent the charge stored in the charge trapping layer 230 from leaking into the gate electrode layer 250.
  • the insulating film 240 is preferably formed to a thickness of 5 to 160nm.
  • the blocking leading edge film may be formed using materials that may be used to form the tunnel insulating film 220 described above.
  • the gate electrode layer 250 may be formed of any conductive material typically used as a gate electrode, such as polysilicon, a metal, or a polyside structure in which metal-silicide is formed on polysilicon.
  • a conductive material typically used as a gate electrode such as polysilicon, a metal, or a polyside structure in which metal-silicide is formed on polysilicon.
  • the gate electrode layer 250 is formed of a metal or polyside structure having better conductivity than polysilicon in consideration of increase in resistance.
  • the hard mask layer patterns 580 are formed in the region where the memory device is to be formed, and the gate electrode layer is exposed until the semiconductor substrate 210 is exposed using the hard mask layer 580 as an etching mask. 250, the blocking insulating film 240, the charge trapping layer 230, and the tunnel insulating film 220 are etched.
  • the separation distance between the source region 212 and the drain region 214 is several tens of nm, and thus the length of the memory element formed over the channel region located between the source region 212 and the drain region 214 is Tens of nm. Therefore, the length of the hard mask film patterns is also determined according to the length of the memory element.
  • a source drain ion implantation process is performed to form a source region 212 and a drain region 214 on the semiconductor substrate 210, and an insulating film spacer 260 is formed.
  • the nonvolatile memory device of the present invention as shown in Fig. 2 is completed.
  • 4A to 4C illustrate a process of forming the uneven nano pattern on the charge trap layer 230 using polystyrene beads.
  • a plurality of polystyrene beads having a size of 10nm ⁇ 100nm is arranged in a single layer using a method such as spin coating.
  • a RIE etching process is applied to the polystyrene beads to reduce the size of the beads formed on the charge trapping layer 230.
  • the size of the polystyrene beads determines the width of the nanopattern, and the size of these polystyrene beads can be freely controlled by setting the RIE etching process conditions.
  • the charge trapping layer 230 exposed between the polystyrene beads is etched, thereby forming a charge trapping layer ( 230 to form a nano-pattern.
  • the nano-pattern is formed on the charge trapping layer 230, the polystyrene beads remaining on the charge trapping layer 230 are removed by a wet etching method, thereby removing the uneven-shaped nanopattern as shown in FIG. 3B. Over 230.
  • 5A to 5D illustrate a method of forming a nanopattern on the charge trapping layer 230 using a nanoimprinting method according to another exemplary embodiment of the present invention.
  • the tunnel insulation layer 220 and the charge trapping layer 230 are sequentially formed on the semiconductor substrate 210 in the same manner as in FIG. 3A, and the pattern is formed using the nano stamp 500 thereon.
  • the stamp 500 to transfer the pattern to the resist layer 510 is aligned with the semiconductor substrate 210. .
  • the surface of the substrate 210 is heated to a high temperature (temperature above the glass conduction temperature; heated to about 200 ° C. in a preferred embodiment of the present invention), and then the nano stamp 500 is resisted.
  • the uneven patterns 502 and 504 of the nano stamp 500 are transferred to the resist layer 510 by pressing the layer 510 and cooling the temperature of the semiconductor substrate 210 while the pressure is maintained. At this time, a pressure of about 0.2 m pascal is applied from the stamp 500 to the resist layer 510.
  • the resist layer 510 may be stamped 500.
  • the pattern formed in Fig. 2) is transferred as it is.
  • a part of the charge trapping layer 230 formed under the recessed portion of the resist layer 510 is etched to react until the uneven nano pattern is formed in the charge trapping layer 230.
  • RIE ion etching process
  • wet etching is performed using a material corresponding to the resist forming material to remove the resist layer 510 described above with reference to FIG. 3B.
  • a nano pattern having an uneven shape may be formed on the charge trap layer 230.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
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Abstract

L'invention concerne un dispositif de mémoire non volatile de type SONOS et son procédé de fabrication. Afin de résoudre les problèmes liés aux dispositifs de mémoire non volatile de type SONOS plus petits de l'état de la technique, tels qu'une baisse de la quantité de charge piégée dans une couche de piégeage de charge qui se traduit par des difficultés pour fixer une marge de fenêtre de mémoire permettant de reconnaître un état d'un programme du dispositif de mémoire et un état d'effacement de ce programme, un nanomotif, tel qu'un motif concavo-convexe est formé sur la surface de jonction entre la couche de piégeage de charge et un film isolant bloquant, parmi d'autres zones de la couche de piégeage de charge, sur laquelle les charges sont principalement piégées. L'invention consiste à ajouter uniquement un procédé de formation de nanomotif au procédé SONOS classique, sans faire appel à un procédé compliqué supplémentaire séparé, de façon à élargir l'interface entre la couche de piégeage de charge et le film isolant bloquant, laquelle correspond à une zone dans laquelle les charges sont piégées parmi d'autres zones de la couche de piégeage de charge. Ainsi, il est possible d'augmenter une zone de piégeage de charge par unité de longueur, et une marge de fenêtre de mémoire suffisamment importante peut ainsi être assurée même dans un dispositif de mémoire ultra-petit inférieur à 45 nm, ce qui permet d'obtenir des dispositifs de mémoire non volatile ayant une fiabilité plus élevée.
PCT/KR2010/008324 2010-06-14 2010-11-24 Dispositif de mémoire non volatile comprenant une couche de piégeage de charge dans un nanomotif, et son procédé de fabrication WO2011159001A1 (fr)

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KR10-2010-0056106 2010-06-14
KR1020100056106A KR101133149B1 (ko) 2010-06-14 2010-06-14 나노 패턴이 형성된 전하 포획층을 포함하는 비휘발성 메모리 소자 및 그 제조하는 방법

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US11121098B2 (en) 2015-10-19 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Trap layer substrate stacking technique to improve performance for RF devices
US11121100B2 (en) 2015-10-19 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Trap layer substrate stacking technique to improve performance for RF devices

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