KR101133149B1 - 나노 패턴이 형성된 전하 포획층을 포함하는 비휘발성 메모리 소자 및 그 제조하는 방법 - Google Patents

나노 패턴이 형성된 전하 포획층을 포함하는 비휘발성 메모리 소자 및 그 제조하는 방법 Download PDF

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KR101133149B1
KR101133149B1 KR1020100056106A KR20100056106A KR101133149B1 KR 101133149 B1 KR101133149 B1 KR 101133149B1 KR 1020100056106 A KR1020100056106 A KR 1020100056106A KR 20100056106 A KR20100056106 A KR 20100056106A KR 101133149 B1 KR101133149 B1 KR 101133149B1
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South Korea
Prior art keywords
layer
charge trapping
trapping layer
memory device
charge
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KR1020100056106A
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English (en)
Korean (ko)
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KR20110136238A (ko
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김태근
안호명
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고려대학교 산학협력단
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Priority to KR1020100056106A priority Critical patent/KR101133149B1/ko
Priority to PCT/KR2010/008324 priority patent/WO2011159001A1/fr
Publication of KR20110136238A publication Critical patent/KR20110136238A/ko
Application granted granted Critical
Publication of KR101133149B1 publication Critical patent/KR101133149B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
KR1020100056106A 2010-06-14 2010-06-14 나노 패턴이 형성된 전하 포획층을 포함하는 비휘발성 메모리 소자 및 그 제조하는 방법 KR101133149B1 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020100056106A KR101133149B1 (ko) 2010-06-14 2010-06-14 나노 패턴이 형성된 전하 포획층을 포함하는 비휘발성 메모리 소자 및 그 제조하는 방법
PCT/KR2010/008324 WO2011159001A1 (fr) 2010-06-14 2010-11-24 Dispositif de mémoire non volatile comprenant une couche de piégeage de charge dans un nanomotif, et son procédé de fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100056106A KR101133149B1 (ko) 2010-06-14 2010-06-14 나노 패턴이 형성된 전하 포획층을 포함하는 비휘발성 메모리 소자 및 그 제조하는 방법

Publications (2)

Publication Number Publication Date
KR20110136238A KR20110136238A (ko) 2011-12-21
KR101133149B1 true KR101133149B1 (ko) 2012-07-11

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KR1020100056106A KR101133149B1 (ko) 2010-06-14 2010-06-14 나노 패턴이 형성된 전하 포획층을 포함하는 비휘발성 메모리 소자 및 그 제조하는 방법

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KR (1) KR101133149B1 (fr)
WO (1) WO2011159001A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9761546B2 (en) 2015-10-19 2017-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Trap layer substrate stacking technique to improve performance for RF devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100550452B1 (ko) 2004-10-19 2006-02-08 한국과학기술원 정배열된 금속 나노점을 이용한 다중비트 비휘발성 메모리소자 및 그 제조 방법
US20080268288A1 (en) 2005-05-10 2008-10-30 The Regents Of The University Of California, A Corporation Of California Spinodally Patterned Nanostructures

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20060005177A (ko) * 2004-07-12 2006-01-17 매그나칩 반도체 유한회사 비휘발성 메모리 소자의 게이트 전극 및 그 형성방법
KR20080112609A (ko) * 2007-06-21 2008-12-26 삼성전자주식회사 저항성 메모리 소자 및 그 제조 방법
KR100890210B1 (ko) * 2007-08-29 2009-03-25 고려대학교 산학협력단 비휘발성 메모리 소자 및 이를 제조하는 방법
KR100871605B1 (ko) * 2007-08-30 2008-12-02 고려대학교 산학협력단 멀티 비트 프로그램이 가능한 비휘발성 메모리 소자 및이를 제조하는 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100550452B1 (ko) 2004-10-19 2006-02-08 한국과학기술원 정배열된 금속 나노점을 이용한 다중비트 비휘발성 메모리소자 및 그 제조 방법
US20080268288A1 (en) 2005-05-10 2008-10-30 The Regents Of The University Of California, A Corporation Of California Spinodally Patterned Nanostructures

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Publication number Publication date
KR20110136238A (ko) 2011-12-21
WO2011159001A1 (fr) 2011-12-22

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