WO2011152424A1 - 半導体モジュールおよび半導体モジュールの製造方法 - Google Patents

半導体モジュールおよび半導体モジュールの製造方法 Download PDF

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Publication number
WO2011152424A1
WO2011152424A1 PCT/JP2011/062536 JP2011062536W WO2011152424A1 WO 2011152424 A1 WO2011152424 A1 WO 2011152424A1 JP 2011062536 W JP2011062536 W JP 2011062536W WO 2011152424 A1 WO2011152424 A1 WO 2011152424A1
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Prior art keywords
layer
electrode
insulating resin
semiconductor module
wiring layer
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PCT/JP2011/062536
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English (en)
French (fr)
Inventor
康行 柳瀬
臼井　良輔
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三洋電機株式会社
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Publication of WO2011152424A1 publication Critical patent/WO2011152424A1/ja
Priority to US13/691,139 priority Critical patent/US20130181344A1/en

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    • H01L2224/81895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Definitions

  • the present invention relates to a semiconductor module in which a semiconductor element is mounted on an element mounting substrate and a method for manufacturing the semiconductor module.
  • the wiring board constituting the semiconductor module that is, the wiring layer in the element mounting board
  • the wiring board is becoming denser and thinner. For this reason, wrinkles are generated in the metal plate for forming the wiring layer in the course of the manufacturing process, which tends to cause a reduction in manufacturing yield, and handling of the wiring layer during processing and pressure bonding of the element mounting substrate to the semiconductor element Handling was difficult.
  • the present invention has been made in view of these problems, and an object thereof is to provide a technique capable of facilitating the handling of components when manufacturing a semiconductor module and simplifying the manufacturing process of the semiconductor module. .
  • An aspect of the present invention is a method for manufacturing a semiconductor module.
  • the manufacturing method of the semiconductor module includes a step of selectively removing a metal plate held on a base material to form a wiring layer provided with a substrate electrode, and a top surface of the substrate electrode itself or a top portion of the substrate electrode. Forming an insulating resin layer on the base material so that the metal layer provided on the surface is exposed, and forming an element mounting substrate including a wiring layer, a substrate electrode, and an insulating resin layer, and In the step of forming the wiring layer, the wiring layer includes a step of tapering such that the end surface thereof enters the inside of the wiring layer forming region as it approaches the semiconductor element.
  • the manufacturing method of the semiconductor module of this aspect since the formation process of the substrate electrode and the wiring layer is performed in a state where the metal plate is supported by the base material, the handling of the metal plate is easy. The possibility of damaging the substrate electrode can be reduced. As a result, the manufacturing yield of the semiconductor module can be improved. Further, in the step of forming the wiring layer, since the end surface of the wiring layer is tapered so as to enter the inside of the wiring layer forming region as it approaches the semiconductor element, the insulating resin formed on the base material There is no possibility that a cavity where the insulating resin does not spread is generated in the portion between the wiring layers formed by the layers.
  • the substrate electrode may be a protruding electrode formed integrally with the wiring layer by selectively removing the metal plate.
  • the base material is transparent, and when the element mounting substrate is pressure-bonded to the semiconductor element, the position of the semiconductor element may be confirmed through the base material, and the element mounting substrate and the semiconductor element may be aligned. Also, a step of pressure-bonding an element mounting substrate to a semiconductor element, removing the base material, removing an insulating resin layer, and forming another insulating resin layer having a function different from that of the insulating resin layer instead of the insulating resin layer May be provided.
  • the semiconductor module includes an insulating resin layer, a wiring layer provided on one main surface of the insulating resin layer, a protruding electrode protruding from the wiring layer toward the insulating resin layer, and an element electrode facing the protruding electrode.
  • the end surface of the wiring layer is tapered so as to enter the inside of the wiring layer forming region as it approaches the semiconductor element, and the protruding electrode penetrates the insulating resin layer. The electrode is electrically connected.
  • the handling of the metal plate for forming the wiring layer can be facilitated, and the manufacturing process of the semiconductor module can be simplified.
  • FIG. 1 is a schematic cross-sectional view showing a configuration of a semiconductor module according to a first embodiment. It is process sectional drawing which shows the 1st manufacturing method of a semiconductor module. It is process sectional drawing which shows the 1st manufacturing method of a semiconductor module. It is process sectional drawing which shows the 1st manufacturing method of a semiconductor module. It is process sectional drawing which shows the 1st manufacturing method of a semiconductor module. It is process sectional drawing which shows the 1st manufacturing method of a semiconductor module. It is process sectional drawing which shows the 1st manufacturing method of a semiconductor module. It is process sectional drawing which shows the 1st manufacturing method of a semiconductor module. It is process sectional drawing which shows the 2nd manufacturing method of a semiconductor module. It is process sectional drawing which shows the 3rd manufacturing method of a semiconductor module.
  • FIG. 10A is a process cross-sectional view illustrating the third manufacturing method of the semiconductor module.
  • FIG. 10B is a schematic cross-sectional view showing the configuration of the semiconductor module according to the second embodiment.
  • FIG. 11A is a process cross-sectional view illustrating the fourth manufacturing method of the semiconductor module.
  • FIG. 11B is a schematic cross-sectional view showing the configuration of the semiconductor module according to the third embodiment.
  • FIG. 12 is a cross-sectional view showing the structure of a conventional solar cell.
  • FIG. 13 is a diagram showing the structure of the solar cell according to the embodiment.
  • FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor module 10 according to the first embodiment.
  • the semiconductor module 10 includes an element mounting substrate 12 and a semiconductor element 100 bonded to the element mounting substrate 12.
  • the element mounting substrate 12 is electrically connected to the insulating resin layer 20 formed of an insulating resin, the wiring layer 30 provided on one main surface of the insulating resin layer 20, and the wiring layer 30.
  • a plurality of protruding electrodes 32 protruding from the layer 30 to the insulating resin layer 20 side are provided as a main configuration.
  • the material constituting the insulating resin layer 20 examples include thermosetting resins such as melamine derivatives such as BT resin, liquid crystal polymers, epoxy resins, PPE resins, polyimide resins, fluororesins, phenol resins, and polyamide bismaleimides.
  • thermosetting resins such as melamine derivatives such as BT resin, liquid crystal polymers, epoxy resins, PPE resins, polyimide resins, fluororesins, phenol resins, and polyamide bismaleimides.
  • the insulating resin layer 20 has high thermal conductivity.
  • the insulating resin layer 20 contains silver, bismuth, copper, aluminum, magnesium, tin, zinc, an alloy thereof, alumina, or the like as a high thermal conductive filler.
  • the wiring layer 30 is provided on one main surface of the insulating resin layer 20, and is formed of a conductive material, preferably rolled metal or electrolytic foil, and further rolled copper or electrolytic copper foil.
  • the wiring layer 30 has a plurality of protruding electrodes 32 protruding from the insulating resin layer 20 side.
  • the wiring layer 30 and the protruding electrode 32 are integrally formed.
  • the present invention is not particularly limited to this.
  • An end surface E of the wiring layer 30 is in contact with the insulating resin layer 20.
  • the end surface E of the wiring layer 30 has a taper shape that enters the inside of the formation region of the wiring layer 30 as the semiconductor element 100 is approached. Due to this shape, unlike the case of a taper shape in which the end face E of the wiring layer 30 protrudes to the outside of the formation region of the wiring layer 30 as it approaches the semiconductor element 100, a solder ball 80, which will be described later, is formed. Therefore, an external connection electrode having a large area connected to the wiring layer can be formed. In addition, since the contact area of the external connection electrode with the wiring layer is large, heat generated from the semiconductor element can be efficiently released from the external connection electrode, and the adhesion between the wiring layer and the external connection electrode can be improved. it can.
  • the protruding electrode 32 has, for example, a round shape in a plan view, and includes a side surface formed so that the diameter becomes narrower toward the top.
  • the side surface may be inclined in the same direction as the inclination direction of the end surface E of the wiring layer 30. If it does so, there will be no bottleneck (location which becomes resistance) in the diffusion path of the heat which occurs from a semiconductor element, and it can radiate heat effectively.
  • the shape of the protruding electrode 32 is not particularly limited, and may be, for example, a cylindrical shape having a predetermined diameter. Further, it may be a polygon such as a rectangle in plan view.
  • the Au / Ni layer 34 is provided on the top surface and the side surface of the protruding electrode 32.
  • the Au / Ni layer 34 includes an Au layer serving as an exposed surface, and a Ni layer interposed between the Au layer and the top surface of the protruding electrode 32.
  • a protective layer 70 is provided on the main surface of the wiring layer 30 opposite to the insulating resin layer 20 to prevent the wiring layer 30 from being oxidized.
  • the protective layer 70 include a solder resist layer.
  • An opening 72 is formed in a predetermined region of the protective layer 70, and a part of the wiring layer 30 is exposed through the opening 72.
  • Solder balls 80 as external connection electrodes are formed in the openings 72, and the solder balls 80 and the wiring layer 30 are electrically connected.
  • a position where the solder ball 80 is formed, that is, a region where the opening 72 is formed is, for example, an end portion that is routed by rewiring (wiring layer 30).
  • the semiconductor element 100 includes a semiconductor substrate 50, an element electrode 52, an Au / Ni layer 54, and a protective layer 56.
  • An element electrode 52, an Au / Ni layer 54, and a protective layer 56 are formed on one main surface of the semiconductor substrate 50.
  • the semiconductor substrate 50 is a silicon substrate such as a P-type silicon substrate.
  • a predetermined integrated circuit (not shown) and an element electrode 52 located on the outer peripheral edge thereof are formed on one main surface of the semiconductor substrate 50.
  • a metal such as aluminum or copper is employed as the material of the element electrode 52.
  • An insulating protective layer 56 for protecting the semiconductor substrate 50 is formed on the main surface of the semiconductor substrate 50 excluding the element electrodes 52.
  • a silicon oxide film (SiO2), a silicon nitride film (SiN), polyimide (PI), or the like is employed as the protective layer 56. Further, an Au / Ni layer 54 is formed on the element electrode 52 so that the Au layer becomes an exposed surface.
  • the gold of the Au / Ni layer 34 provided on the top surface of the bump electrode 32 and the gold of the Au / Ni layer 54 provided on the surface of the element electrode 52 are joined by gold-gold bonding.
  • a corresponding element electrode 52 is electrically connected. Note that the gold / gold bonding between the Au / Ni layer 34 and the Au / Ni layer 54 contributes to the improvement of the reliability of the electrical connection between the protruding electrode 32 and the corresponding element electrode 52. Yes.
  • the insulating resin layer 20 between the wiring layer 30 and the semiconductor element 100 has a tapered shape of the wiring layer 30. Since the insulating resin layer 20 is filled in every corner, the adhesiveness between the insulating resin layer 20 and the wiring layer 30 and the insulating resin layer 20 and the protective layer 70 are It is possible to improve the adhesion.
  • a copper plate 200 is prepared as a metal plate having a thickness equivalent to the sum of the height of the protruding electrode 32 and the thickness of the wiring layer 30 as shown in FIG.
  • the thickness of the copper plate 200 is, for example, 40 ⁇ m.
  • rolled copper made of rolled copper or electrolytic copper foil is employed as the copper plate 200.
  • the copper plate 200 is attached to a base material 300 as a support member using an adhesive layer 310.
  • the substrate 300 is preferably transparent, and a glass substrate or a PET film is suitable.
  • a resist 202 is selected by a lithography method in accordance with a pattern corresponding to the formation planned region of the protruding electrode 32 shown in FIG. Form. Specifically, a resist film having a predetermined film thickness is attached to the copper plate 200 using a laminator, exposed using a photomask having a pattern of the protruding electrodes 32, and then developed to form a resist on the copper plate 200. 202 is selectively formed. In order to improve the adhesion to the resist, it is desirable to perform pretreatment such as polishing and cleaning on the surface of the copper plate 200 as needed before laminating the resist film.
  • a bump electrode having a predetermined pattern protruding from the surface S of the copper plate 200 by performing a wet etching process using a chemical solution such as a ferric chloride solution using the resist 202 as a mask. 32 is formed.
  • the protruding electrode 32 is formed to have a tapered side surface portion whose diameter (dimension) becomes narrower as it approaches the tip portion.
  • the height of the protruding electrode 32 is 20 ⁇ m, for example.
  • the resist 202 and the resist protective film are stripped using a stripping agent.
  • the bump electrode 32 is integrally formed on the copper plate 200.
  • the protruding electrode 32 is an example of a “substrate electrode” that is an electrode on the element mounting substrate side.
  • a resist 204 having an opening through which the protruding electrode 32 is exposed is selectively formed by a lithography method. Specifically, a resist film having a predetermined thickness is attached to the copper plate 200 using a laminator, and exposure is performed using a photomask having a pattern that masks the opening corresponding to the protruding electrode 32, followed by development. As a result, a resist 204 is selectively formed on the copper plate 200.
  • an Au / Ni layer 34 is formed on the top and side surfaces of the protruding electrode 32 exposed in the opening provided in the resist 204 by electrolytic plating or electroless plating. .
  • the Au layer becomes an exposed surface, and the Ni layer is interposed between the Au layer and the top surface of the protruding electrode 32.
  • the Au / Ni layer 34 for example, the Au layer has a thickness of 0.25 ⁇ m, and the Ni layer has a thickness of 1 to 3 ⁇ m.
  • a metal layer may be formed on the top surface and the side surface of the bump electrode 32 using a conductive paste such as a gold paste, for example.
  • a resist 206 corresponding to the wiring layer formation region is selectively formed by lithography. Specifically, a resist film having a predetermined thickness is attached to the copper plate 200 using a laminator apparatus, exposed using a photomask having a pattern corresponding to the wiring layer formation region, and developed, thereby developing the copper plate 200. A resist 206 is selectively formed thereon.
  • the copper plate 200 is processed into a predetermined wiring pattern by performing a wet etching process using a chemical solution such as a ferric chloride solution using the resist 206 as a mask to form a wiring layer.
  • (Rewiring) 30 is formed.
  • the wiring layer 30 in which the predetermined protruding electrode 32 is integrally provided is formed.
  • the protruding electrode 32 and the wiring layer 30 are continuously formed of the same material.
  • the thickness of the wiring layer 30 is 20 ⁇ m.
  • the insulating resin layer 20 is laminated on the wiring layer 30, the protruding electrode 32, and the adhesive layer 310 using a roll laminator or a hot press machine.
  • a thermosetting epoxy-based adhesive resin film is used as the insulating resin layer 20 to be laminated.
  • the insulating resin layer 20 to be laminated may have a thickness sufficient to cover the Au / Ni layer 34 formed on the top surface of the protruding electrode 32.
  • the temperature at which the epoxy adhesive resin film is laminated is preferably a temperature at which the epoxy adhesive resin film is not completely cured (100 ° C. or less).
  • the Au / Ni layer 34 provided on the top surface of the bump electrode 32 is exposed and the top surface of the bump electrode 32 is exposed using O 2 plasma etching or polishing treatment.
  • the insulating resin layer 20 is thinned so that the exposed surface of the insulating resin layer 20 is flush. Thereby, the element mounting substrate 12 including the wiring layer 30, the protruding electrode 32, and the insulating resin layer 20 is formed.
  • a semiconductor substrate 50 having an element electrode 52, an Au / Ni layer 54, and a protective layer 56 formed on one main surface is prepared.
  • the semiconductor substrate 50 such as a P-type silicon substrate is subjected to one main process using a semiconductor manufacturing process in which a well-known lithography technique, etching technique, ion implantation technique, film forming technique, heat treatment technique, and the like are combined.
  • a predetermined integrated circuit is formed on the surface and an element electrode 52 is formed on the outer peripheral edge thereof.
  • a metal such as aluminum or copper is employed as the material of the element electrode 52.
  • an insulating protective layer 56 for protecting the semiconductor substrate 50 is formed on the main surface of the semiconductor substrate 50 excluding these element electrodes 52.
  • a silicon oxide film (SiO2), a silicon nitride film (SiN), polyimide (PI), or the like is employed as the protective layer 56.
  • an Au / Ni layer 54 is formed on the element electrode 52 so that the Au layer becomes an exposed surface.
  • the layer configuration and formation method of the Au / Ni layer 54 are the same as those of the Au / Ni layer 34.
  • electrolytic plating is performed in the opening. Alternatively, it can be formed by performing electroless plating.
  • the Au / Ni layer 54 provided on the element electrode 52 and the Au / Ni layer provided on the top surface of the protruding electrode 32 corresponding to the Au / Ni layer 54. 34 is aligned, and then the element mounting substrate 12 and the semiconductor element 100 are bonded together using a press and temporarily bonded.
  • the bonding time and pressure when the element mounting substrate 12 and the semiconductor element 100 are bonded in this step are, for example, 1 MPa for 3 minutes, respectively.
  • the wiring layer 30 has already been patterned, and the semiconductor substrate 50 can be viewed through the base material 300, the adhesive layer 310, and the insulating resin layer 20 in a region where the wiring layer 30 does not exist. Therefore, by providing an alignment mark (not shown) on the semiconductor substrate 50, the element mounting substrate 12 and the semiconductor substrate 50 can be aligned while directly observing the alignment mark on the semiconductor substrate 50 side. .
  • the element mounting substrate 12 and the semiconductor element 100 are subjected to main pressure bonding using a press machine.
  • the insulating resin layer 20 is thermally cured.
  • the time and pressure at which the element mounting substrate 12 and the semiconductor element 100 are finally bonded are, for example, 10 MPa and 10 MPa, respectively.
  • a protective layer (photo solder resist layer) 70 is laminated on the upper surface of the wiring layer 30 and the exposed insulating resin layer 20, a predetermined region of the protective layer 70 is formed by photolithography. An opening 72 is provided in the (solder ball mounting area).
  • the protective layer 70 functions as a protective film for the wiring layer 30.
  • An epoxy resin or the like is employed for the protective layer 70, and the film thickness thereof is, for example, about 30 ⁇ m.
  • solder balls 80 are mounted on the openings 72 of the protective layer 70 by screen printing.
  • the solder ball 80 is formed by printing a solder paste made of a resin and a solder material in a paste form on a desired location using a screen mask and heating to a solder melting temperature.
  • dicing processing is performed along the scribe line L to separate the semiconductor module 10 into individual pieces.
  • the semiconductor module 10 according to the first embodiment can be manufactured.
  • the formation process of the bump electrode 32, the Au / Ni layer 34, and the wiring layer 30 is performed in a state where the copper plate 200 is supported by the base material 300. 200 is easy to handle, and the possibility of damaging the wiring layer 30 and the protruding electrode 32 can be reduced. As a result, the manufacturing yield of the semiconductor module 10 can be improved.
  • the wiring layer 30 is already formed on the element mounting substrate 12, and there is no extra metal portion for forming the wiring layer 30. For this reason, the curvature which arises when the element mounting board
  • the manufacturing time can be shortened and the wiring layer 30 can be shortened. It can suppress that dispersion
  • the Au / Ni layer 34 formed on the top surface of the bump electrode 32 is coated with the insulating resin layer 20, and then the insulating resin layer 20 is thinned to form the top surface of the bump electrode 32.
  • the method of forming the insulating resin layer 20 is not limited to this.
  • the insulating resin layer 20 can be laminated so that the Au / Ni layer 34 formed on the top surface of the protruding electrode 32 is exposed by adjusting the viscosity and the coating amount of the insulating resin layer 20.
  • the insulating resin layer 20 is made of a photosensitive resin and the insulating resin layer 20 is laminated, the Au / Ni layer 34 portion formed on the top surface of the bump electrode 32 is masked and exposed and developed, whereby the bump electrode The insulating resin layer 20 may be formed so that the Au / Ni layer 34 formed on the top surface of the 32 is exposed.
  • the second manufacturing method of the semiconductor module is the same as the first manufacturing method of the semiconductor module up to the step shown in FIG.
  • the insulating resin layer 20 is formed using a solvent such as NaOH or acetone, O 2 plasma, or the like. Remove.
  • an insulating resin layer 20 ′ is injected between the wiring layer 30 and the semiconductor element 100.
  • the insulating resin layer 20 ′ used at this time is an insulating resin layer having a higher heat conductivity filler content than the insulating resin layer 20, an insulating resin layer having an adhesive strength higher than that of the insulating resin layer 20, or the like.
  • the function is higher than that of the insulating resin layer 20.
  • the arrow shown in FIG. 8B schematically shows the flow of the injected insulating resin layer 20 ′.
  • the steps shown in FIGS. 6B to 7B are performed in the same manner as in the first manufacturing method of the semiconductor module.
  • the semiconductor module 10 in which the insulating resin layer 20 is replaced with the high-functional insulating resin layer 20 ′ in the configuration shown in FIG. 1 is manufactured.
  • the effect of adopting the second manufacturing method of the semiconductor module will be described below.
  • the end surface E of the wiring layer 30 is tapered so as to enter the inside of the formation region of the wiring layer 30 as the semiconductor element 100 is approached.
  • the protruding electrode 32 has a shape such that the diameter becomes narrower as it approaches the top.
  • the end surface of the wiring layer 30 and the side surface of the protruding electrode 32 are tapered so that the opening between the wiring layer 30 and the protruding electrode 32 and the semiconductor element 100 expands as the semiconductor element 100 is approached.
  • the insulating resin layer 20 ′ flows smoothly into the opening when the insulating resin layer 20 ′ is injected, voids are formed between the wiring layer 30, the protruding electrode 32 and the semiconductor module 10 and the insulating resin layer 20 ′. Is suppressed from occurring. As a result, the manufacturing yield and operation reliability of the semiconductor module 10 can be improved.
  • the insulating resin layer 20 includes It is possible to reduce the possibility that these fillers intervene as residues at the bonding interface. For this reason, after sufficiently securing the connection reliability between the protruding electrode 32 and the element electrode 52, the insulating resin layer 20 is replaced with a more functional insulating resin layer 20 ′, thereby improving the connection reliability and insulating resin.
  • the enhancement of the function of the layer 20 ′ can be achieved.
  • a resist 208 having an opening that exposes an Au / Ni layer formation region corresponding to the element electrode is formed.
  • an Au / Ni layer 34 is formed in the opening by an electrolytic plating method or an electroless plating method.
  • the bump plate 32 is formed by etching the copper plate 200 using the Au / Ni layer 34 as a mask.
  • the wiring layer 30 is formed by processing the copper plate 200 into a predetermined wiring pattern using a lithography method and an etching method.
  • the semiconductor module 10 according to the second embodiment shown in FIG. 10B can be manufactured by performing the same processes as those in FIGS. 4B to 7B.
  • the semiconductor module 10 according to the second embodiment has the same configuration as that of the semiconductor module 10 according to the first embodiment except that the Au / Ni layer 34 is provided only on the top surface of the protruding electrode 32.
  • the Au / Ni layer 34 also serves as a mask for forming the protruding electrode 32 from the copper plate 200, the steps required for forming and removing the mask can be omitted. For this reason, the manufacturing process of the semiconductor module can be further simplified, and the manufacturing time and manufacturing cost can be reduced.
  • the wiring layer 30 may be formed by patterning the copper plate 200 (see FIG. 11A). That is, in the fourth manufacturing method of the semiconductor module, the protruding electrode is not formed from the copper plate 200, and the wiring layer 30 having the same thickness as the copper plate 200 is formed by processing the copper plate 200. Subsequently, the semiconductor module 10 according to Embodiment 3 shown in FIG. 11B can be manufactured by performing the same steps as those in FIGS. 4B to 7B. As shown in FIG. 11B, in the semiconductor module 10 according to the third embodiment, the Au / Ni layer 34 provided on one main surface of the wiring layer 30 is connected to the Au / Ni layer 54 of the semiconductor element 100. Has been.
  • the thickness of the wiring layer 30 can be made equal to the thickness of the copper plate 200, it is possible to increase the thickness of the wiring layer 30 while suppressing the warpage of the semiconductor module 10.
  • the protruding electrode 32 and the element electrode 52 are electrically connected by Au—Au connection, but the top surface of the protruding electrode 32 is Sn plated.
  • a layer may be applied, and the protruding electrode 32 and the device electrode 52 may be electrically connected by Sn—Au connection.
  • a Cu layer may be formed on the device electrode 52 instead of the Au / Ni layer 54, and the Cu layer and the protruding electrode 32 may be directly joined by Cu—Cu connection. According to these joining methods, the amount of Au used can be reduced, and the manufacturing cost of the semiconductor module can be reduced.
  • FIG. 12 shows a cross-sectional view of a conventional solar cell
  • FIG. 13 shows an embodiment when the present invention is applied to a solar cell.
  • FIG. 12 schematically shows a cross-sectional structure of a conventional pin-type amorphous solar cell.
  • 400 is a solar cell body
  • 451 is a substrate
  • 452 is a lower electrode
  • 453 is an n-type semiconductor layer
  • 454 is an i layer
  • 455 is a p layer
  • 456 is a transparent electrode
  • 457 is a passivation layer
  • 458 is an upper electrode.
  • Reference numeral 459 denotes a collecting electrode
  • 460 denotes a bus bar. Light is incident from the top of the figure.
  • the substrate 451 may be a conductive material such as a metal such as Fe, Ni, Cr, Al, Mo, Au, Pt, Pb or an alloy thereof, or may be polyester, polyethylene, polycarbonate, cellulose acetate, polypropylene, An electrically insulating material such as a film or sheet of a heat-resistant synthetic resin such as polyvinyl chloride, polyvinylidene chloride, polystyrene, polyamide, polyimide, or epoxy, glass, or ceramics may be used.
  • a conductive material such as a metal such as Fe, Ni, Cr, Al, Mo, Au, Pt, Pb or an alloy thereof
  • An electrically insulating material such as a film or sheet of a heat-resistant synthetic resin such as polyvinyl chloride, polyvinylidene chloride, polystyrene, polyamide, polyimide, or epoxy, glass, or ceramics may be used.
  • the surface on the side where the deposited film is formed is formed of Al, Ag, Pt, Au, Ti, W, Fe, Cr, Cu, stainless steel, SnO 2 , In 2 O 3
  • the lower electrode 102 is formed by using a so-called simple metal or alloy such as ZnO or ITO, and a transparent conductive oxide (TCO), for example, using a method such as plating, vapor deposition, or sputtering.
  • the n layer 453, the i layer 454, and the p layer 455 are manufactured by a normal semiconductor manufacturing process, and are manufactured by using, for example, a vapor deposition method, a sputtering method, a CVD method, or the like.
  • amorphous silicon or the like can be given as a semiconductor material constituting the i layer 454 that is preferably used in the solar cell of the present invention.
  • a semiconductor material constituting the p layer 455 or the n layer 453 preferably used in the present photovoltaic element can be obtained by doping the amorphous silicon constituting the i layer 454 described above with a valence electron control agent.
  • the transparent electrode 106 preferably has a high light transmittance (for example, 90% or more) in order to efficiently absorb light from the sun, a white fluorescent lamp, or the like into the semiconductor layer.
  • the material is SnO 2 , Examples thereof include metal oxides such as In 2 O 3 , ZnO, and ITO.
  • the passivation layer 457 is an insulating material for preventing a defective portion from coming into contact with the upper electrode 458, the current collecting electrode 459, and the bus bar 460. Further, since the passivation layer 457 is laminated on the entire surface of the semiconductor layer, it needs to be a light-transmitting material so as not to prevent the incidence of sunlight. Further, considering the environment when used outdoors as a solar cell, it is required to have good weather resistance and stability to heat, humidity and light. In some cases, the solar cell is bent or shocked, so that it is necessary to have mechanical strength. As such a material, a polymer resin is suitable, and specifically, polyester, ethylene vinyl acetate copolymer, acrylic resin, epoxy resin, urethane, or the like is used.
  • the film thickness may be any film thickness that maintains electrical insulation and does not impair light transmission. For example, it is 3 ⁇ m to 5 ⁇ m.
  • the upper electrode 458 performs the same function as the current collecting electrode 458 in terms of function.
  • the electrode material include metals such as Ag, Pt, Cu, and C.
  • the bus bar 560 is an electrode for further collecting a current flowing through the current collecting electrode 459.
  • a metal such as Ag, Pt, or Cu is used as the electrode material.
  • FIG. 13A is a cross-sectional view along the line AA ′ shown in the perspective view of the solar cell shown in FIG.
  • a SUS substrate 551 by a sputtering apparatus to form a lower electrode 552.
  • the substrate 551 is deposited in the order of an n layer 553, an i layer 554, and a p layer 555 by a plasma CVD film forming apparatus.
  • an alloy of In and Sn was vapor-deposited with a vapor deposition apparatus, and about 700 liters of a transparent electrode 556 having a function of serving as an antireflection effect was deposited.
  • the upper electrode 558 having a width of about 100 ⁇ m and a length of 8 cm is printed at a distance of 1 cm on the substrate 551 by screen printing.
  • the element mounting substrate 12 provided with the base material 300 formed by the steps shown in FIGS. 2 to 4 is bonded to the passivation layer 557 by pressure bonding.
  • the element mounting substrate 32 is a copper plate provided with protruding electrodes 32 (the surface of which is covered with Au / Ni 34) formed integrally with the copper plate, and the copper plate Has the functions of the upper electrode and the collector electrode of the solar cell (hereinafter referred to as the upper electrode 558).
  • the material of the passivation layer 557 is the same as that of the insulating resin layer 20 in FIGS. 2 to 4 described above. That is, an insulating resin having fluidity by pressurization is used. Specifically, the pressure bonding is performed from the substrate 551 side and the upper electrode 558 side with the protruding electrode 32 of the upper electrode 558 facing the formed passivation layer 557. Then, the protruding electrode 32 penetrates the passivation layer 557 made of resin and reaches the transparent electrode 556, so that the protruding electrode 32 and the transparent electrode 556 can be electrically connected.
  • FIG. 12 shows a structure of a conventional solar cell.
  • the passivation layer 457 formed on the transparent electrode is insulative or high resistance, even if the upper electrode 458 is laminated thereon, the ohmic contact between the upper electrode 458 and the transparent electrode 456 is performed. Is not sufficient, and current cannot sufficiently flow through the collector electrode 459. Therefore, it is necessary that the upper electrode 458 and the transparent electrode 456 are in sufficient contact.
  • a conductive paste containing an unreacted component of a solvent or a polymer resin is included in the passivation layer 457, so that the passivation layer 457 is dissolved and the conductive filler contacts the transparent electrode 456. Like to do.
  • the protruding electrode 32 formed on the upper electrode 558 passes through the passivation layer 557 by pressurization without containing the conductive paste in the passivation layer 557 and is transparent.
  • the projection electrode 32 and the transparent electrode 556 can be electrically connected by reaching the electrode 556.
  • a bus bar 560 made of a metal such as Ag, Pt, or Cu is provided above the upper electrode 558. Form. This completes the solar cell.
  • the handling of the metal plate for forming the wiring layer is facilitated, and the manufacturing process of the semiconductor module is simplified. can do.

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Abstract

【課題】半導体モジュールを製造する際に構成部材のハンドリングを容易にし、半導体モジュールの製造プロセスを簡略化する。 【解決手段】銅板を接着層３１０により基材３００に保持した状態で、銅板を選択的に除去して突起電極３２および配線層３０を形成する。続いて、配線層３０、突起電極３２および接着層３１０の上にＡｕ／Ｎｉ層３４が露出するように絶縁樹脂層２０を積層して素子搭載用基板を形成する。基材３００に保持された素子搭載用基板と半導体素子とを仮圧着した後、基材３００および接着層３１０を除去し、素子搭載用基板と半導体素子とを本圧着する。

Description

半導体モジュールおよび半導体モジュールの製造方法
　本発明は、素子搭載用基板に半導体素子が搭載された半導体モジュールおよび半導体モジュールの製造方法に関する。
　携帯電話、ＰＤＡ、ＤＶＣ、ＤＳＣといったポータブルエレクトロニクス機器の高機能化が加速するなか、こうした製品が市場で受け入れられるためには小型・軽量化が必須となっており、その実現のために高集積のシステムＬＳＩが求められている。一方、これらのエレクトロニクス機器に対しては、より使いやすく便利なものが求められており、機器に使用されるＬＳＩに対し、高機能化、高性能化が要求されている。このため、ＬＳＩチップの高集積化にともないそのＩ／Ｏ数（入出力部の数）が増大する一方でパッケージ自体の小型化要求も強く、これらを両立させるために、半導体部品の高密度な基板実装に適合した半導体モジュールの開発が強く求められている。こうした要求に対応するため、ＣＳＰ（Ｃｈｉｐ　Ｓｉｚｅ　Ｐａｃｋａｇｅ）と呼ばれるパッケージ技術が種々開発されている。
特開平１０－２２３３９号公報
　半導体モジュールが小型化するにつれて、半導体モジュールを構成する配線基板、すなわち、素子搭載用基板中の配線層の高密度化、薄膜化が進んでいる。このため、製造プロセスの過程で配線層を形成するための金属板にしわが生じることで製造歩留まりの低下を招きやすくなり、加工中の配線層の取り扱いや、素子搭載用基板を半導体素子に圧着する際のハンドリングが難しくなっていた。
　本発明はこうした課題に鑑みてなされたものであり、その目的は、半導体モジュールを製造する際に構成部材のハンドリングを容易にし、半導体モジュールの製造プロセスを簡略化することができる技術の提供にある。
　本発明のある態様は、半導体モジュールの製造方法である。当該半導体モジュールの製造方法は、基材に保持された金属板を選択的に除去して、基板電極が設けられた配線層を形成する工程と、基板電極の頂部面自体または前記基板電極の頂部面に設けられた金属層が露出するように、基材の上に絶縁樹脂層を形成して、配線層、基板電極および絶縁樹脂層を含む素子搭載用基板を形成する工程と、を備え、配線層を形成する工程において、配線層は、その端面が、半導体素子に近づくにつれて配線層の形成領域の内側に入り込むようなテーパー状にする工程を含むことを特徴とする。
　この態様の半導体モジュールの製造方法によれば、金属板が基材に支持された状態で、基板電極や配線層の形成工程が実施されるため、金属板のハンドリングが容易であり、配線層や基板電極を破損する可能性を低減することができる。この結果、半導体モジュールの製造歩留まりを向上させることができる。また、配線層を形成する工程において、配線層は、その端面が、半導体素子に近づくにつれて配線層の形成領域の内側に入り込むようなテーパー状にすることから、基材の上に形成する絶縁樹脂層が形成した配線層間にスムースに流れ込んでいき、その箇所に絶縁樹脂が行き渡らない空洞が生じることがない。
　上記態様の半導体モジュールの製造方法において、基板電極が金属板を選択的に除去することによって配線層と一体的に形成された突起電極であってもよい。また、基材が透明であり、素子搭載用基板を半導体素子に圧着する際に、基材を通して半導体素子の位置を確認して、素子搭載用基板と半導体素子とを位置合わせしてもよい。また、半導体素子に素子搭載用基板を圧着し、前記基材を除去した後、絶縁樹脂層を除去し、絶縁樹脂層に代えて絶縁樹脂層と機能が異なる別の絶縁樹脂層を形成する工程を備えてもよい。
　本発明の他の態様は、半導体モジュールである。当該半導体モジュールは、絶縁樹脂層と、絶縁樹脂層の一方の主表面に設けられた配線層と、配線層から絶縁樹脂層側に突出している突起電極と、突起電極に対向する素子電極が設けられた半導体素子と、を備え、配線層の端面が、半導体素子に近づくにつれて配線層の形成領域の内側に入り込むようなテーパー状であり、突起電極が絶縁樹脂層を貫通し、突起電極と素子電極とが電気的に接続されていることを特徴とする。
　なお、上述した各要素を適宜組み合わせたものも、本件特許出願によって特許による保護を求める発明の範囲に含まれうる。
　本発明によれば、配線層を形成するための金属板のハンドリングを容易にし、半導体モジュールの製造プロセスを簡略化することができる。
実施の形態１に係る半導体モジュールの構成を示す概略断面図である。 半導体モジュールの第１の製造方法を示す工程断面図である。 半導体モジュールの第１の製造方法を示す工程断面図である。 半導体モジュールの第１の製造方法を示す工程断面図である。 半導体モジュールの第１の製造方法を示す工程断面図である。 半導体モジュールの第１の製造方法を示す工程断面図である。 半導体モジュールの第１の製造方法を示す工程断面図である。 半導体モジュールの第２の製造方法を示す工程断面図である。 半導体モジュールの第３の製造方法を示す工程断面図である。 図１０（Ａ）は、半導体モジュールの第３の製造方法を示す工程断面図である。図１０（Ｂ）は、実施の形態２に係る半導体モジュールの構成を示す概略断面図である。 図１１（Ａ）は、半導体モジュールの第４の製造方法を示す工程断面図である。図１１（Ｂ）は、実施の形態３に係る半導体モジュールの構成を示す概略断面図である。 図１２は従来の太陽電池の構造を示す断面図である。 図１３は実施の形態に係る太陽電池の構造を示す図である。
　以下、本発明の実施の形態を図面を参照して説明する。なお、すべての図面において、同様な構成要素には同様の符号を付し、適宜説明を省略する。
　図１は、実施の形態１に係る半導体モジュール１０の構成を示す概略断面図である。半導体モジュール１０は、素子搭載用基板１２および素子搭載用基板１２と貼り合わされた半導体素子１００とを備える。
　素子搭載用基板１２は、絶縁性の樹脂で形成された絶縁樹脂層２０と、絶縁樹脂層２０の一方の主表面に設けられた配線層３０と、配線層３０と電気的に接続され、配線層３０から絶縁樹脂層２０の側に突出している複数の突起電極３２とを主な構成として備える。　
　絶縁樹脂層２０を構成する材料としては、たとえば、ＢＴレジン等のメラミン誘導体、液晶ポリマー、エポキシ樹脂、ＰＰＥ樹脂、ポリイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミドビスマレイミド等の熱硬化性樹脂が例示される。半導体モジュール１０の放熱性向上の観点から、絶縁樹脂層２０は高熱伝導性を有することが望ましい。このため、絶縁樹脂層２０は、銀、ビスマス、銅、アルミニウム、マグネシウム、錫、亜鉛およびこれらの合金やアルミナなどを高熱伝導性フィラーとして含有することが好ましい。
　配線層３０は、絶縁樹脂層２０の一方の主表面に設けられており、導電材料、好ましくは圧延金属や電解箔、さらには圧延銅や電解銅箔により形成される。配線層３０には、絶縁樹脂層２０の側に複数の突起電極３２が突設されている。本実施の形態においては、配線層３０と突起電極３２とは一体的に形成されているが、特にこれに限定されない。
　配線層３０の端面Ｅは、絶縁樹脂層２０と接している。この配線層３０の端面Ｅは、半導体素子１００に近づくにつれて配線層３０の形成領域の内側に入り込むようなテーパー状となっている。
　この形状のため、配線層３０の端面Ｅが半導体素子１００に近づくにつれて配線層３０の形成領域の外側に張り出すようなテーパー状の場合と異なり、後述の外部接続電極であるはんだボール８０を形成する面積が大きくできるので、配線層に接続する面積の大きい外部接続電極を形成することができる。また外部接続電極の配線層との接触面積が大きいことにより、半導体素子から発生する熱を外部接続電極から効率よく放出することができるとともに、配線層と外部接続電極との密着性を高めることができる。
　突起電極３２は、たとえば平面視で丸型であり、頂部に近づくにつれて径が細くなるように形成された側面を備えている。その側面は、配線層３０の端面Ｅの傾斜方向と同じ方向に傾斜していても良い。そうすると、半導体素子から発生する熱の拡散経路にボトルネック（抵抗となる箇所）がなく効果的に放熱ができる。なお、突起電極３２の形状は特に限定されず、たとえば、所定の径を有する円柱状であってもよい。また、平面視で四角形などの多角形であってもよい。
　突起電極３２の頂部面および側面には、Ａｕ／Ｎｉ層３４が設けられている。Ａｕ／Ｎｉ層３４は、露出面となるＡｕ層と、Ａｕ層と突起電極３２の頂部面との間に介在するＮｉ層からなる。
　配線層３０の絶縁樹脂層２０と反対側の主表面には、配線層３０の酸化などを防ぐための保護層７０が設けられている。保護層７０としては、ソルダーレジスト層などが挙げられる。保護層７０の所定の領域には開口部７２が形成されており、開口部７２によって配線層３０の一部が露出している。開口部７２内には外部接続電極としてのはんだボール８０が形成され、はんだボール８０と配線層３０とが電気的に接続されている。はんだボール８０を形成する位置、すなわち開口部７２の形成領域は、たとえば再配線（配線層３０）で引き回した先の端部である。
　半導体素子１００は、半導体基板５０、素子電極５２、Ａｕ／Ｎｉ層５４および保護層５６を有する。半導体基板５０の一方の主表面に素子電極５２、Ａｕ／Ｎｉ層５４および保護層５６が形成されている。具体的には、半導体基板５０は、Ｐ型シリコン基板などのシリコン基板である。半導体基板５０の一方の主表面には、所定の集積回路（図示せず）およびその外周縁部に位置する素子電極５２とが形成されている。素子電極５２の材料にはアルミニウムや銅などの金属が採用される。素子電極５２を除いた半導体基板５０の主表面上に、半導体基板５０を保護するための絶縁性の保護層５６が形成されている。保護層５６としてはシリコン酸化膜（ＳｉＯ2）やシリコン窒化膜（ＳｉＮ）やポリイミド（ＰＩ）などが採用される。また、素子電極５２の上にＡｕ層が露出面となるようなＡｕ／Ｎｉ層５４が形成されている。
　突起電極３２の頂部面に設けられたＡｕ／Ｎｉ層３４の金と、素子電極５２の表面に設けられたＡｕ／Ｎｉ層５４の金とが金－金接合することにより、突起電極３２と、これに対応する素子電極５２とが電気的に接続されている。なお、Ａｕ／Ｎｉ層３４とＡｕ／Ｎｉ層５４とが金－金接合することは、突起電極３２と、これに対応する素子電極５２との電気的な接続の信頼性の向上に寄与している。
　本実施の形態の半導体モジュール１０によれば、素子搭載用基板１２と半導体素子１００とを圧着する際に、配線層３０と半導体素子１００との間の絶縁樹脂層２０が配線層３０のテーパー状の端面Ｅに沿って流動しやすくなるため、隅々にまで絶縁樹脂層２０が充填されることから、絶縁樹脂層２０と配線層３０との密着性、及び絶縁樹脂層２０と保護層７０との密着性を高めることができる。
　また、配線層３０間が短絡していないことを顕微鏡を用いて検査する場合に、端面Ｅにおいて、半導体素子１００から遠い方の端部に焦点を合わせて観察を行えば済むため、検査に要する手間を低減することができる。
（半導体モジュールの第１の製造方法）
　実施の形態に係る半導体モジュール１０の製造方法について図２乃至７を参照して説明する。
　まず、図２（Ａ）に示すように、図１に示したような突起電極３２の高さと配線層３０の厚さとの和と同等な厚さを有する金属板としての銅板２００を用意する。銅板２００の厚さは、たとえば４０μｍである。銅板２００としては圧延された銅からなる圧延銅や、電解銅箔が採用される。この銅板２００を支持部材としての基材３００に接着層３１０を用いて貼り付ける。基材３００は透明であることが好ましく、ガラス基板やＰＥＴフィルムが好適である。
　次に、図２（Ｂ）に示すように、スクライブラインＬによって囲まれた各区画において、図１に示した突起電極３２の形成予定領域に対応したパターンに合わせてレジスト２０２をリソグラフィ法により選択的に形成する。具体的には、ラミネーター装置を用いて銅板２００に所定膜厚のレジスト膜を貼り付け、突起電極３２のパターンを有するフォトマスクを用いて露光した後、現像することによって、銅板２００の上にレジスト２０２が選択的に形成される。なお、レジストとの密着性向上のために、レジスト膜のラミネート前に、銅板２００の表面に研磨、洗浄等の前処理を必要に応じて施すことが望ましい。
　次に、図２（Ｃ）に示すように、レジスト２０２をマスクとして塩化第二鉄溶液などの薬液を用いたウェットエッチング処理を行うことにより、銅板２００の表面Ｓから突出する所定パターンの突起電極３２を形成する。この際、突起電極３２はその先端部に近づくにつれて径（寸法）が細くなるテーパー状の側面部を有するように形成される。なお、突起電極３２の高さは、たとえば、２０μｍである。続いて、レジスト２０２およびレジスト保護膜を剥離剤を用いて剥離する。以上説明した工程により、銅板２００に突起電極３２が一体的に形成される。なお、突起電極３２は、素子搭載用基板側の電極である「基板電極」の一例である。
　次に、図３（Ａ）に示すように、突起電極３２が露出するような開口部を有するレジスト２０４をリソグラフィ法により選択的に形成する。具体的には、ラミネーター装置を用いて銅板２００に所定膜厚のレジスト膜を貼り付け、突起電極３２に対応する開口部をマスクするようなパターンを有するフォトマスクを用いて露光した後、現像することによって、銅板２００の上にレジスト２０４が選択的に形成される。
　次に、図３（Ｂ）に示すように、レジスト２０４に設けられた開口部内に露出した突起電極３２の頂部面および側面に電解めっき法または無電解めっき法によりＡｕ／Ｎｉ層３４を形成する。Ａｕ／Ｎｉ層３４では、Ａｕ層が露出面となり、Ａｕ層と突起電極３２の頂部面との間にＮｉ層が介在する。Ａｕ／Ｎｉ層３４のうち、たとえば、Ａｕ層の厚さは０．２５μｍ、Ｎｉ層の厚さは１～３μｍである。なお、Ａｕ／Ｎｉ層３４に代えて、たとえば金ペーストなどの導電性ペーストを用いて突起電極３２の頂部面および側面に金属層を形成してもよい。
　次に、図３（Ｃ）に示すように、配線層形成領域に対応するレジスト２０６をリソグラフィ法により選択的に形成する。具体的には、ラミネーター装置を用いて銅板２００に所定膜厚のレジスト膜を貼り付け、配線層形成領域に対応するパターンを有するフォトマスクを用いて露光した後、現像することによって、銅板２００の上にレジスト２０６が選択的に形成される。
　次に、図４（Ａ）に示すように、レジスト２０６をマスクとして塩化第二鉄溶液などの薬液を用いたウェットエッチング処理を行うことにより、銅板２００を所定の配線パターンに加工して配線層（再配線）３０を形成する。これにより、所定の突起電極３２が一体的に設けられた配線層３０が形成される。言い換えると、突起電極３２と配線層３０とが同一材料にて連続的に形成されている。上述したように、加工前の銅板２００の厚さが４０μで、突起電極３２の高さが２０μｍの場合には、配線層３０の厚さは２０μｍとなる。
　次に、図４（Ｂ）に示すように、ロールラミネータやホットプレス機を用いて、配線層３０、突起電極３２および接着層３１０の上に絶縁樹脂層２０を積層する。絶縁樹脂層２０としては、たとえば、熱硬化性のエポキシ系接着樹脂フィルムが用いられる。積層される絶縁樹脂層２０の厚さは、突起電極３２の頂部面に形成されたＡｕ／Ｎｉ層３４を被覆するのに十分な厚みであればよい。後述する工程において、半導体基板５０に貼り合わせるため、エポキシ系接着樹脂フィルムの積層時の温度は、エポキシ系接着樹脂フィルムが完全硬化しない温度（１００℃以下）が好ましい。
　次に、図４（Ｃ）に示すように、Ｏ2プラズマエッチングや研磨処理を用いて、突起電極３２の頂部面に設けられたＡｕ／Ｎｉ層３４が露出し、かつ突起電極３２の頂部面と絶縁樹脂層２０の露出面が面一になるように絶縁樹脂層２０を薄膜化する。これにより、配線層３０、突起電極３２および絶縁樹脂層２０からなる素子搭載用基板１２が形成される。
　次に、図５（Ａ）に示すように、半導体素子１００として、一方の主表面に素子電極５２、Ａｕ／Ｎｉ層５４および保護層５６が形成された半導体基板５０を用意する。具体的には、Ｐ型シリコン基板などの半導体基板５０に対して、周知のリソグラフィ技術、エッチング技術、イオン注入技術、成膜技術、及び熱処理技術などを組み合わせた半導体製造プロセスを用いて一方の主表面に所定の集積回路とその外周縁部に素子電極５２を形成する。素子電極５２の材料にはアルミニウムや銅などの金属が採用される。これらの素子電極５２を除いた半導体基板５０の主表面上に、半導体基板５０を保護するための絶縁性の保護層５６が形成されている。保護層５６としてはシリコン酸化膜（ＳｉＯ2）やシリコン窒化膜（ＳｉＮ）やポリイミド（ＰＩ）などが採用される。また、素子電極５２の上にＡｕ層が露出面となるようなＡｕ／Ｎｉ層５４を形成する。Ａｕ／Ｎｉ層５４の層構成および形成方法は、Ａｕ／Ｎｉ層３４と同様であり、素子電極５２の表面が露出するような開口部を有するマスクを形成した状態で、当該開口部内に電解めっき、または無電解めっきを行うことにより形成することができる。
　次に、図５（Ｂ）に示すように、素子電極５２に設けられたＡｕ／Ｎｉ層５４と、Ａｕ／Ｎｉ層５４に対応して突起電極３２の頂部面に設けられたＡｕ／Ｎｉ層３４とを位置合わせした後、素子搭載用基板１２と半導体素子１００とをプレス機を用いて貼り合わせて仮圧着する。本工程で素子搭載用基板１２と半導体素子１００とを貼り合わせる際の貼り合わせ時間、圧力は、たとえば、それぞれ３分間、１ＭＰａである。
　この段階では、配線層３０が既にパターニングされており、配線層３０が存在しない領域では、基材３００、接着層３１０および絶縁樹脂層２０を通して、半導体基板５０を視認可能である。このため、半導体基板５０にアライメントマーク（図示せず）を設けておくことにより、半導体基板５０側のアライメントマークを直接観察しながら素子搭載用基板１２と半導体基板５０とを位置あわせすることができる。
　次に、図６（Ａ）に示すように、基材３００および接着層３１０を除去した後、プレス機を用いて、素子搭載用基板１２と半導体素子１００とを本圧着する。この際に、絶縁樹脂層２０は熱硬化する。素子搭載用基板１２と半導体素子１００とを本圧着する際の時間、圧力は、それぞれ、たとえば１０分間、１０ＭＰａである。なお、この本圧着は、上述の仮圧着と同時に行ってもよい。
　突起電極３２の頂部面に設けられたＡｕ／Ｎｉ層３４が露出した状態で、本圧着することにより、Ａｕ／Ｎｉ層３４とＡｕ／Ｎｉ層５４との間に残渣が生じることが抑制されるため、突起電極３２と素子電極５２との電気的な接続の信頼性を向上させることができる。
　次に、図６（Ｂ）に示すように、配線層３０および露出した絶縁樹脂層２０の上面に保護層（フォトソルダーレジスト層）７０を積層した後、フォトリソグラフィ法により保護層７０の所定領域（はんだボール搭載領域）に開口部７２を設ける。保護層７０は配線層３０の保護膜として機能する。保護層７０にはエポキシ樹脂などが採用され、その膜厚は、たとえば、約３０μｍである。
　次に、図７（Ａ）に示すように、保護層７０の開口部７２にスクリーン印刷法によりはんだボール８０を搭載する。具体的には、樹脂とはんだ材をペースト状にしたはんだペーストをスクリーンマスクにより所望の箇所に印刷し、はんだ溶融温度に加熱することではんだボール８０を形成する。
　次に、図７（Ｂ）に示すように、スクライブラインＬに沿ってダイシング加工を行うことにより、半導体モジュール１０を個片化する。
　以上の工程によれば、実施の形態１に係る半導体モジュール１０を製造することができる。上述した半導体モジュール１０の製造方法では、銅板２００が基材３００に支持された状態で、突起電極３２、Ａｕ／Ｎｉ層３４および配線層３０の形成工程が実施されるため、これらの工程における銅板２００のハンドリングが容易であり、配線層３０や突起電極３２を破損する可能性を低減することができる。この結果、半導体モジュール１０の製造歩留まりを向上させることができる。
　また、素子搭載用基板１２を半導体素子１００に本圧着する際に、素子搭載用基板１２において配線層３０が既に形成されており、配線層３０を形成するための余分な金属部分がない。このため、素子搭載用基板１２を半導体素子１００に本圧着した場合に生じる反りを低減することができる。
　また、銅板２００から配線層３０を形成する前に、銅板２００の厚みを配線層３０の厚みにエッチダウンして調整する必要がないため、製造時間の短縮を図ることができるとともに、配線層３０の厚みにばらつきが生じることを抑制することができる。
　なお、本製造方法では、突起電極３２の頂部面に形成されたＡｕ／Ｎｉ層３４を絶縁樹脂層２０で被覆した後に、絶縁樹脂層２０を薄膜化して突起電極３２の頂部面に形成されたＡｕ／Ｎｉ層３４を露出させているが（図４（Ａ）、図４（Ｂ）参照）、絶縁樹脂層２０の形成方法はこれに限られない。たとえば、絶縁樹脂層２０の粘度や塗布量を調節することにより、突起電極３２の頂部面に形成されたＡｕ／Ｎｉ層３４が露出するように絶縁樹脂層２０を積層することもできる。また、絶縁樹脂層２０を感光性樹脂とし、絶縁樹脂層２０を積層した後に、突起電極３２の頂部面に形成されたＡｕ／Ｎｉ層３４部分をマスクして露光、現像することにより、突起電極３２の頂部面に形成されたＡｕ／Ｎｉ層３４が露出するように絶縁樹脂層２０を形成してもよい。
（半導体モジュールの第２の製造方法）
　半導体モジュールの第２の製造方法は、図６（Ａ）に示す工程までは、半導体モジュールの第１の製造方法と同様である。半導体モジュールの第２の製造方法では、図６（Ａ）に示す工程の後に、図８（Ａ）に示すように、ＮａＯＨ、アセトンなどの溶剤や、Ｏ2プラズマなどを用いて絶縁樹脂層２０を除去する。
　次に、図８（Ｂ）に示すように、配線層３０と半導体素子１００との間に絶縁樹脂層２０'を注入する。このときに用いる絶縁樹脂層２０'は、熱伝導性が高いフィラーの含有率が絶縁樹脂層２０に比べて高い絶縁樹脂層や、絶縁樹脂層２０よりも接着強度が高い絶縁樹脂層などであり、絶縁樹脂層２０に比べて高機能である。なお、図８（Ｂ）に示す矢印は、注入された絶縁樹脂層２０'の流れを模式的に示す。
　このように、絶縁樹脂層２０を高機能型の絶縁樹脂層２０'に入れ替えた後、半導体モジュールの第１の製造方法と同様に、図６（Ｂ）～図７（Ｂ）に示す工程を実施することにより、図１に示す構成において、絶縁樹脂層２０が高機能型の絶縁樹脂層２０'に入れ替えられた半導体モジュール１０が製造される。
　半導体モジュールの第２の製造方法を採用する場合の効果について以下に述べる。配線層３０の端面Ｅは、半導体素子１００に近づくにつれて配線層３０の形成領域の内側に入り込むようなテーパー状となっている。また、突起電極３２は、頂部に近づくにつれて径が細くなるような形状になっている。言い換えると、配線層３０および突起電極３２と半導体素子１００との間の開口部が半導体素子１００に近づくにつれて広がるように、配線層３０の端面および突起電極３２の側面がテーパー状となっている。このため、絶縁樹脂層２０'を注入する際に、絶縁樹脂層２０'が開口部内にスムースに流れ込むため、配線層３０、突起電極３２および半導体モジュール１０と絶縁樹脂層２０'との間にボイドが発生することが抑制される。この結果、半導体モジュール１０の製造歩留まりや、動作信頼性を向上させることができる。
　また、本圧着に用いる絶縁樹脂層２０のフィラーの含有率を相対的に低くすることにより、突起電極３２と素子電極５２とをＡｕ－Ａｕ接合を介して接合する際に、絶縁樹脂層２０中のフィラーが接合界面に残渣として介在する可能性を低減することができる。このため、突起電極３２と素子電極５２との接続信頼性を十分に確保した上で、絶縁樹脂層２０をより高機能な絶縁樹脂層２０'に入れ替えることで、接続信頼性の向上と絶縁樹脂層２０'の高機能化の両立を図ることができる。
（半導体モジュールの第３の製造方法）
　図９（Ａ）に示すように、素子電極に対応するＡｕ／Ｎｉ層の形成領域が露出するような開口部を有するレジスト２０８を形成する。
　次に、図９（Ｂ）に示すように、電解めっき法または無電解めっき法により開口部内にＡｕ／Ｎｉ層３４を形成する。
　次に、図９（Ｃ）に示すように、レジスト２０８を除去した後、Ａｕ／Ｎｉ層３４をマスクとして銅板２００をエッチングすることにより、突起電極３２を形成する。
　次に、図１０（Ａ）に示すように、リソグラフィ法およびエッチング法を用いて銅板２００を所定の配線パターンに加工して配線層３０を形成する。
　続いて、図４（Ｂ）～図７（Ｂ）と同様な工程を実施することにより、図１０（Ｂ）に示す実施の形態２に係る半導体モジュール１０を製造することができる。実施の形態２に係る半導体モジュール１０は、Ａｕ／Ｎｉ層３４が突起電極３２の頂部面にのみ設けられていることを除き、実施の形態１の半導体モジュール１０と同様な構成を有する。
　半導体モジュールの第３の製造方法では、Ａｕ／Ｎｉ層３４が銅板２００から突起電極３２を形成するためのマスクを兼ねているため、マスクの形成や除去に要する工程を省略することができる。このため、半導体モジュールの製造プロセスをより簡略化し、製造時間や製造コストの低減を図ることがきる。
（半導体モジュールの第４の製造方法）
　図９（Ｂ）に示す工程の後、銅板２００をパターニングすることにより、配線層３０を形成してもよい（図１１（Ａ）参照）。すなわち、半導体モジュールの第４の製造方法では、銅板２００から突起電極が形成されず、銅板２００の加工により、銅板２００と同等な厚さの配線層３０が形成される。続いて、図４（Ｂ）～図７（Ｂ）と同様な工程を実施することにより、図１１（Ｂ）に示す実施の形態３に係る半導体モジュール１０を製造することができる。図１１（Ｂ）に示すように、実施の形態３に係る半導体モジュール１０では、配線層３０の一方の主表面に設けられたＡｕ／Ｎｉ層３４が半導体素子１００のＡｕ／Ｎｉ層５４と接続されている。
　半導体モジュールの第４の製造方法では、素子搭載用基板１２において突起電極が形成されていない。このため、配線層３０の厚さを銅板２００の厚さと同等とすることができるので、半導体モジュール１０に反りが発生することを抑制しつつ、配線層３０の厚膜化を図ることができる。
　本発明は、上述の各実施の形態に限定されるものではなく、当業者の知識に基づいて各種の設計変更等の変形を加えることも可能であり、そのような変形が加えられた実施の形態も本発明の範囲に含まれうるものである。
　たとえば、上述の実施の形態１および実施の形態２の半導体モジュールでは、突起電極３２と素子電極５２とがＡｕ－Ａｕ接続により電気的に接続されているが、突起電極３２の頂部面にＳｎめっき層を施し、突起電極３２と素子電極５２とをＳｎ－Ａｕ接続により電気的に接続してもよい。この他、素子電極５２の上にＡｕ／Ｎｉ層５４に代えてＣｕ層を形成し、このＣｕ層と突起電極３２とをＣｕ－Ｃｕ接続により直に接合してもよい。これらの接合方法によれば、Ａｕの使用量を減らすことができ、半導体モジュールの製造コストを低減することができる。Ｓｎは容易に変形する材料であるため、Ａｕ／Ｎｉ層に代えてＳｎめっき層を用いる場合には、突起電極３２の高さのばらつきがＳｎ層が変形することにより吸収される。このため、突起電極３２の高さのばらつきに起因する半導体モジュールの製造歩留まりの低下を抑制することができる。
（太陽電池の構成）
　以下に、本発明を太陽電池に採用した場合の実施の形態を示す。
　図１２は従来の太陽電池の断面図を示し、図１３は本発明を太陽電池に採用した場合の実施の形態を示す。
　まず、図１２において、太陽電池の構造について説明する。
　図１２は、従来のｐｉｎ型非晶質太陽電池の断面構造を模式的に表わしたものである。
　図１２において、４００は太陽電池本体、４５１は基体、４５２は下部電極、４５３はｎ型半導体層、４５４はｉ層、４５５はｐ層、４５６は透明電極、４５７はパッシベーション層、４５８は上部電極、４５９は集電電極、４６０はバスバーを表す。なお、光は図の上部から入射する構造である。
　基体４５１は、例えばＦｅ、Ｎｉ、Ｃｒ、Ａｌ、Ｍｏ、Ａｕ、Ｐｔ、Ｐｂ等の金属またはこれらの合金などの導電性のものでも良く、あるいはポリエステル、ポリエチレン、ポリカーポネート、セルロースアセテート、ポリプロピレン、ポリ塩化ビニル、ポリ塩化ビニリデン、ポリスチレン、ポリアミド、ポリイミド、エポキシ等の耐熱性合成樹脂のフィルムまたはシート、ガラス、セラミックスなどの電気絶縁性のものでも良い。
　基体４５１が電気絶縁性である場合には、堆積膜の形成される側の表面にＡｌ、Ａｇ、Ｐｔ、Ａｕ、Ｔｉ、Ｗ、Ｆｅ、Ｃｒ、Ｃｕ、ステンレス、ＳｎＯ2、Ｉｎ2Ｏ3、ＺｎＯ、ＩＴＯ等のいわゆる金属単体又は合金、及び透明導電性酸化物（ＴＣＯ）を、例えばメッキ、蒸着、スパッタ等の方法を用い下部電極１０２を形成する。
　ｎ層４５３、ｉ層４５４、ｐ層４５５は通常の半導体製造プロセスに依って作製されるもので、例えば蒸着法、スパッタ法、ＣＶＤ法等を用いることより作製する。
　本発明の太陽電池において好適に用いられるｉ層４５４を構成する半導体材料としては、アモルファスシリコン等が挙げられる。
　本光起電力素子において好適に用いられるｐ層４５５またはｎ層４５３を構成する半導体材料としては、前述したｉ層４５４を構成するアモルファスシリコンに価電子制御剤をドーピングすることによって得られる。
　また、透明電極１０６としては、太陽や白色蛍光灯等からの光を半導体層内に効率良く吸収させるために光の透過率が高い（例えば９０％以上）ことが望ましく、材料としてはＳｎＯ2、Ｉｎ2Ｏ3、ＺｎＯ、ＩＴＯなどの金属酸化物が挙げられる。
　さらに、パッシベーション層４５７は、欠陥部分が上部電極４５８、集電電極４５９及びバスバー４６０に接触することを防ぐための絶縁性材料である。また、パッシベーション層４５７は、半導体層全面に積層されるものであるため太陽光の入射を妨げないように光透過性の材料である必要がある。また、太陽電池として屋外で使用する場合の環境を考え、耐候性が良く、熱、湿度及び光に対する安定性が要求される。また、場合によっては、太陽電池が曲げられたり衝撃が与えられるため、機械的な強度も合わせ持つ必要がある。このような材料としては高分子樹脂が好適であり、具体的にはポリエステル、エチレン酢酸ビニル共重合体、アクリル樹脂、エポキシ樹脂、ウレタン等が用いられる。また、膜厚としては、電気的絶縁性が保たれ、かつ、光透過性を損なわれない膜厚であればよい。例えば３μｍ～５μｍである。  
　上部電極４５８は、機能上は集電電極４５８と同様の機能を果たすものである。電極材料としてはＡｇ、Ｐｔ、Ｃｕ、Ｃ等の金属等が挙げられる。
　バスバー５６０は、集電電極４５９を流れる電流を更に集めるための電極である。電極材料としては、例えばＡｇ、Ｐｔ、Ｃｕ、等の金属が用いられる。
　以下、実施例により、本発明の太陽電池の構成を更に詳しく説明するが、本発明はこれらの実施例により限定されるものではない。    
　（太陽電池の製造方法）
　図１３に示すように、本発明の層構成の太陽電池を次のようにして作製する。図１３（Ａ）は、図１３（Ｂ）に示す太陽電池の斜視図に示すＡ－Ａ’線に沿った断面図である。
　まず、ＳＵＳ基板２０ｃｍ角、厚み０．１ｍｍ程度）５５１にスパッタ装置にてＣｒを約１５００Å堆積し、下部電極５５２を形成する。その基板５５１をプラズマＣＶＤ成膜装置にてｎ層５５３、ｉ層５５４、ｐ層５５５の順に堆積を行う。その後、蒸着装置にてＩｎとＳｎの合金を蒸着し、反射防止効果を兼ねた機能を有する透明電極５５６を約７００Å堆積した。
　次に、パッシベーション層５５７を堆積した後、基板５５１をスクリーン印刷法にて、幅約１００μｍ、長さ８ｃｍの上部電極５５８を問隔１ｃｍで印刷する。
　そして、上述の図２～図４に示す工程によって形成された基材３００を備えた素子搭載用基板１２をパッシべーション層５５７に圧着して貼り合わせる。なお、本実施の形態においては、素子搭載用基板３２は、銅板に一体的に形成された突起電極３２（その表面にはＡｕ／Ｎｉ３４で覆われている）を備えた銅板であり、その銅板は、太陽電池の上部電極と集電電極の機能を兼ね備えている（以下、上部電極５５８と称する）。
　また、本発明においては、パッシベーション層５５７の材料としては、上述の図２～４における絶縁樹脂層２０と同様のものを採用する。すなわち、加圧により流動性を有する絶縁樹脂を用いる。
　具体的な圧着による貼り合わせは、形成したパッシべーション層５５７に上部電極５５８の突起電極３２を正対させて基板５５１側と上部電極５５８側から加圧をする。そうすると、突起電極３２が樹脂からなるパッシべーション層５５７を貫通して透明電極５５６に到達することで、突起電極３２と透明電極５５６との電気的接続が可能となる。
　ここで、図１２に従来の太陽電池の構造を示す。
　従来の構造において、透明電極の上に形成したパッシべーション層４５７は絶縁性または高抵抗であるため、その上に上部電極４５８を積層してもその上部電極４５８と透明電極４５６とのオーミックコンタクトは充分ではなく、集電電極４５９に充分に電流を流すことができない。そのため、上部電極４５８と透明電極４５６とが充分に接触するようにする必要がある。具体的には、パッシべーション層４５７に溶剤又は高分子樹脂の未反応成分を含有する導電性ペーストを含ませ、それにより、パッシべーション層４５７を溶解し導電性フィラーが透明電極４５６に接触するようにしている。
　これに対して、本発明によれば、パッシべーション層５５７に導電ペーストを含有させることなく、上部電極５５８に形成された突起電極３２が、加圧によりパッシべーション層５５７を貫通して透明電極５５６に到達し、突起電極３２と透明電極５５６とが電気的に接続させることができる。
　図１１３（Ａ）、（Ｂ）に示すように、上部電極５５８を透明電極５５６と電気的に接続した後、上部電極５５８の上方に例えばＡｇ、Ｐｔ、Ｃｕ、等の金属からなるバスバー５６０を形成する。これによって、太陽電池が完成する。
１０　半導体モジュール、１２　素子搭載用基板、２０　絶縁樹脂層、３０　配線層、３２　突起電極、５０　半導体基板、５２　素子電極、５６、保護層、７０　保護層、１００　半導体素子、５５８　上部電極。
　本発明に係る素子搭載用基板に半導体素子が搭載された半導体モジュールおよび半導体モジュールの製造方法によれば、配線層を形成するための金属板のハンドリングを容易にし、半導体モジュールの製造プロセスを簡略化することができる。

Claims (8)

  1. 　絶縁樹脂層と、
    　前記絶縁樹脂層の一方の主表面に設けられた配線層と、
    　前記配線層から前記絶縁樹脂層側に突出している突起電極と、
    　前記突起電極に対向する素子電極が設けられた半導体素子と、
    　を備え、
    　前記配線層の端面が、半導体素子に近づくにつれて配線層の形成領域の内側に入り込むようなテーパー状であり、
    　前記突起電極が前記絶縁樹脂層を貫通し、前記突起電極と前記素子電極とが電気的に接続されていることを特徴とする半導体モジュール。
  2. 　前記突起電極は、前記配線層の端面の傾斜方向と同じ方向に傾斜していることを特徴とする請求項１に記載の半導体モジュール。
  3. 　基材に保持された金属板を選択的に除去して、基板電極が設けられた配線層を形成する工程と、
    　前記基板電極の頂部面自体または前記基板電極の頂部面に設けられた金属層が露出するように、前記基材の上に絶縁樹脂層を形成して、前記配線層、前記基板電極および前記絶縁樹脂層を含む素子搭載用基板を形成する工程と、
    を備えていることを特徴とする半導体モジュールの製造方法。
  4. 　前記素子搭載用基板を形成する工程の後に、更に、前記基板電極の頂部面自体または前記基板電極の頂部面に設けられた金属層と、前記素子搭載用基板に対向して設けられる半導体素子に設けられた素子電極と、が電気的に接続するように、前記基材に保持された状態の前記素子搭載用基板と前記半導体素子とを圧着する工程と、
    　前記基材を除去する工程と、
    　を備えることを特徴とする請求項３に記載の半導体モジュールの製造方法。
  5. 　前記配線層を形成する工程において、前記配線層は、その端面が、半導体素子に近づくにつれて配線層の形成領域の内側に入り込むようなテーパー状にする工程を含むことを特徴とする請求項２乃至４のいずれか１項に記載の半導体モジュールの製造方法。
  6. 　前記基板電極が前記金属板を選択的に除去することによって前記配線層と一体的に形成された突起電極である請求項２乃至５のうちいずれか１項に記載の半導体モジュールの製造方法。
  7. 　前記基材が透明であり、
    　前記素子搭載用基板を前記半導体素子に圧着する際に、前記基材を通して前記半導体素子の位置を確認して、前記素子搭載用基板と前記半導体素子とを位置合わせする請求項２乃至６のいずれか１項に記載の半導体モジュールの製造方法。
  8. 　前記半導体素子に前記素子搭載用基板を圧着し、前記基材を除去した後、前記絶縁樹脂層を除去し、前記絶縁樹脂層に代えて前記絶縁樹脂層と機能が異なる別の絶縁樹脂層を形成する工程を備える請求項２乃至７のいずれか１項に記載の半導体モジュールの製造方法。
PCT/JP2011/062536 2010-05-31 2011-05-31 半導体モジュールおよび半導体モジュールの製造方法 WO2011152424A1 (ja)

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