WO2011149017A1 - 半導体モジュール基板および半導体モジュール - Google Patents

半導体モジュール基板および半導体モジュール Download PDF

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Publication number
WO2011149017A1
WO2011149017A1 PCT/JP2011/062092 JP2011062092W WO2011149017A1 WO 2011149017 A1 WO2011149017 A1 WO 2011149017A1 JP 2011062092 W JP2011062092 W JP 2011062092W WO 2011149017 A1 WO2011149017 A1 WO 2011149017A1
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Prior art keywords
lead electrode
insulating substrate
substrate
semiconductor module
insulating
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PCT/JP2011/062092
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English (en)
French (fr)
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植田　義明
清茂 宮脇
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京セラ株式会社
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Publication of WO2011149017A1 publication Critical patent/WO2011149017A1/ja

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    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13062—Junction field-effect transistor [JFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • the present invention relates to, for example, an insulating substrate on which a semiconductor element is mounted and a semiconductor module substrate having a lead electrode, and a semiconductor module in which a semiconductor element is mounted on the semiconductor module substrate and modularized.
  • Some semiconductor modules have a semiconductor element and a lead electrode mounting portion provided on the same insulating substrate on a metal substrate.
  • Such a semiconductor module is disclosed in, for example, Japanese Patent Application Laid-Open No. 2009-070863.
  • An object of the present invention is to provide a semiconductor module substrate and a semiconductor module in which the bondability between a metal substrate and an insulating substrate is improved.
  • a semiconductor module substrate is provided with a metal substrate, a first insulating substrate provided on the metal substrate, and a space between the first insulating substrate and the metal substrate. And a second insulating substrate. Further, the semiconductor module substrate is provided on the first insulating substrate, has a bent portion in a side view, and extends on the first lead electrode and the second insulating substrate. And a second lead electrode that is symmetrical to the first lead electrode when viewed from the side.
  • a semiconductor module according to an embodiment of the present invention is mounted on the semiconductor module substrate and the first insulating substrate, and is electrically connected to the first lead electrode and the second lead electrode.
  • a semiconductor element is mounted on the semiconductor module substrate and the first insulating substrate, and is electrically connected to the first lead electrode and the second lead electrode.
  • FIG. 2 is a cross-sectional view of the semiconductor module shown in FIG. 1 taken along line AA.
  • It is an insulating substrate of the semiconductor module which concerns on the modification 1 of 1st Embodiment, Comprising: (A) is a perspective view of an insulating substrate, (B) is a perspective view of the other example of an insulating substrate. It is an insulated substrate of the semiconductor module which concerns on the modification 2 of 1st Embodiment, Comprising: (A) is a perspective view of an insulated substrate, (B) is sectional drawing of an insulated substrate, (C) is another example of an insulated substrate. It is sectional drawing.
  • FIG. 5A is a perspective view of the insulating substrate
  • FIG. 5B is a cross-sectional view of the insulating substrate
  • FIG. 5B It is sectional drawing of the principal part of the semiconductor module which concerns on the modification 5 of 1st Embodiment.
  • FIG. 8 It is an internal outline figure which shows the internal outline of the semiconductor module which concerns on 2nd Embodiment. It is sectional drawing when the semiconductor module shown in FIG. 8 is cut
  • the semiconductor module according to the present embodiment includes a metal substrate 1, a first insulating substrate 3 a bonded to the metal substrate 1 and provided with a first lead electrode 4 a, and the metal substrate 1.
  • a second insulating substrate 3b which is bonded to the first insulating substrate 3a with a second lead electrode 4b provided thereon; a semiconductor element 2 mounted on the first insulating substrate 3a; It has.
  • the semiconductor module substrate includes a metal substrate 1, an insulating substrate 3, and lead electrodes 4. And what provided the semiconductor element 2 in the semiconductor module board
  • the metal substrate 1 is a plate-like member formed in a rectangular shape when viewed in plan, and the first insulating substrate 3a and the second insulating substrate 3b are, for example, silver on the upper main surface of the metal substrate 1. It is joined via a brazing material such as (Ag) brazing or silver (Ag) -copper (Cu) brazing.
  • the metal substrate 1 is made of, for example, a metal material such as copper (Cu), iron (Fe) -nickel (Ni) -cobalt (Co) alloy, or copper (Cu) -tungsten (W) alloy.
  • the thermal expansion coefficient of the metal substrate 1 is set to, for example, 4 (ppm / ° C.) or more and 23 (ppm / ° C.).
  • the metal substrate 1 is manufactured, for example, in a predetermined shape using a known metal working method such as cutting or punching an ingot produced by casting these metal materials into a mold.
  • the metal substrate 1 is a metal having excellent corrosion resistance and good wettability with the brazing material on the outer surface of the metal substrate 1, specifically, a Ni layer having a thickness of 0.5 ( ⁇ m) to 9 ( ⁇ m). Then, an Au layer having a thickness of 0.5 ( ⁇ m) or more and 5 ( ⁇ m) or less is sequentially deposited by a plating method.
  • the plated layer can effectively suppress the metal substrate 1 from being oxidized and corroded, and can firmly adhere and fix the first insulating substrate 3 a and the second insulating substrate 3 b to the upper main surface of the metal substrate 1.
  • the semiconductor element 2 is mounted on the first insulating substrate 3a via the first lead electrode 4a.
  • the semiconductor element 2 is, for example, a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), an IGBT (Insulated Gate Bi-polar Transistor), a Schottky diode, or a JFET (Junction Field Effect Transistor), which is a power semiconductor. Moreover, it is a semiconductor element etc. with a high calorific value.
  • the insulating substrate 3 includes a first insulating substrate 3 a and a second insulating substrate 3 b, and is joined to the upper main surface of the metal substrate 1 with a gap therebetween.
  • the insulating substrate 3 is made of a ceramic material such as alumina ceramics, aluminum nitride ceramics or mullite ceramics, or a mixed material of these ceramic materials.
  • the insulating substrate 3 is made of a material that quickly releases the heat generated by the semiconductor element 2 to the metal substrate 1 and has high insulating properties.
  • the thermal conductivity of the insulating substrate 3 is set to, for example, 16 (w / m ⁇ K) or more and 2000 (w / m ⁇ K) or more.
  • the thermal expansion coefficient of the insulating substrate 3 is set to 3 (ppm / ° C.) or more and 11 (ppm / ° C.), for example.
  • first insulating substrate 3 a and the second insulating substrate 3 b have a metallized layer formed at a position corresponding to a joint portion between the metal substrate 1 and the lead electrode 4.
  • a nickel plating layer having a thickness of 1 ( ⁇ m) or more and 3 ( ⁇ m) or less is formed by a plating method such as electrolytic plating or electroless plating in order to improve wettability with the brazing material. Is attached.
  • the lead electrode 4 is a member for establishing electrical continuity between the semiconductor element 2 in the first insulating substrate 3a of the frame 5 and the outside.
  • the lead electrode 4a is provided on the first insulating substrate 3a.
  • the lead electrode 4b is provided on the second insulating substrate 3b and is electrically connected to the semiconductor element 2 by a bonding wire or the like.
  • the lead electrode 4 is made of, for example, a metal material such as an iron (Fe) -nickel (Ni) -cobalt (Co) alloy or an iron (Fe) -nickel (Ni) alloy. These metal ingots are manufactured to have a predetermined shape by adopting a known metal working method such as a rolling method, a punching method or an etching method.
  • the rigidity of the lead electrode 4 is higher than when the lead electrode 4 is formed by combining a plurality of members. Even if the stress is concentrated on the lead electrode 4, the lead electrode 4 is not easily broken, and the electrical reliability of the lead electrode 4 can be maintained well.
  • the plate is formed by bending, a thermal stress is repeatedly applied to the bent portion, which may cause a crack at the bent portion.
  • the bent portion may be formed into an R shape, or the bending angle of the insulating substrate 3 may be changed. By making the obtuse angle with respect to the upper surface, the thermal stress applied to the bent portion can be reduced, and the electrical reliability of the lead electrode 4 can be maintained well.
  • the lead electrode 4 is a metal having excellent corrosion resistance on the outer surface of the lead electrode 4 and good wettability with the brazing material. Specifically, the thickness is 0.5 ( ⁇ m) or more and 9 ( ⁇ m) or less.
  • the Ni layer and the Au layer having a thickness of 0.5 ( ⁇ m) or more and 5 ( ⁇ m) or less are sequentially deposited by a plating method. The plating layer can effectively prevent the lead electrode 4 from being oxidized and corroded, and can firmly bond and fix the lead electrode 4 and the insulating substrate 3 together. As shown in FIG. 1 or FIG.
  • the lead electrode 4 includes a lead electrode 4 provided in the vicinity of one inner wall surface of the frame 5 in a side view in a region surrounded by the frame 5, and a frame
  • the lead electrode provided in the vicinity of the other inner wall surface of the body 5 is formed to be symmetrical.
  • the shape and location of the lead electrode 4 are made symmetrical so that the thermal stress transmitted to the metal substrate 1 or the insulating substrate 3 is prevented from concentrating on the biased portion.
  • the manufacturing yield of the semiconductor module substrate and the semiconductor module can be improved.
  • the first lead electrode 4a has a lead electrode structure (bending portion) having a stress relaxation function by bending deformation in two stages.
  • the second lead electrode 4b also has a lead electrode structure (bent portion) having a stress relaxation function in two stages.
  • the lead electrode 4 is not limited to two steps, and may have a lead electrode structure (bent portion) bent in a plurality of steps. A structure in which the lead electrode 4 is provided with bent portions at a plurality of locations will be described in a second embodiment to be described later.
  • the first lead electrode 4a is provided at a location in contact with the first insulating substrate 3a.
  • the second lead electrode 4b is provided at a location in contact with the second insulating substrate 3b.
  • the lead electrode 4 is provided at a location in contact with the insulating substrate 3 and a location away from the upper surface of the insulating substrate 3.
  • first lead electrode 4a may be provided across the plurality of insulating substrates 3, and a connecting portion connecting the plurality of insulating substrates 3 may be a bent portion having a stress relaxation function.
  • the lead electrode 4 In the cooling process after the lead electrode 4 and the insulating substrate 3 are joined, the lead electrode 4 has a stress caused by a difference in thermal contraction caused by a difference in thermal expansion coefficient between the lead portion and the metal substrate 1 or a thermal stress when the module is used.
  • the stress generated between the insulating substrate 3 and the metal substrate 1 can be relaxed.
  • first lead electrode 4a and the second lead electrode 4b are respectively located inside the upper surfaces of the first insulating substrate 3a and the second insulating substrate 3b when viewed in plan from the upper main surface side of the metal substrate 1. It is preferable that it is located in. Since the first lead electrode 4a and the second lead electrode 4b are provided inside the first insulating substrate 3a and the second insulating substrate 3b, the first lead electrode 4a and the second lead electrode 4b are provided. Can increase the creeping distance from the metal substrate 1, suppress creeping discharge, and improve the withstand voltage between the electrodes. As a result, the electrical insulation of the semiconductor element 2 is improved, and a decrease in the operability of the semiconductor element 2 can be suppressed. In addition, the semiconductor module can be reduced in size. Further, since the distance between the lead electrodes 4 can be increased, the spatial discharge can be suppressed.
  • the distance between the lead electrode 4 and the outer peripheral portion of the insulating substrate 3 is as follows: A is 0.1 (mm) to 10 (mm) and B is 0.1 (mm) or more 10 (mm) or less, C is set to 0.1 (mm) or more and 10 (mm) or less, and D is set to 0.1 (mm) or more and 10 (mm) or less.
  • the frame 5 may be joined to the upper main surface of the metal substrate 1 so as to surround the first insulating substrate 3a and the second insulating substrate 3b.
  • the frame 5 is made of a metal material such as iron (Fe) -nickel (Ni) -cobalt (Co) alloy or iron (Fe) -nickel (Ni) alloy.
  • the frame 5 is manufactured, for example, by forming an ingot of an iron (Fe) -nickel (Ni) -cobalt (Co) alloy into a predetermined frame shape by a known press process.
  • the frame 5 is made of, for example, a ceramic material such as alumina ceramics, aluminum nitride ceramics, or mullite ceramics, or a dielectric material.
  • the frame body 5 suppresses the sealing resin 6 from flowing to the periphery of the metal substrate 1, uniformly fills the sealing resin 6 inside the frame body 5, and effectively seals the semiconductor module. be able to.
  • a sealing resin 6 is provided on the upper main surface of the metal substrate 1 so as to cover the first insulating substrate 3a and the second insulating substrate 3b, the first lead electrode 4a and the second lead electrode 4b, and the semiconductor element 2. It has been.
  • a sealing resin 6 is provided on the upper main surface of the metal substrate 1 so as to cover the first insulating substrate 3a and the second insulating substrate 3b, the first lead electrode 4a and the second lead electrode 4b, and the semiconductor element 2. Therefore, the electrical reliability of the semiconductor module can be improved. Moreover, the withstand voltage of the semiconductor module can be ensured.
  • the sealing resin 6 is provided so as to fill the inside of the frame body 5.
  • the sealing resin 6 is made of, for example, a resin material such as an epoxy resin or a fluorine resin, or a dielectric material.
  • a structure in which the inside of the frame 5 is hermetically sealed instead of the sealing resin 6 may be used.
  • a structure in which the insulating oil is hermetically sealed in the frame 5 instead of the sealing resin 6 may be used.
  • Fine irregularities are formed on the side surface of the insulating substrate 3, and when the sealing resin 6 is provided in the frame 5, the sealing resin 6 has an anchor effect on the fine irregularities.
  • the adhesiveness between the sealing resin 6 and the insulating substrate 3 is improved, and voids such as voids can be reduced with respect to the surface of the insulating substrate 3, and due to the generation of voids, the temperature of the semiconductor element increases. Loss of function of the semiconductor element can be suppressed.
  • the sealing resin 6 exerts a fixing effect between the respective insulating substrate 3 and the sealing resin 6, and the sealing resin The adhesion between the insulating substrate 3 and the insulating substrate 3 is improved, and generation of voids such as voids due to peeling or the like can be suppressed.
  • a heat sink that dissipates heat from the metal substrate 1 may be provided on the lower surface of the metal substrate 1.
  • the heat sink may be a forced cooling method in which a cooling medium such as water or air flows inside the heat sink, or may be a natural air cooling method in which a metal plate is simply disposed.
  • a heat sink can be used.
  • the metal plate may be formed by alternately stacking a plurality of copper, molybdenum, or tungsten layers.
  • the bonding area between each insulating substrate 3 and the metal substrate 1 can be reduced.
  • the thermal stress generated due to the difference in thermal expansion coefficient between the insulating substrate 3 and the metal substrate 1 due to the heat generation of the semiconductor element 2 can be reduced, and the insulating substrate 3 is peeled off, cracked, or insulated from the metal substrate 1.
  • substrate 3, a crack, etc. can be suppressed.
  • the semiconductor elements 2 are individually mounted on the insulating substrate 3, the heat generated in the semiconductor elements 2 is not easily transmitted to other semiconductor elements 2, and the temperature rise due to mutual thermal interference of the semiconductor elements 2. The resulting thermal destruction can be suppressed.
  • warpage deformation of the metal substrate 1 can be suppressed, and when a heat sink is joined to the metal substrate 1, the adhesion with the metal substrate 1 is improved and heat can be efficiently radiated.
  • the metal substrate 1 is formed into a predetermined shape by using a known metal working method such as cutting or punching an ingot produced by casting an iron (Fe) -nickel (Ni) -cobalt (Co) alloy into a mold. Is produced.
  • the green sheet is made of a raw material powder such as aluminum oxide, silicon oxide, magnesium oxide, calcium oxide, an organic binder, a plasticizer, a solvent, and a dispersant. Etc. are mixed and added to form a paste, which is formed by a doctor blade method, a calender roll method or the like. It is manufactured according to each shape by punching a flat green sheet using a mold.
  • the insulating substrate 3 is printed by applying a conductive paste obtained by adding an organic binder, a plasticizer, a solvent, etc. to a high melting point metal powder such as tungsten, molybdenum, or manganese on a predetermined position on the upper surface of the insulating substrate 3 by a screen printing method or the like. Then, a metallized layer is formed at a position corresponding to a joint portion between the metal substrate 1 and the insulating substrate 3.
  • the insulating substrate 3 is manufactured after firing by firing the green sheet at a temperature of about 1600 ° C.
  • a nickel plating layer having a thickness of 1 ( ⁇ m) to 3 ( ⁇ m) is formed on the metallized layer by a plating method such as electrolytic plating or electroless plating.
  • the lead electrode 4 is formed into a predetermined shape by using a known metal working method such as cutting or punching an ingot produced by casting an iron (Fe) -nickel (Ni) -cobalt (Co) alloy into a mold. Is produced.
  • a known metal working method such as cutting or punching an ingot produced by casting an iron (Fe) -nickel (Ni) -cobalt (Co) alloy into a mold. Is produced.
  • the metal substrate 1, the insulating substrate 3, and the lead electrode 4 are joined via a brazing material such as silver (Ag) brazing or silver (Ag) -copper (Cu) brazing to produce an element housing package.
  • a brazing material such as silver (Ag) brazing or silver (Ag) -copper (Cu) brazing to produce an element housing package.
  • the first lead electrode 4a and the semiconductor element 2 are made of a material such as gold (Au) -tin (Sn) solder or gold (Au) -germanium (Ge) solder. Bonded and fixed. Then, a semiconductor module is manufactured.
  • the upper main surface of the metal substrate 1 is sealed with a sealing resin 6 so as to cover the insulating substrate 3, the lead electrode 4, and the semiconductor element 2.
  • the sealing resin 6 is filled inside the frame body 5.
  • the corners of the adjacent side surfaces may be chamfered in the shape of an R surface or a C surface.
  • the insulating substrate 3 has its corners between adjacent side surfaces of the insulating substrate 3 chamfered in the shape of an R surface.
  • the insulating substrate 3 has chamfered corners between adjacent side surfaces of the insulating substrate 3 in the shape of a C surface.
  • the corners between the adjacent side surfaces of the insulating substrate 3 are chamfered in the shape of the R surface or the C surface, the creeping distance becomes long, so that the creeping discharge between the lead electrode 4 and the metal substrate 1 is suppressed. be able to. As a result, a decrease in the operability of the semiconductor element 2 can be suppressed.
  • the shape of the R surface is preferably set such that, for example, the radius of curvature is 0.3 (mm) or more and 5 (mm) or less.
  • the length of a side is set to 0.3 (mm) or more and 5 (mm) or less, for example.
  • the chamfering of the shape of the R surface or the C surface is formed by punching the R surface or the C surface on a green sheet.
  • the metal substrate 1 of the insulating substrate 3 depends on the difference in thermal expansion coefficient between the metal substrate 1 and the insulating substrate 3. It is possible to suppress the occurrence of cracks and the like at the corners of the joint surface.
  • the corners between the adjacent side surfaces of the insulating substrate 3 are chamfered in the shape of the R surface or the C surface, the bonding area between the metal substrate 1 and the insulating substrate 3 can be reduced, and the metal substrate 1 The thermal stress caused by the difference in thermal expansion coefficient between the insulating substrate 3 and the insulating substrate 3 can be reduced. As a result, peeling of the insulating substrate 3 from the metal substrate 1 can be suppressed.
  • the insulating substrate 3 of the semiconductor module according to the present embodiment may be chamfered in the shape of an R surface at the corner between the adjacent upper surface and side surface. Since the insulating substrate 3 is chamfered in the shape of an R surface at the corners of the adjacent upper surface and side surfaces, the creeping distance between the lead electrode 4 and the metal substrate 1 is increased, thereby suppressing creeping discharge. it can.
  • the insulating substrate 3 is chamfered in the shape of the R surface at the corner between the adjacent upper surface and side surface, when sealing with the sealing resin 6, the insulating substrate 3 is sealed from the upper surface to the side surface.
  • the fluidity of the resin 6 is improved, generation of voids such as voids between the insulating substrate 3 and the sealing resin 6 can be suppressed, and the sealing performance can be improved.
  • the radius of curvature of the R surface is set to 0.3 (mm) or more and 0.5 (mm) or less.
  • the insulating substrate 3 can obtain the same effect even if the corners between the adjacent upper surface and side surface are chamfered into a C-surface shape.
  • the length of a side is set to 0.3 (mm) or more and 5 (mm) or less, for example.
  • the shape of the R or C surface is formed by punching a green sheet. Alternatively, it may be formed by polishing or the like in the shape of the R or C surface after sintering.
  • the insulating substrate 3 has corners between adjacent upper and side surfaces chamfered in the shape of an R surface, and the side surfaces are directed from the upper surface to the lower surface. It may be a widened inclined surface. Since the creepage distance between the lead electrode 4 and the metal substrate 1 is further increased, the creeping discharge can be further suppressed.
  • the insulating substrate 3 has an inclined surface in which the corner portion between the adjacent upper surface and side surface is chamfered in the shape of an R surface and the side surface extends from the upper surface to the lower surface, the insulating substrate 3 is sealed with the sealing resin 6.
  • the fluidity of the sealing resin 6 with respect to the insulating substrate 3 is further improved, generation of voids such as voids between the insulating substrate 3 and the sealing resin 6 can be suppressed, and the sealing property is improved. can do.
  • the shape of the R surface for example, the radius of curvature is set to 0.05 (mm) or more and 0.5 (mm) or less.
  • the insulating substrate 3 has an inclined surface in which corners between adjacent upper surfaces and side surfaces are chamfered in the shape of a C surface, and the side surfaces extend from the upper surface to the lower surface. Even if it becomes, the same effect can be acquired.
  • the shape of C surface the length of a side is set to 0.05 (mm) or more and 0.5 (mm) or less, for example.
  • the insulating substrate 3 of the semiconductor module according to the present embodiment may be chamfered in the shape of an R surface at the corners between the adjacent lower surface and side surface. Since the corners between the adjacent side surfaces and the lower surface of the insulating substrate 3 are chamfered in the shape of the R surface, the creeping distance between the lead electrode 4 and the metal substrate 1 is increased, so that creeping discharge can be suppressed.
  • the insulating substrate 3 is chamfered in the shape of the R surface, the adjacent lower side surface and side corners are chamfered, the bonding area between the insulating substrate 3 and the metal substrate 1 can be reduced, and the amount of thermal expansion Occurrence of peeling or cracking due to the difference can be suppressed.
  • the sealing resin 6 and the metal substrate are bonded to each other depending on the shape of the R surface. 1 can be improved.
  • the radius of curvature of the R surface is set to 0.05 (mm) or more and 0.5 (mm) or less.
  • the insulating substrate 3 can obtain the same effect even if the corners between the adjacent lower surface and side surface are chamfered into a C-surface shape.
  • the length of a side is set to 0.05 (mm) or more and 0.5 (mm) or less, for example.
  • the insulating substrate 3 has a corner portion between the adjacent upper surface and the side surface of the insulating substrate 3 chamfered in the shape of an R surface or a C surface, and a corner portion between the adjacent lower surface and the side surface of the insulating substrate 3. It may be chamfered in the shape of the R surface or the C surface.
  • the metal plate 7 may be disposed between the metal substrate 1 and the insulating substrate 3.
  • the metal plate 7 is bonded to a position facing the lead electrode 4 on the insulating substrate 3.
  • the metal plate 7 is provided with the same material as the lead electrode 4 and has substantially the same area as the area where the lead electrode 4 is bonded to the insulating substrate 3.
  • the metal substrate 1 and the metal plate 7 are metallic materials, they can be elastically deformed to relieve stress. Thereby, the stress balance of the lead electrode 4 and the metal plate 7 can be taken, and the curvature deformation of the insulated substrate 3 can be suppressed. As a result, it is possible to prevent the insulating substrate 3 from being cracked or peeled off.
  • the metal plate 7 can be increased in the creeping distance by being disposed inside the insulating substrate 3 when viewed in plan, and creeping discharge can be suppressed.
  • Second Embodiment The present invention is not limited to the first embodiment described above, and various modifications and improvements can be made without departing from the scope of the present invention.
  • a second embodiment will be described. Note that, in the semiconductor module according to the second embodiment, portions similar to those of the semiconductor module according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted as appropriate.
  • the semiconductor module according to the second embodiment is provided with a gap between the metal substrate 1, the first insulating substrate 3ax provided on the metal substrate 1, and the first insulating substrate 3ax on the metal substrate 1.
  • the first insulating substrate 3ax, the first lead electrode 4ax having a bent portion in side view and extending upward, and the second insulating substrate 3bx A first lead electrode 4ax and a second lead electrode 4bx that is bilaterally symmetric when viewed from the side are provided.
  • the semiconductor module according to the second embodiment is provided with the metal plate 7 on each of the insulating substrates 3.
  • the semiconductor element 2 and the lead electrode 4 are provided on the metal plate 7. Since the metal substrate 1 and the metal plate 7 are metallic materials, it is possible to suppress the occurrence of cracks or peeling on the insulating substrate 3 by sandwiching the insulating substrate 3 between them. A semiconductor module substrate and a semiconductor module with excellent performance can be provided.
  • the first lead electrode 4ax is provided on the edge of the first insulating substrate 3ax that is separated from the second insulating substrate 3bx.
  • the second lead electrode 4bx is provided on the edge of the second insulating substrate 3bx that is separated from the first insulating substrate 3ax. That is, as shown in FIG. 8 or FIG. 9, the lead electrode 4 is a first lead electrode 4 ax provided in the vicinity of one inner wall surface of the frame 5 in a side view in the region surrounded by the frame 5.
  • the second lead electrode 4bx provided in the vicinity of the other inner wall surface of the frame 5 is formed so as to be symmetrical.
  • the concentration of the thermal stress applied to the semiconductor module substrate can be reduced.
  • the thermal stress can be relieved in the entire semiconductor module substrate, and the manufacturing yield of the semiconductor module substrate can be improved.
  • the distance between the lead electrodes 4 can be increased, the spatial discharge in the region surrounded by the frame body 5 can be suppressed, and a semiconductor module having excellent electrical reliability can be provided.
  • a third lead electrode 4cx and a fourth lead electrode 4dx that overlap the first lead electrode 4ax in a side view are further provided on the first insulating substrate 3ax.
  • any two lead electrodes 4 of the first lead electrode 4ax, the third lead electrode 4cx, or the fourth lead electrode 4dx located at both ends on the first insulating substrate 3ax are set in the same shape.
  • the lead electrode 4 is formed on the semiconductor module substrate by making the lead electrodes 4 provided in the vicinity of the four corners of the frame body 5 in the region surrounded by the frame body 5 the same shape.
  • a plurality of bent portions are provided on the lead electrode 4.
  • the stress relaxation function can be effectively exhibited.
  • the bent portion is provided at a position lower than the height position of the upper end of the frame body 5.
  • the lead electrode 4 can be made difficult to float from the first insulating substrate 3a by biting into the first insulating substrate 3a. As a result, the lead electrode 4 is less likely to be peeled off from the first insulating substrate 3a, and the lead electrode 4 is less likely to be disconnected at the junction between the lead electrode 4 and the first insulating substrate 3a. An excellent semiconductor module can be realized.
  • first lead electrode 4ax and the second lead electrode 4bx are arranged to face each other, and the first lead electrode 4ax and the second lead electrode 4bx are along a virtual line connecting the both.
  • a through hole H penetrating in the direction is provided.
  • the lead electrode 4 By providing the lead electrode 4 with the through hole H, the lead electrode 4 and the other electrode can be screwed to the lead electrode 4 through a bolt or a nut. The connection can be maintained satisfactorily, and a semiconductor module substrate with an excellent manufacturing yield can be provided.
  • the through hole H of the lead electrode 4 can be an elliptical through hole Hx or a through hole Hy in which the four corners of the hole H are R. Further, in place of the through hole H, notches Nx and Ny can be formed in the lead electrode 4.

Abstract

　半導体モジュール基板であって、金属基板１と、金属基板１上に設けられた第１の絶縁基板３ａと、金属基板１上に第１の絶縁基板３ａと間を空けて設けられた第２の絶縁基板３ｂと、を備えている。さらに、半導体モジュール基板は、第１の絶縁基板３ａ上に設けられ、側面視して折り曲げ部を有し、上方に向かって延びた第１のリード電極４ａと、第２の絶縁基板３ｂ上に設けられ、側面視して第１のリード電極４ａと左右対称となる第２のリード電極４ｂと、を備えている。

Description

半導体モジュール基板および半導体モジュール
　本発明は、例えば、半導体素子を搭載する絶縁基板とリード電極を備えた半導体モジュール基板、および半導体モジュール基板に半導体素子を搭載し、モジュール化された半導体モジュールに関する。
　半導体モジュールにおいて、金属基板上の同一の絶縁基板上に半導体素子およびリード電極の搭載部が設けられているものがある。このような半導体モジュールとしては、例えば、特開２００９－０７０８６３号公報に開示されている。
　しかしながら、半導体モジュールは、半導体素子およびリード電極の搭載部が同一の絶縁基板上に設けられているため、金属基板と絶縁基板との間で熱膨張量差によるクラックまたは剥がれ等が発生しやすいという問題があった。
　本発明の目的は、金属基板と絶縁基板との接合性が向上した半導体モジュール基板および半導体モジュールを提供することである。
　本発明の一実施形態に係る半導体モジュール基板は、金属基板と、前記金属基板上に設けられた第１の絶縁基板と、前記金属基板上に前記第１の絶縁基板と間を空けて設けられた第２の絶縁基板とを備えている。さらに、半導体モジュール基板は、前記第１の絶縁基板上に設けられ、側面視して折り曲げ部を有し、上方に向かって延びた第１のリード電極と、前記第２の絶縁基板上に設けられ、側面視して前記第１のリード電極と左右対称となる第２のリード電極とを備えている。
　また、本発明の一実施形態に係る半導体モジュールは、前記半導体モジュール基板と、前記第１の絶縁基板に搭載されるとともに、前記第１のリード電極および前記第２のリード電極に電気的に接続された半導体素子とを備えている。
第１実施形態に係る半導体モジュールの内部の概観を示す内部概観図である。 図１に示す半導体モジュールをＡ－Ａ線で切断したときの断面図である。 第１実施形態の変形例１に係る半導体モジュールの絶縁基板であって、（Ａ）は絶縁基板の斜視図、（Ｂ）は絶縁基板の他の例の斜視図である。 第１実施形態の変形例２に係る半導体モジュールの絶縁基板であって、（Ａ）は絶縁基板の斜視図、（Ｂ）は絶縁基板の断面図、（Ｃ）は絶縁基板の他の例の断面図である。 第１実施形態の変形例３に係る半導体モジュールの絶縁基板であって、（Ａ）は絶縁基板の斜視図、（Ｂ）は絶縁基板の断面図、（Ｃ）は絶縁基板の他の例の断面図である。 第１実施形態の変形例４に係る半導体モジュール絶縁基板であって、（Ａ）は絶縁基板の斜視図、（Ｂ）は絶縁基板の断面図、（Ｃ）は絶縁基板の他の例の断面図である。 第１実施形態の変形例５に係る半導体モジュールの要部の断面図である。 第２実施形態に係る半導体モジュールの内部の概観を示す内部概観図である。 図８に示す半導体モジュールをＢ－Ｂ線で切断したときの断面図である。 第２実施形態の変形例６に係るリード電極の正面図である。
　以下、本発明の一実施形態に係る半導体モジュールについて、図面を参照しながら説明する。
　≪第１実施形態≫
　　＜半導体モジュールの構成＞
　本実施形態に係る半導体モジュールは、図１に示すように、金属基板１と、金属基板１上に接合され、第１のリード電極４ａが設けられた第１の絶縁基板３ａと、金属基板１上に第１の絶縁基板３ａと間を空けて接合され、第２のリード電極４ｂが設けられた第２の絶縁基板３ｂと、第１の絶縁基板３ａ上に搭載された半導体素子２と、を備えている。なお、半導体モジュール基板は、金属基板１と、絶縁基板３およびリード電極４を備えたものである。そして、半導体モジュール基板に半導体素子２を設けたものが、半導体モジュールである。
　金属基板１は、平面視したとき、矩形状に形成された板状の部材であり、金属基板１の上側主面に、第１の絶縁基板３ａおよび第２の絶縁基板３ｂが、例えば、銀（Ａｇ）ロウまたは銀（Ａｇ）－銅（Ｃｕ）ロウ等のロウ材を介して接合される。金属基板１は、例えば、銅（Ｃｕ）、鉄（Ｆｅ）－ニッケル（Ｎｉ）－コバルト（Ｃｏ）合金または銅（Ｃｕ）－タングステン（Ｗ）合金等の金属材料から成る。金属基板１の熱膨張係数は、例えば、４（ｐｐｍ／℃）以上２３（ｐｐｍ／℃）に設定される。
　金属基板１は、例えば、それらの金属材料を型枠に鋳込んで作製したインゴットを周知の切削加工または打ち抜き加工等の金属加工法を用いて所定の形状にして製作される。
　金属基板１は、金属基板１の外表面に耐蝕性に優れ、かつロウ材との濡れ性が良い金属、具体的には、厚さ０．５（μｍ）以上９（μｍ）以下のＮｉ層と厚さ０．５（μｍ）以上５（μｍ）以下のＡｕ層を順次、メッキ形成法によりメッキ層を被着させておく。メッキ層は金属基板１が酸化腐蝕するのを有効に抑制できるとともに、金属基板１の上側主面に第１の絶縁基板３ａおよび第２の絶縁基板３ｂを強固に接着固定することができる。
　半導体素子２は、第１の絶縁基板３ａに第１のリード電極４ａを介して搭載されている。半導体素子２は、例えば、パワー半導体であるパワーＭＯＳＦＥＴ（Metal-Oxide-Semiconductor　Field-Effect　Transistor）、ＩＧＢＴ（Insulated　Gate　Bi-polar　Transistor）、ショットキーダイオード、ＪＦＥＴ（Junction　Field　Effect　Transistor）等である。また、高発熱量を伴う半導体素子等である。
　絶縁基板３は、図２に示すように、第１の絶縁基板３ａおよび第２の絶縁基板３ｂからなり、金属基板１の上側主面に互いに間を空けて接合されている。絶縁基板３は、例えば、アルミナ質セラミックス、窒化アルミニウム質セラミックスまたはムライト質セラミックス等のセラミック材料、或いはこれらのセラミック材料の混合材料から成る。絶縁基板３は、半導体素子２の発熱をすみやかに金属基板１に逃がし、かつ高い絶縁性を有する材料が用いられる。
　また、絶縁基板３の熱伝導率は、例えば、１６（ｗ／ｍ・Ｋ）以上２０００（ｗ／ｍ・Ｋ）以上に設定される。絶縁基板３の熱膨張係数は、例えば、３（ｐｐｍ／℃）以上１１（ｐｐｍ／℃）に設定される。
　また、第１の絶縁基板３ａおよび第２の絶縁基板３ｂは、金属基板１およびリード電極４との接合部に該当する位置にメタライズ層が形成されている。また、メタライズ層上には、ロウ材との濡れ性を良好にするために、電解メッキまたは無電解メッキ等のメッキ形成方法によって、厚さ１（μｍ）以上３（μｍ）以下のニッケルメッキ層が被着されている。
　リード電極４は、枠体５の第１の絶縁基板３ａ内の半導体素子２と外部との間で電気的に導通をとるための部材である。リード電極４ａは、第１の絶縁基板３ａ上に設けられる。また、リード電極４ｂは、第２の絶縁基板３ｂ上に設けられ、半導体素子２とボンディングワイヤ等で電気的に接続されている。リード電極４は、例えば、鉄（Ｆｅ）－ニッケル（Ｎｉ）－コバルト（Ｃｏ）合金または鉄（Ｆｅ）－ニッケル（Ｎｉ）合金等の金属材料から成る。これらの金属のインゴットを周知の圧延加工法、打ち抜き加工法またはエッチング加工法等の金属加工法を採用することによって、所定の形状となるように製作される。なお、リード電極４は、これらの金属加工法を用いることで、板体を折り曲げて形成した場合は、リード電極４を複数の部材を組み合わせて作製した場合に比べて、リード電極４の剛性を良好に維持することができ、リード電極４に応力が仮に集中したとしても、リード電極４が破壊されにくく、リード電極４の電気的信頼性を良好に維持することができる。さらに、板体を折り曲げて形成する場合は、折り曲げ個所に熱応力が繰り返し加わることで、該個所にクラックが発生する虞があるが、折り曲げ個所をＲ形状にしたり、折り曲げ角度を絶縁基板３の上面に対して鈍角にすることによって、折り曲げ個所に加わる熱応力を低減することができ、リード電極４の電気的信頼性を良好に維持することができる。
　なお、リード電極４は、リード電極４の外表面に耐蝕性に優れ、かつロウ材との濡れ性が良好な金属、具体的には、厚さ０．５（μｍ）以上９（μｍ）以下のＮｉ層と厚さ０．５（μｍ）以上５（μｍ）以下のＡｕ層を順次、メッキ形成法によりメッキ層を被着させる。メッキ層はリード電極４が酸化腐蝕するのを有効に防止できるとともに、リード電極４と絶縁基板３とを強固に接着固定することができる。なお、リード電極４は、図１または図２に示すように、枠体５で囲まれる領域内において、側面視して枠体５の一方内壁面の近傍に設けられたリード電極４と、枠体５の他方内壁面の近傍に設けられたリード電極とは、左右対称となるように形成されている。枠体５で囲まれる領域内において、リード電極４の形状および配置場所を左右対称となるようにすることで、金属基板１または絶縁基板３に伝わる熱応力が偏った個所に集中するのを抑制することができ、半導体モジュール基板および半導体モジュールの製造歩留まりを向上させることができる。
　また、第１のリード電極４ａは、２段にして曲げ変形による応力緩和機能を有するリード電極構造（折り曲げ部）を有している。また、第２のリード電極４ｂも２段にして応力緩和機能を有するリード電極構造（折り曲げ部）を有している。また、リード電極４は、２段に限らず、複数段に曲げたリード電極構造（折り曲げ部）としてもよい。リード電極４が、複数個所に折り曲げ部を設けた構造は、後述する第２実施形態において説明する。なお、第１のリード電極４ａは、図１に示すように、第１の絶縁基板３ａと接する個所に設けられている。また、第２のリード電極４ｂは、図１に示すように、第２の絶縁基板３ｂと接する個所に設けられている。そして、リード電極４に複数の折り曲げ部を設けた場合は、絶縁基板３と接する個所と、絶縁基板３の上面から離れた個所に設けられる。
　また、第１のリード電極４ａは、複数の絶縁基板３上にまたがって設けられており、複数の絶縁基板３を連結する連結個所が、応力緩和機能を有する折り曲げ部になっていてもよい。
　リード電極４は、リード電極４と絶縁基板３との接合後の冷却過程において、リード部と金属基板１との熱膨張係数の違いにより発生する熱収縮差による応力や、モジュール使用時における熱応力を緩和することができ、絶縁基板３と金属基板１の間に生じる応力を緩和することができる。
　また、第１のリード電極４ａおよび第２のリード電極４ｂは、金属基板１の上側主面側から平面視したときに、それぞれ第１の絶縁基板３ａおよび第２の絶縁基板３ｂの上面の内側に位置していることが好ましい。第１のリード電極４ａおよび第２のリード電極４ｂが、第１の絶縁基板３ａおよび第２の絶縁基板３ｂの内側に設けられているので、第１のリード電極４ａおよび第２のリード電極４ｂは、金属基板１との沿面距離が長くなり、沿面放電が抑制され、電極間耐電圧を向上させることができる。これによって、半導体素子２の電気的絶縁性が向上し、半導体素子２の作動性の低下を抑制することができる。また、半導体モジュールを小型化することができる。また、リード電極４間の距離を長くすることができるので、空間放電を抑制することができる。
　また、リード電極４と絶縁基板３の外周部との距離は、図２に示すように、Ａは、０．１（ｍｍ）以上１０（ｍｍ）以下、Ｂは、０．１（ｍｍ）以上１０（ｍｍ）以下、Ｃは、０．１（ｍｍ）以上１０（ｍｍ）以下、Ｄは、０．１（ｍｍ）以上１０（ｍｍ）以下に設定される。
　枠体５が、金属基板１の上側主面に第１の絶縁基板３ａおよび第２の絶縁基板３ｂを取り囲むように接合されていてもよい。枠体５は、例えば、鉄（Ｆｅ）－ニッケル（Ｎｉ）－コバルト（Ｃｏ）合金または鉄（Ｆｅ）－ニッケル（Ｎｉ）合金等の金属材料から成る。枠体５は、例えば、鉄（Ｆｅ）－ニッケル（Ｎｉ）－コバルト（Ｃｏ）合金のインゴットを周知のプレス加工により所定の枠状となすことによって製作される。また、枠体５は、例えば、アルミナ質セラミックス、窒化アルミニウム質セラミックスまたはムライト質セラミックス等のセラミック材料、或いは誘電体材料から成る。
　また、枠体５は、封止樹脂６が金属基板１の周辺部に流れるのを抑制し、枠体５の内側で封止樹脂６を均一に充填し、効果的に半導体モジュールを封止することができる。
　封止樹脂６が、金属基板１の上側主面に第１の絶縁基板３ａおよび第２の絶縁基板３ｂ、第１のリード電極４ａおよび第２のリード電極４ｂ、半導体素子２を覆うように設けられている。封止樹脂６が、金属基板１の上側主面に第１の絶縁基板３ａおよび第２の絶縁基板３ｂ、第１のリード電極４ａおよび第２のリード電極４ｂ、半導体素子２を覆うように設けられるので、半導体モジュールの電気的信頼性を向上させることができる。また、半導体モジュールの耐電圧を確保することができる。
　また、封止樹脂６は、枠体５が設けられた場合には、枠体５の内側を充填するように設けられる。封止樹脂６は、例えば、エポキシ樹脂またはフッ素樹脂等の樹脂材料、或いは誘電体材料から成る。なお、封止樹脂６に置き換えて、枠体５内を気密封止する構造であってもよい。また、封止樹脂６に置き換えて、絶縁用オイルを枠体５内に気密封止する構造であってもよい。
　絶縁基板３の側面には、微細な凹凸が形成されており、枠体５内に封止樹脂６を設けた場合は、封止樹脂６が微細な凹凸に対してアンカー効果を奏する。その結果、封止樹脂６と絶縁基板３との密着性が向上し、絶縁基板３の表面に対してボイド等の空隙を低減することができ、空隙の発生により半導体素子の高温化に伴う、半導体素子の機能喪失を抑制することができる。
　また、第１の絶縁基板３ａおよび第２の絶縁基板３ｂが離間しているので、封止樹脂６は、それぞれの絶縁基板３と封止樹脂６との間において固着効果を及ぼし、封止樹脂６と絶縁基板３との密着性が向上し、剥がれ等によるボイド等の空隙の発生を抑制することができる。
　また、金属基板１の下面には、金属基板１からの熱を放散させるヒートシンクを設けてもよい。ヒートシンクは、例えば、効率よく放熱するために、ヒートシンクの内部を水や空気等の冷却媒体が流れる強制冷却方式であっても、単に金属板を配置した自然空冷方式であってもよく、周知のヒートシンンクを用いることができる。なお、金属板は、銅、モリブデンまたはタングステンの層を複数層交互に積層したものであってもよい。
　本実施形態によれば、金属基板１上に設けられた複数の絶縁基板３が、互いに間を空けて設けられているので、各絶縁基板３と金属基板１との接合面積を小さくすることができ、半導体素子２の発熱によって、絶縁基板３と金属基板１との熱膨張係数の違いに起因して生じる熱応力を低減することができ、金属基板１に対する絶縁基板３の剥離やクラック、絶縁基板３に対するリード電極４の剥離やクラック等の発生を抑制することができる。
　本実施形態によれば、金属基板１の上側主面に接合された第１のリード電極４ａを介して半導体素子２が搭載された第１の絶縁基板３ａと、金属基板１の上側主面に接合された第２のリード電極４ｂが設けられた第２の絶縁基板３ｂとが、互いに離間して接合されているので、第１の絶縁基板３ａと金属基板１、および第２の絶縁基板３ｂと金属基板１との接合面積を小さくすることができ、半導体素子２の発熱によって、絶縁基板３と金属基板１との熱膨張係数の違いで生じる熱膨張量差による剥がれやクラック等の発生を抑制することができる。
　また、半導体素子２が、絶縁基板３にそれぞれ個別に搭載されるので、半導体素子２で発生した熱が、他の半導体素子２に伝わりにくくなり、半導体素子２の相互の熱干渉による温度上昇に起因した熱破壊を抑制することができる。
　また、金属基板１の反り変形を抑制することができ、金属基板１にヒートシンクを接合した場合、金属基板１と密着性が向上し、効率よく放熱することができる。
　＜半導体モジュールの製造方法＞
　ここで、半導体モジュールの製造方法を説明する。
　金属基板１は、例えば、鉄（Ｆｅ）－ニッケル（Ｎｉ）－コバルト（Ｃｏ）合金を型枠に鋳込んで作製したインゴットを周知の切削加工や打ち抜き加工等の金属加工法を用いて所定形状にして製作される。
　また、絶縁基板３は、例えば、酸化アルミニウム質焼結体からなる場合、グリーンシートは、酸化アルミニウム、酸化珪素、酸化マグネシウム、酸化カルシウム等の原料粉末に、有機バインダー、可塑剤、溶剤、分散剤等を混合添加してペースト状とし、ドクターブレード法やカレンダーロール法等によって形成される。平板形状のグリーンシートに金型を用いた打ち抜きを施すことによってそれぞれの形状に合わせて製作される。
　絶縁基板３は、タングステン、モリブデンまたはマンガン等の高融点金属粉末に有機バインダー、可塑剤、溶剤等を添加してなる導電ペーストを、絶縁基板３の上面の所定位置にスクリーン印刷法等によって印刷塗布して、金属基板１および絶縁基板３との接合部に該当する位置にメタライズ層が形成される。
　さらに、グリーンシートを、約１６００℃の温度で焼成することにより、焼成後に、絶縁基板３が製作される。
　また、電解メッキ又は無電解メッキ等のメッキ形成方法によって、メタライズ層上に厚さ１（μｍ）以上３（μｍ）以下のニッケルメッキ層が形成される。
　リード電極４は、例えば、鉄（Ｆｅ）－ニッケル（Ｎｉ）－コバルト（Ｃｏ）合金を型枠に鋳込んで作製したインゴットを周知の切削加工や打ち抜き加工等の金属加工法を用いて所定形状にして製作される。
　金属基板１と絶縁基板３とリード電極４が銀（Ａｇ）ロウまたは銀（Ａｇ）－銅（Ｃｕ）ロウ等のロウ材を介して接合されることによって素子収納用パッケージが製作される。
　素子収納用パッケージの絶縁基板３ａ上に、第１のリード電極４ａおよび半導体素子２が、例えば、金（Ａｕ）－錫（Ｓｎ）半田または金（Ａｕ）－ゲルマニウム(Ｇｅ)半田等の材料で接着固定される。そして、半導体モジュールが製作される。また、金属基板１の上側主面は絶縁基板３、リード電極４および半導体素子２を覆うように封止樹脂６で封止される。また、枠体５を設ける場合は、枠体５の内側に封止樹脂６が充填される。
　本発明は上述の実施の形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良等が可能である。以下、本実施形態の変形例について説明する。なお、本実施形態の変形例に係る半導体モジュールのうち、本実施形態に係る半導体モジュールと同様な部分については、同一の符号を付して適宜説明を省略する。また、下記の変形例を組み合わせた新たな構造については説明を省略するが、当然変形例同士を組み合わせてもよい。
　　＜変形例１＞
　本実施形態に係る半導体モジュールの絶縁基板３は、図３に示すように、絶縁基板３は、隣り合った側面同士の角部がＲ面またはＣ面の形状に面取りされていてもよい。絶縁基板３は、図３（Ａ）に示すように、絶縁基板３の隣り合った側面同士の角部が、Ｒ面の形状に面取りされている。また、絶縁基板３は、図３（Ｂ）に示すように、絶縁基板３の隣り合った側面同士の角部が、Ｃ面の形状に面取りされている。絶縁基板３の隣り合った側面同士の角部が、Ｒ面またはＣ面の形状に面取りされているので、沿面距離が長くなるため、リード電極４と金属基板１の間の沿面放電を抑制することができる。結果として、半導体素子２の作動性の低下を抑制することができる。
　Ｒ面の形状は、例えば、曲率半径が、０．３（ｍｍ）以上５（ｍｍ）以下に設定されることが好ましい。また、Ｃ面の形状は、例えば、辺の長さが、０．３（ｍｍ）以上５（ｍｍ）以下に設定される。また、Ｒ面またはＣ面の形状の面取りは、Ｒ面またはＣ面をグリーンシートに、打ち抜き加工等によって形成しておく。
　絶縁基板３の隣り合った側面同士の角部がＲ面またはＣ面の形状に面取りされているので、金属基板１と絶縁基板３との熱膨張係数の違いによって、絶縁基板３の金属基板１との接合面の角部にクラック等が発生するのを抑制できる。
　また、絶縁基板３の隣り合った側面同士の角部がＲ面またはＣ面の形状に面取りされているので、金属基板１と絶縁基板３との接合面積を小さくすることができ、金属基板１と絶縁基板３との熱膨張係数の違いによって生じる熱応力を低減することができる。その結果、金属基板１に対する絶縁基板３の剥離等を抑制することができる。
　　＜変形例２＞
　本実施形態に係る半導体モジュールの絶縁基板３は、図４（Ａ）、（Ｂ）に示すように、隣り合った上面と側面との角部がＲ面の形状に面取りされていてよい。絶縁基板３が、隣り合った上面と側面との角部がＲ面の形状に面取りされているので、リード電極４と金属基板１との間の沿面距離が長くなるため沿面放電を抑制することできる。
　また、絶縁基板３が、隣り合った上面と側面との角部がＲ面の形状に面取りされているので、封止樹脂６で封止する際、上面から側面にかけて、絶縁基板３に対する封止樹脂６の流動性が向上し、絶縁基板３と封止樹脂６との間にボイド等の空隙の発生を抑制することができ、封止性を向上することができる。
　また、Ｒ面の形状は、例えば、曲率半径が、０．３（ｍｍ）以上０．５（ｍｍ）以下に設定される。
　絶縁基板３は、図４（Ｃ）に示すように、隣り合った上面と側面との角部がＣ面の形状に面取りしても、同様な効果を得ることができる。また、Ｃ面の形状は、例えば、辺の長さが、０．３（ｍｍ）以上５（ｍｍ）以下に設定される。
　また、Ｒ面またはＣ面の形状は、グリーンシートに打ち抜き加工等によって形成しておく。または、焼結後にＲ面またはＣ面の形状に研磨等で形成してもよい。
　　＜変形例３＞
　さらに、絶縁基板３は、図５（Ａ）、（Ｂ）に示すように、隣り合った上面と側面との角部がＲ面の形状に面取りされるとともに、側面が上面から下面に向かって広がる傾斜面となっていてもよい。リード電極４と金属基板１との間の沿面距離がさらに長くなるため沿面放電をさらに抑制することができる。
　また、絶縁基板３が、隣り合った上面と側面との角部がＲ面の形状に面取りされ、側面が上面から下面に向かって広がる傾斜面を有しているので、封止樹脂６で封止する際、絶縁基板３に対する封止樹脂６の流動性がさらに向上し、絶縁基板３と封止樹脂６との間にボイド等の空隙の発生を抑制することができ、封止性を向上することができる。Ｒ面の形状は、例えば、曲率半径が、０．０５（ｍｍ）以上０．５（ｍｍ）以下に設定される。
　また、絶縁基板３は、図５（Ｃ）に示すように、隣り合った上面と側面との角部がＣ面の形状に面取りされるとともに、側面が上面から下面に向かって広がる傾斜面となっていても、同様な効果を得ることができる。また、Ｃ面の形状は、例えば、辺の長さが、０．０５（ｍｍ）以上０．５（ｍｍ）以下に設定される。
　　＜変形例４＞ 
　本実施形態に係る半導体モジュールの絶縁基板３は、図６（Ａ）、（Ｂ）に示すように、隣り合った下面と側面との角部がＲ面の形状に面取りされていてもよい。絶縁基板３の隣り合った側面と下面との角部がＲ面の形状に面取りされているので、リード電極４と金属基板１との沿面距離が長くなるため沿面放電を抑制することができる。
　また、絶縁基板３が、隣り合った下側面と側面の角部がＲ面の形状に面取りされているので、絶縁基板３と金属基板１との接合面積を小さくすることができ、熱膨張量差による剥がれやクラック等の発生を抑制することができる。
　また、絶縁基板３は、絶縁基板３の隣り合った下面と側面との角部がＲ面の形状に面取りされているので、Ｒ面の形状によって、固着効果により、封止樹脂６と金属基板１との密着性を向上することができる。
　また、Ｒ面の形状は、例えば、曲率半径が、０．０５（ｍｍ）以上０．５（ｍｍ）以下に設定される。
　絶縁基板３は、図６（Ｃ）に示すように、隣り合った下面と側面との角部がＣ面の形状に面取りしても、同様な効果を得ることができる。また、Ｃ面の形状は、例えば、辺の長さが、０．０５（ｍｍ）以上０．５（ｍｍ）以下に設定される。
　また、絶縁基板３は、絶縁基板３の隣り合った上面と側面との角部がＲ面またはＣ面の形状に面取りされるとともに、絶縁基板３の隣り合った下面と側面との角部がＲ面またはＣ面の形状に面取りされていてもよい。これによって、リード電極４と金属基板１との沿面距離を長くすることでき、沿面放電をさらに抑制することができる。
　　＜変形例５＞
　本実施形態に係る半導体モジュールは、金属基板１と絶縁基板３との間に金属板７が配置されてもよい。金属板７は、絶縁基板３上のリード電極４と相対する位置に接合されている。また、金属板７は、絶縁基板３上にリード電極４が接合されている面積とほぼ同一の面積で、リード電極４と同一の材料で設けられている。
　金属基板１と金属板７は、互いに金属材料であるため、互いに弾性変形し応力を緩和することができる。これにより、リード電極４と金属板７との応力バランスがとれ、絶縁基板３の反り変形を抑制できる。これによって、絶縁基板３にクラックや剥がれ等が発生するのを抑制することができる。
　また、金属板７は、平面視したときに絶縁基板３の内側に配置することで沿面距離を長くすることができ、沿面放電を抑制することができる。
　≪第２実施形態≫
　本発明は上述の第１実施形態に限定されるものではなく、本発明の要旨を逸脱しない範囲において種々の変更、改良等が可能である。以下、第２実施形態について説明する。なお、第２実施形態に係る半導体モジュールのうち、第１実施形態に係る半導体モジュールと同様な部分については、同一の符号を付して適宜説明を省略する。
　第２実施形態に係る半導体モジュールは、金属基板１と、金属基板１上に設けられた第１の絶縁基板３ａｘと、金属基板１上に第１の絶縁基板３ａｘと間を空けて設けられた第２の絶縁基板３ｂｘと、第１の絶縁基板３ａｘ上に、側面視して折り曲げ部を有し、上方に向かって延びた第１のリード電極４ａｘと、第２の絶縁基板３ｂｘ上に、側面視して第１のリード電極４ａｘと左右対称となる第２のリード電極４ｂｘと、を備えている。
　また、第２実施形態に係る半導体モジュールは、絶縁基板３上のそれぞれに金属板７が設けられている。そして、金属板７上に半導体素子２やリード電極４が設けられている。金属基板１と金属板７は、互いに金属材料であるため、両者の間に絶縁基板３を挟むことで、絶縁基板３にクラックや剥がれ等が発生するのを抑制することができ、電気的信頼性の優れた半導体モジュール基板および半導体モジュールを提供することができる。
　また、第１のリード電極４ａｘは、第２の絶縁基板３ｂｘから離れた第１の絶縁基板３ａｘの縁に設けられている。また、第２のリード電極４ｂｘは、第１の絶縁基板３ａｘから離れた第２の絶縁基板３ｂｘの縁に設けられている。つまり、リード電極４は、図８または図９に示すように、枠体５で囲まれる領域内において、側面視して枠体５の一方内壁面の近傍に設けられた第１のリード電極４ａｘと、枠体５の他方内壁面の近傍に設けられた第２のリード電極４ｂｘとは、左右対称となるように形成されている。枠体５で囲まれる領域内において、第１のリード電極４ａｘと第２のリード電極４ｂｘとの間の距離を長くすることで、半導体モジュール基板に印加される熱応力の集中を半導体モジュール基板の一端側と他端側の両方に加わるようにすることによって、半導体モジュール基板全体で熱応力を緩和することができ、半導体モジュール基板の製造歩留まりを向上させることができる。また、リード電極４間の距離を長くすることができるので、枠体５で囲まれる領域における空間放電を抑制することができ、電気的信頼性の優れた半導体モジュールを提供することができる。
　また、図８に示すように、第１の絶縁基板３ａｘ上には、側面視して第１のリード電極４ａｘと重なる第３のリード電極４ｃｘおよび第４のリード電極４ｄｘがさらに設けられている場合は、第１の絶縁基板３ａｘ上の両端に位置する、第１のリード電極４ａｘ、第３のリード電極４ｃｘまたは第４のリード電極４ｄｘのいずれか２つのリード電極４が同じ形状に設定されている。つまり、リード電極４は、図９に示すように、枠体５で囲まれる領域内において、枠体５の四隅の近傍に設けられたリード電極４を同じ形状にすることで、半導体モジュール基板に印加される熱応力の集中を半導体モジュール基板の四隅に均等に印加されるようにすることによって、半導体モジュール基板全体で熱応力を効果的に緩和することができ、半導体モジュール基板の製造歩留まりを効果的に向上させることができる。
　また、折り曲げ部は、リード電極４に複数個所設けられている。複数の折り曲げ部は、第１の絶縁基板３ａｘと接する個所と、第１の絶縁基板３ａｘの上面から離れた個所に設けることで、応力緩和機能を効果的に発揮することができる。また、第１の絶縁基板３ａｘの上面から離れた個所に折り曲げ部を設けた場合は、当該折り曲げ部は枠体５の上端の高さ位置よりも低い位置に設けられている。枠体５の上端の高さ位置よりも低い位置にリード電極４の折り曲げ部を設けた場合は、封止樹脂６を枠体５内に充填したときには、リード電極４の折り曲げ部が封止樹脂６内に食い込むことにより、第１の絶縁基板３ａからリード電極４を浮きにくくすることができる。その結果、リード電極４が、第１の絶縁基板３ａに対して剥離しにくくなり、リード電極４と第１の絶縁基板３ａとの接合個所においてにリード電極４が断線しにくく、電気的信頼性に優れた半導体モジュールを実現することができる。
　また、第１のリード電極４ａｘおよび第２のリード電極４ｂｘは、互いに対向して配置されており、第１のリード電極４ａｘおよび第２のリード電極４ｂｘには、両者を結ぶ仮想線に沿った方向に貫通する貫通孔Ｈが設けられている。
　リード電極４に貫通孔Ｈを設けることで、リード電極４に対して、リード電極４と他電極との接続をボルトやナットを貫通して螺子止めを行うことができ、リード電極４の電気的接続を良好に維持することができ、製造歩留まりの優れた半導体モジュール基板を提供することができる。なお、図１０に示すように、リード電極４の貫通孔Ｈは、楕円状の貫通孔Ｈｘや孔Ｈの四隅をＲとした貫通孔Ｈｙとすることができる。また、貫通孔Ｈに代えて、リード電極４に切欠きＮｘ、Ｎｙを形成することができる。

Claims (11)

  1. 　金属基板と、
    前記金属基板上に設けられた第１の絶縁基板と、
    前記金属基板上に前記第１の絶縁基板と間を空けて設けられた第２の絶縁基板と、
    前記第１の絶縁基板上に設けられ、側面視して折り曲げ部を有し、上方に向かって延びた第１のリード電極と、
    前記第２の絶縁基板上に設けられ、側面視して前記第１のリード電極と左右対称となる第２のリード電極と、を備えたことを特徴とする半導体モジュール基板。
  2. 　請求項１に記載の半導体モジュール基板であって、
    前記第１のリード電極は、前記第２の絶縁基板から離れた前記第１の絶縁基板の縁に設けられており、前記第２のリード電極は、前記第１の絶縁基板から離れた前記第２の絶縁基板の縁に設けられていることを特徴とする半導体モジュール基板。
  3. 　請求項１または請求項２に記載の半導体モジュール基板であって、
    前記第１の絶縁基板上には、側面視して前記第１のリード電極と重なる第３のリード電極および第４のリード電極がさらに設けられており、
    前記第１の絶縁基板上の両端に位置する、前記第１のリード電極、前記第３のリード電極および前記第４のリード電極のいずれか２つのリード電極が同じ形状であることを特徴とする半導体モジュール基板。
  4. 　請求項１乃至請求項３のいずれかに記載の半導体モジュール基板であって、
    前記折り曲げ部は、前記第１のリード電極に複数個所設けられていることを特徴とする半導体モジュール基板。
  5. 　請求項４に記載の半導体モジュール基板であって、
    前記複数の折り曲げ部は、前記第１の絶縁基板と接する個所と、前記第１の絶縁基板の上面から離れた個所とに設けられていることを特徴とする半導体モジュール基板。
  6. 　請求項１乃至請求項５のいずれかに記載の半導体モジュール基板であって、
    前記第１のリード電極および前記第２のリード電極は、板体を折り曲げて形成したものであることを特徴とする半導体モジュール基板。
  7. 　請求項１乃至請求項６のいずれかに記載の半導体モジュール基板であって、
    前記第１のリード電極および前記第２のリード電極は、互いに対向して配置されており、前記第１のリード電極および前記第２のリード電極には、両者を結ぶ仮想線に沿った方向に貫通する貫通孔が設けられていることを特徴とする半導体モジュール基板。
  8. 　請求項１乃至請求項７のいずれかに記載の半導体モジュール基板と、
    前記第１の絶縁基板に搭載されるとともに、前記第１のリード電極および前記第２のリード電極に電気的に接続された半導体素子と、
    を備えたことを特徴とする半導体モジュール。
  9. 　請求項８に記載の半導体モジュールであって、
    前記金属基板の上側主面に前記第１の絶縁基板および前記第２の絶縁基板、前記第１のリード電極および前記第２のリード電極、ならびに前記半導体素子を取り囲む枠体が設けられていることを特徴とする半導体モジュール。
  10. 　請求項９に記載の半導体モジュールであって、
    前記枠体で囲まれる領域内には、前記第１の絶縁基板および前記第２の絶縁基板、ならびに前記半導体素子を覆う封止樹脂が設けられていることを特徴とする半導体モジュール。
  11. 　請求項１０に記載の半導体モジュールであって、
    前記第１のリード電極の上部および前記第２のリード電極の上部が、前記封止樹脂から露出していることを特徴とする半導体モジュール。
PCT/JP2011/062092 2010-05-27 2011-05-26 半導体モジュール基板および半導体モジュール WO2011149017A1 (ja)

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JP2017011305A (ja) * 2012-03-01 2017-01-12 三菱電機株式会社 電力用半導体モジュール及び電力変換装置
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