Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K3/00—Apparatus or processes for manufacturing printed circuits
  • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
  • H05K3/42—Plated through-holes or plated via connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/0213—Electrical arrangements not otherwise provided for
  • H05K1/0237—High frequency adaptations
  • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
  • H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K1/00—Printed circuits
  • H05K1/02—Details
  • H05K1/11—Printed elements for providing electric connections to or between printed circuits
  • H05K1/115—Via connections; Lands around holes or via connections
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/07—Electric details
  • H05K2201/0776—Resistance and impedance
  • H05K2201/0792—Means against parasitic impedance; Means against eddy currents
• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
  • H05K2201/09—Shape and layout
  • H05K2201/09009—Substrate related
  • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base
  • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

• the invention relates generally to a circuit board having vias filled with conductive material to interconnect different layers of the circuit board.
• Complex circuit boards can have a number of different layers.
• the layers include signal layers and power/ground layers, where each power/ground layer is a power layer or a ground layer.
• the signal layers are generally interleaved with the power/ground layers, so that no two signal layers are immediately adjacent to one another, and so that no two power/ground layers are immediately adjacent to one another.
• vias extending through the layers and filled with a conductive material can be employed. Each such signal layer is electrically connected to the vias so that the two signal layers become electrically interconnected to one another.
• the invention comprises a circuit board comprising a plurality of layers, comprising a first layer, a second layer below the first layer, and a bottom layer.
• the circuit board comprises a pair of vias filled with a conductive material and extending through the layers.
• the pair of vias has a pair of via stubs.
• the circuit board comprises a first pair of conductive signal paths connected to the pair of vias within the first layer, and a second pair of conductive signal paths connected to the pair of vias within the second layer.
• the pair of via stubs is defined between the second layer and the bottom layer.
• a differential signal having a frequency is to be transmitted between the first pair of conductive signal paths and the second pair of conductive signal paths via the pair of vias.
• Means are provided for increasing the resonant frequency of the via stubs beyond the frequency of the differential signal.
• the means comprise one or more holes extending at least partially through the layers and located between the pair of vias. The holes have a lower dielectric constant than the layers to increase a resonant frequency of the pair of via stubs beyond the frequency of the differential signal.
• the holes extend completely through the layers.
• the holes are not filled with any material, such that ambient air is located within the holes.
• the holes each have a radius smaller than a radius of each via.
• the holes are positioned along a line between center points of the pair of vias.
• the holes comprise a plurality of first holes positioned along a first curve around a first via of the pair of vias, and a plurality of second holes positioned along a second curve around a second via of the pair of vias.
• each via stub is a transmission line antenna having the resonant frequency.
• the circuit board further comprises: a pair of anti-pads concentric to the pair of vias and extending through the layers; a first pair of pads on the first layer and concentric to and in contact with the pair of vias, the first pair of pads connecting the first pair of conductive signal paths to the pair of vias, the first pair of conductive signal paths crossing the pair of anti-pads; and, a second pair of pads on the second layer and concentric to and in contact with the pair of vias, the second pair of pads connecting the second pair of conductive signal paths to the pair of vias, the first pair of conductive signal paths crossing the pair of anti-pads, wherein each pad has a radius smaller than a radius of each anti-pad.
• the plurality of layers comprise a plurality of signal layers and a plurality of power/ground layers, the signal layers interleaved in relation to the power/ground layers such that no two signal layers are immediately adjacent to one another and no two power/ground layers are immediately adjacent to one another, wherein the first layer and the second layer are each one of the signal layers, and wherein each power/ground layer is one of a ground layer and a power layer.
• the invention comprises a method comprising providing a circuit board having a plurality of layers, a pair of vias filled with a conductive material and extending through the layers, a first pair of conductive signal paths, and a second pair of conductive signal paths.
• the layers comprise a first layer, a second layer below the first layer, and a bottom layer.
• the first pair of conductive paths is connected to the pair of vias within the first layer and the second pair of conductive paths is connected to the pair of vias within the second layer.
• the pair of vias has a pair of via stubs defined between the second layer and the bottom layer.
• a differential signal is to be transmitted between the first pair of conductive signal paths and the second pair of conductive signal paths via the pair of vias.
• the method comprises forming one or more holes at least partially through the layers and located between the pair of vias. The holes have a lower dielectric constant than the layers to increase a resonant frequency of the pair of via stubs beyond the frequency of the differential signal.
• forming the holes comprises laser etching the holes.
• the holes extend completely through the layers.
• the holes are not filled with any material, such that ambient air is located within the holes.
• the holes each have a radius smaller than a radius of each via.
• the holes are positioned along a line between center points of the pair of vias.
• the holes comprise a plurality of first holes positioned along a first curve around a first via of the pair of vias, and a plurality of second holes positioned along a second curve around a second via of the pair of vias.
• each via stub is a transmission line antenna having the resonant frequency.
• the invention comprises an electronic device comprising one or more electrical components, and a circuit board of the first aspect on, to, or within which each electrical component is mounted.
• the invention relates to a circuit board having vias filled with conductive material to interconnect different layers of the circuit board, the circuit board having holes with a lower dielectric constant than the layers to increase a resonant frequency of resultant via stubs beyond the frequency of a differential signal transmitted between the different layers.
• FIG. 1 is a diagram of a top view of a circuit board, according to an embodiment of the present invention.
• FIG. 2 is a diagram of a cross-sectional front view of the circuit board of FIG. 1, according to an embodiment of the present invention
• FIG. 3 is a diagram of a cross-sectional top view of the circuit board of FIGs. 1 and 2, according to an embodiment of the present invention
• FIG. 4 is a diagram of a graph depicting how lowering the dielectric constant of a circuit board near vias of the board raises the resonant frequency at which signal attenuation is maximized, according to an embodiment of the present invention
• FIG. 5 is a diagram of a top view of a circuit board, according to another embodiment of the present invention.
• FIG. 6 is a flowchart of a rudimentary method, according to an embodiment of the present invention.
• FIG. 7 is a block diagram of a representative electronic device, according to an embodiment of the present invention.
• two signal layers of a multiple-layer circuit board can be interconnected using vias that extend through the layers and that are filled with a conductive material. Each such layer is electrically connected to the vias so that the two signal layers become electrically interconnected to one another.
• a first signal layer may be the top layer of the circuit board
• a second signal layer may be a layer below the top layer, but above the bottom layer, of the circuit board. Electrically connecting both the first signal layer and the second signal layer to the vias results in these two signal layers becoming electrically interconnected to one another.
• a differential signal having a frequency may be transmitted between signal paths on the first signal layer and signal paths on the second signal layer in this example.
• the frequency at which the differential signal is transmitted is relatively high, such as greater than five gigabits-per-second (Gbps).
• Gbps gigabits-per-second
• a potential problem results from the use of the vias to electrically interconnect the first and the second signal layers.
• the vias extend through all the layers of the circuit board.
• the portions of the vias between the first signal layer and the second signal layer are actively employed to electrically interconnect the first and the second signal layers together.
• the portions of the vias below the second signal layer - i.e., between the second signal layer and the bottom signal layer - are not. These latter portions of the vias are referred to as via stubs.
• the via stubs act as transmission line antennas, and have a resonant frequency.
• the differential signal transmitted between the signal paths on the first signal layer and the signal paths on the second signal layer are greatly attenuated, such as by three-to-ten decibels or more.
• this issue is not much of a problem, because the differential signals are transmitted at frequencies significantly lower than the resonant frequency of the via stubs.
• high-frequency differential signals which are becoming more common as performance specifications are increased, this issue becomes a problem, because the differential signals are transmitted at frequencies near or at the resonant frequency of the via stubs.
• a conventional solution to this problem is to back-drill the circuit board at the vias to bore out the via stubs, so that the via stubs are reduced in length if not completely removed.
• back-drilling typically requires expensive and specialized equipment, and further requires that the back-drill be precisely located over the vias. As such, the back-drilling process is expensive and time-consuming.
• Embodiments of the invention by comparison, approach this problem from a different perspective.
• the resonant frequency of the via stubs is inversely proportional to the dielectric constant of the layers of the circuit board around the vias. Therefore,
• embodiments of the invention lower the dielectric constant, which serves to increase the resonant frequency of the via stubs.
• FIGs. 1, 2, and 3 show a circuit board 100, according to a preferred embodiment of the invention.
• FIG. 1 is a top view of the circuit board 100, and FIG.
• FIG. 2 is a cross-sectional front view of the circuit board 100 at the sectional mark 102 of FIG. 1.
• FIG. 3 is a cross-sectional top view of the circuit board 100 at the sectional mark 124 of FIG. 2.
• the circuit board 100 includes signal layers 104A, 104B, 104C, 104D, and 104E, collectively referred to as the signal layers 104, and power/ground layers 106A, 106B, 106C, and 106D, collectively referred to as the power/ground layers 106.
• signal layers 104A, 104B, 104C, 104D, and 104E collectively referred to as the signal layers 104
• power/ground layers 106A, 106B, 106C, and 106D collectively referred to as the power/ground layers 106.
• the signal layers 104 are interleaved in relation to the power/ ground layers 106. This means that no two signal layers 104 are immediately adjacent to one another, and that no two power/ground layers 106 are immediately adjacent to one another.
• Each signal layer 104 may be connected to one or more electrical components mounted within or on the signal layer 104.
• Each power/ground layer 106 is a ground layer or a power layer. Each ground layer is connected to a relative or absolute ground. Each power layer is connected to the same or different power source.
• Vias 108A and 108B extend completely through the layers 104 and 106 of the circuit board 100.
• the vias 108 are filled with a conductive material.
• pads 110A and HOB collectively referred to as the pads 110
• the pads 110 connect conductive signal paths 114A and 114B, collectively referred to as the conductive signal paths 114, to the vias 108.
• pads 116A and 116B there are pads 116A and 116B, collectively referred to as the pads 116, that are concentric to and in contact with the vias 108.
• the pads 116 connect conductive signal paths 118A and 118B, collectively referred to as the conductive signal paths 118, to the vias 108.
• Anti-pads 112 concentric to the vias 108 and that surround the pads 110 and 116 extend completely through the layers 104 and 106 of the circuit board 100.
• the anti-pads 112 are not filled with any material, such that ambient air is located within the anti-pads 112.
• the anti-pads 112 electrically isolate the vias 108 from the layers 104 and 106 that do not include conductive signal paths, like the conductive signal paths 114 and 118 of the layers 104 A and
• each pad 110 and 116 has a radius smaller than the radius of each anti-pad 112.
• the conductive signal paths 114 and the conductive signal paths 118 are therefore connected to the vias 108.
• a differential signal having a frequency is transmitted between the conductive signal paths 114 of the layer 104 A and the conductive signal paths 118 of the layer 104C using the vias 108.
• 104 A and 104C are actively used to electrically connect the signal paths 114 within the layer 104A to the signal paths 118 within the layer 104C that is below the layer 104A.
• the vias 108 extend through all the layers 104. As such, there are portions of the vias 108, extending from the layer 104C to the bottom layer 104E, which are not actively used to electrically connect the signal paths 114 within the layer 104 A to the signal paths 118 within the layer 104C. These portions of the vias 108 are referred to as via stubs. There are two via stubs, since each via 108 has a via stub; however, just one via stub 122 is depicted and called out in FIG. 2, which is part of the via 108 A. That is, the via stub that is part of the via 108B is not shown in FIG. 2. Nevertheless, the nomenclature "via stubs 122" is used herein to refer to both the visible via stub 122 of the via 108 A in FIG. 2, and the via stub of the via 108B that is not visible within FIG. 2.
• the via stubs 122 are transmission line antennas that have a resonant frequency. At the resonant frequency of the via stubs 122, the differential signal transmitted between the conductive signal paths 114 and 118 is attenuated. To ensure that the differential signal is not so attenuated, the circuit board 100 includes holes 120 extending at least partially through the layers 104 and 106, and that are located between the vias 108. The holes 120 have a lower dielectric constant than the layers 104 and 106. Because the resonant frequency of the via stubs 122 is inversely proportional to the dielectric constant of the layers 104 and 106 around the vias 108, the presence of the holes 120 increases the resonant frequency of the via stubs 122.
• the number and configuration of the holes 120 are specified so that the resonant frequency of the via stubs 122 is raised sufficiently beyond the frequency of the differential signal so that the differential signal is not attenuated.
• Appropriate modeling and simulation software can be used in this respect to determine the number and configuration of the holes 120.
• the holes 120 do not have any purpose within the circuit board 100 other than to decrease the dielectric constant of the layers 104 and 106 around the vias 108, and thus to increase the resonant frequency of the via stubs 122.
• the holes 120 extend completely through the layers 104 and 106, but in general, the holes at least partially extend through the layers 104 and 106.
• the holes 120 have a radius smaller than the radius of each via 108.
• the holes 120 are not filled with any material, such that ambient air is located within the holes 120.
• Ambient air has a lower dielectric constant than generally any material from which the layers 104 and 106 can be suitably fabricated.
• the holes 120 are filled with a material that has a lower dielectric constant than the material from which the layers 104 and 106 are fabricated.
• the holes serve as the means for performing the functionality of increasing the resonant frequency of the via stubs 122 beyond the frequency of the differential signal.
• FIG. 4 shows a graph 400 depicting how the lowering the dielectric constant of the circuit board 100 near the vias 108 raises the resonant frequency of the via stubs 122 at which attenuation of the differential signal being transmitted between the conductive signal paths 114 and 118 occurs, according to an embodiment of the invention.
• the x-axis 402 denotes frequency in hertz (Hz), starts at zero Hz at the left, and increases from left to right, for example to 10 x 10 9 Hz (10 GHz).
• the y-axis 404 denotes gain in decibels (dB), starts at zero decibels at the top, and decreases from top to bottom.
• the curves depicted in the graph 400 represent the gain in dB of the differential signal that results from the vias 108.
• the lowest point of each curve occurs at the resonant frequency of the via stubs 122 of the vias 108. Attenuation of the differential signal is maximized at the resonant frequency of the via stubs, since the gain resulting from the vias 108 is at its lowest at this resonant frequency.
• the dielectric constant of the layers 104 and 106 of the circuit board 100 near the vias 108 is decreased, the resonant frequency of the via stubs 122 increases.
• the resonant frequency of the via stubs 122 can be increased to a frequency beyond the frequency of the differential signal so that attenuation of the differential signal is sufficiently lowered, or minimized, by suitably decreasing the dielectric constant of the circuit board 100 near the vias 108.
• FIG. 5 shows a top view of the circuit board 100, according to another embodiment of the invention.
• the holes 120 are arranged in a different configuration as compared to the holes 120 in FIGs. 1 and 3. Specifically, some holes 120 are positioned along a curve around the via 108A. Other holes 120 are positioned along a curve around the via 108B.
• FIG. 5 thus illustrates that the configuration of the holes 120 can be varied to decrease the dielectric constant of the layers 104 and 106 near the vias 108 to raise the resonant frequency of the via stubs 122 beyond the frequency of the differential signal transmitted between the conductive signal paths 114 and 118.
• FIG. 6 shows a rudimentary method 600 of manufacture, according to an embodiment of the invention.
• the circuit board 100 is provided (602).
• the holes 120 are formed at least partially through the layers 104 and 106 of the circuit board 100 (604).
• laser etching may be employed to form the holes 120 within the circuit board 100.
• back drilling using expensive and specialized equipment, is unnecessary to form the holes 120, in contradistinction to the prior art's boring out the via stubs 122 by such back drilling.
• the holes 120 may subsequently be filled with a material that has a lower dielectric than the material from which the layers 104 and 106 are fabricated. Alternatively, the holes 120 may remain empty, such that atmospheric ambient air is present within the holes 120.
• FIG. 7 is a block diagram of a representative electronic device 700, according to an embodiment of the invention.
• the electronic device 700 includes the circuit board 100 that has been described, as well as one or more electrical components 702.
• Each electrical component 702 is mounted on, to, or within the circuit board 100.
• each electrical component 702 may be mounted on, to, or within one of the layers 104 and 106 of the circuit board 100.
• the electrical components 702 may include resistors, capacitors, inductors, integrated circuits, as well as other types of electrical components.
• the electrical components 702 are interconnected with one another on the circuit board 100 to work in unison to provide the electronic device 700 with an intended or desired functionality.

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• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Manufacturing & Machinery (AREA)
• Production Of Multi-Layered Print Wiring Board (AREA)
• Structure Of Printed Boards (AREA)

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Citations (6)

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• 2010
  • 2010-04-29 US US12/770,691 patent/US8542494B2/en not_active Expired - Fee Related
• 2011
  • 2011-04-21 WO PCT/EP2011/056464 patent/WO2011134902A1/en active Application Filing
  • 2011-04-21 DE DE112011101471T patent/DE112011101471T5/de active Pending
  • 2011-04-21 CN CN201180018633.XA patent/CN102860140B/zh active Active
  • 2011-04-21 GB GB1221450.8A patent/GB2493681B/en active Active
• 2013
  • 2013-05-16 US US13/895,675 patent/US9119334B2/en active Active

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