WO2011127867A2 - 一种多层电路板及其制造方法 - Google Patents

一种多层电路板及其制造方法 Download PDF

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Publication number
WO2011127867A2
WO2011127867A2 PCT/CN2011/074807 CN2011074807W WO2011127867A2 WO 2011127867 A2 WO2011127867 A2 WO 2011127867A2 CN 2011074807 W CN2011074807 W CN 2011074807W WO 2011127867 A2 WO2011127867 A2 WO 2011127867A2
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WO
WIPO (PCT)
Prior art keywords
core
identification
different
circuit board
conductor
Prior art date
Application number
PCT/CN2011/074807
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English (en)
French (fr)
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WO2011127867A3 (zh
Inventor
丁丽
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2011/074807 priority Critical patent/WO2011127867A2/zh
Priority to RU2013100939/07A priority patent/RU2013100939A/ru
Priority to EP11768478.7A priority patent/EP2566306A4/en
Priority to CN2011800016324A priority patent/CN102301837B/zh
Priority to BR112013000765A priority patent/BR112013000765A2/pt
Publication of WO2011127867A2 publication Critical patent/WO2011127867A2/zh
Publication of WO2011127867A3 publication Critical patent/WO2011127867A3/zh
Priority to US13/686,057 priority patent/US9018531B2/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09936—Marks, inscriptions, etc. for information
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Definitions

  • the present invention relates to the field of electronic communication technologies, and in particular, to a multilayer circuit board and a method of fabricating the same.
  • Background Art In the fabrication process of a multilayer circuit board, since the multilayer circuit board includes a plurality of core boards stacked together, in the core board stacking process, especially when the number of core boards is large, stacking order disorder is apt to occur. For example: Originally, core A should be on the first layer and the result on the fifth.
  • the inventors have found that the prior art has at least the following disadvantages: If the stacking order of the two core boards is wrong, the electrical network connection is usually normal, but the impedance or S-parameter of the trace will be affected during transmission. When the signal is present, there will be a signal anomaly and the crosstalk will increase. Summary of the invention
  • Embodiments of the present invention provide a multilayer circuit board and a method of fabricating the same to reduce the error rate of the core board stack.
  • Embodiments of the present invention provide the following aspects:
  • the present invention provides an embodiment of a multilayer circuit board, comprising: a plurality of core boards stacked together, the core board comprising an insulating layer and at least one conductor layer disposed together
  • the conductor layer includes an electric circuit
  • the core board is provided with at least one identification conductor at an edge of the at least one conductor layer, and the identification conductor forms a logo pattern on a side surface of the core board along a stacking direction of the core board,
  • the identification patterns of multiple core boards are different.
  • the present invention also provides a method for fabricating a multilayer circuit board, comprising: processing a plurality of core plates, comprising: fabricating at least one conductor layer on each of the plurality of insulating layers, the guide The body layer includes a circuit located at a middle portion of the conductor layer, and an identification conductor at an edge of the conductor layer, the identification conductor of the core plate forming a logo pattern on a side along a stacking direction of the core board, the plurality of core boards
  • the identification patterns are different; each of the plurality of core boards is identified according to the identification pattern of each of the plurality of core sheets, and each of the identified core boards is pressed The stacking sequence is stacked and pressed into a multilayer board.
  • the identification conductors of the plurality of core plates are along the stacking direction of the core board.
  • Different marking patterns are formed on the side surface.
  • the stacking order can be arranged according to the identification pattern. After the stacking is completed, it is also easy to check whether the order of the core board stacking is wrong according to the identification pattern, and to find and eliminate the wrong stacking materials early, so as to avoid the stacking of the wrong semi-finished products, and proceed to the next step.
  • FIG. 1 is a schematic view of a core board in a multilayer circuit board of the present invention
  • FIG. 2 is a side view of a multilayer circuit board along a stacking direction of a core board according to the present invention
  • FIG. 3 is a side view of another multilayer circuit board along a stacking direction of a core board according to the present invention
  • FIG. 5 is a schematic flow chart of a method for fabricating a multilayer circuit board according to the present invention.
  • the present invention is not limited by the embodiments of the present invention. As shown in FIG.
  • the present invention provides an embodiment of a multilayer circuit board, comprising: a plurality of core boards 1 stacked together, the core board 1 comprising an insulating layer and at least one conductor layer laminated together
  • the conductor layer includes a circuit
  • the core board is provided with at least one identification conductor at an edge of at least one layer of the conductor layer
  • the marking conductor 11 forms a marking pattern on a side surface of the core board along a stacking direction of the core board, and the marking pattern of the plurality of core boards is on a side of the multilayer circuit board along a core board stacking direction Different.
  • the identification conductors of the plurality of core plates form different identification patterns on the side along the stacking direction of the core board, in the multilayer circuit board
  • the stacking order can be arranged according to the identification pattern. After the stacking is completed, it is also easy to check whether the order of the core board stacking is wrong according to the logo pattern, and to find and eliminate the wrong stacking materials early, so as to avoid the semi-finished products with the wrong core stack stacking, and proceed to the next process.
  • the multi-layer circuit board is completed, during the inspection of the finished product, it is possible to check whether the order of the core board stacking is in error according to the logo pattern, and to find and reject the unqualified multi-layer circuit board early.
  • the marking conductor is simple in structure, and it is only necessary to arrange the marking conductor at the edge of the conductor layer when the conductor layer is arranged for the core board, and the processing procedure of the multilayer circuit board is not increased, and the processing is simple and convenient.
  • the core board may include an insulating layer and a conductor layer which are attached together, or an insulating layer and two conductor layers which are laminated together, the insulating layer Located between the two layers of conductor layers.
  • the identification pattern is a pattern of the identification conductors on a side of the core board along a stacking direction of the core sheets.
  • at least one identification conductor may be disposed at an edge position of one side of at least one conductor layer of the core board, such that one side of the multilayer circuit board along the stacking direction of the core board A plurality of logo graphics are formed.
  • the identification conductor may be disposed at an edge position of the plurality of side edges of the at least one conductor layer of the core board, such that the plurality of circuit boards are along the stacking direction of the core board.
  • the logo is formed on the side.
  • the identification conductor is formed with a logo pattern on a plurality of sides of the core board along the core board stacking direction.
  • the plurality of identification patterns formed by the same core sheets on a plurality of sides along the stacking direction of the core sheets may be different, so as to distinguish the respective side edges of the core sheets when the core sheets are stacked.
  • the identification conductors of the plurality of core plates constituting a multilayer circuit board may be located on different sides. Thus, the plurality of sides of the multilayer circuit board along the core stacking direction have identification patterns.
  • the identification pattern of the partial core board is located on one side of the multilayer circuit board, and the identification pattern of the other part of the core board is located on the other side of the multilayer circuit board.
  • the length of the identification conductor may be determined according to the ratio of the length of the core plate to the width of the plate, for example, may be greater than or equal to 2 mm. If the core board is detected by the naked eye for stacking errors, the length of the marking conductor can be recognized by the naked eye as a minimum requirement. If the test is performed by the test equipment, the test device can recognize that the identification conductor is the minimum requirement.
  • the identification conductor may have a width of 5 to 10 mils or even less.
  • the principle is not to obstruct the circuit arrangement of the intermediate portion of the conductor layer.
  • the marking conductor may be a copper skin, the copper skin may be a non-functional copper skin, and the non-functional copper skin means a copper skin without a circuit.
  • the identification patterns of the plurality of core plates are different, and can be implemented as follows: the color of the identification patterns located on different core boards is different; or
  • the number of logo patterns located on different core boards is different; or The identification patterns of the different core boards are different in length from the ends of the side edges; or the identification patterns on the different core boards are located at: different sides of the multilayer circuit board along the stacking direction of the core sheets.
  • the number of the identification patterns of the core boards located in the different layers may be different. As shown in FIG. 2 or 3, the number of the identification conductors of the core board is according to the core board in the multilayer circuit. The number of layers of the board is set. For example: If the core board A is located on the fifth layer starting from the top core board of the multilayer circuit board, the core board A can be provided with five identification conductors.
  • the identification patterns of each layer of core sheets are unequal in size.
  • the identification patterns of each layer of core sheets are substantially equal.
  • the implementation manners of the identification patterns of the core boards of the different layers being different from the lengths of the ends of the side edges may be: as shown in FIG. 4, the identification patterns of the plurality of core boards stacked together are on the multi-layer circuit board On the side of the core, a diagonal line is formed. During the process of stacking the core plates, it can be easily judged whether the stacking order of the core plates is wrong.
  • the multilayer circuit board may be a backplane, or a single board or the like.
  • the present invention further provides an embodiment of a method for fabricating a multilayer circuit board, including: Step 101: processing a plurality of core boards, comprising: fabricating at least one conductor layer on each of the plurality of insulating layers, The conductor layer includes a circuit located at a middle portion of the conductor layer, and an identification conductor at an edge of the conductor layer, the identification conductor of the core plate forming a logo pattern on a side along a stacking direction of the core board, the plurality of core boards The logo graphics are different.
  • Step 102 Identify each of the plurality of core boards according to an identification pattern of each of the plurality of core boards, and perform each of the identified core boards in a stacking order Stacked, laminated to a multilayer board.
  • - g - in the embodiment of the invention by arranging the identification conductors at the edges of the conductor layers, the identification conductors of the plurality of core plates form different identification patterns on the sides along the stacking direction of the core sheets, In the manufacturing process of a multilayer circuit board, for example: During the inner layer processing stage, when stacking the core boards, the stacking order can be arranged according to the identification pattern.
  • the multi-layer circuit board is completed, during the inspection of the finished product, it is possible to check whether the order of the core board stacking is in error according to the logo pattern, and to find and reject the unqualified multi-layer circuit board early.
  • the marking conductor is simple in structure, and it is only necessary to arrange the marking conductor at the edge of the conductor layer when the conductor layer is arranged for the core board, and the processing procedure of the multilayer circuit board is not increased, and the processing is simple and convenient.
  • the stacking sequence may be a stacking sequence in which the plurality of core boards are predetermined according to the function and circuit connection relationship of each core board.
  • the length of the identification conductor may be determined according to the ratio of the length of the core plate to the width of the plate, for example, may be greater than or equal to 2 mm. If the core board is detected by the naked eye for stacking errors, the length of the marking conductor can be recognized by the naked eye as a minimum requirement. If the test is performed by the test equipment, the test equipment can recognize that the identification conductor is the minimum requirement.
  • the identification conductor may have a width of 5 to 10 mils or even less. It is based on the principle that the circuit arrangement in the middle of the conductor layer is not hindered.
  • the marking conductor may be a copper skin, the copper skin may be a non-functional copper skin, and the non-functional copper skin means a copper skin without a circuit.
  • the identification patterns of the plurality of core plates are different, and can be implemented as follows: the color of the identification patterns located on different core boards is different; or
  • the number of identification patterns on different core boards is different; or the identification patterns on different core boards are different in length from the end of the side; or The identification patterns on the different core boards are located at: different sides of the multilayer circuit board in the direction in which the core sheets are stacked.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

提供了一种多层电路板。所述多层电路板包括：堆叠在一起的多个芯板（1），所述芯板（1）包括贴置在一起的绝缘层和至少一层导体层，所述导体层包括电路，所述芯板（1）在至少一层导体层的边缘设置有至少一个标识导体（11），所述标识导体（11）在所述芯板（1）沿着芯板堆叠方向的侧面形成标识图形，所述多个芯板（1）的标识图形在所述多层电路板沿着芯板堆叠方向的侧面上各不相同。还提供了一种多层电路板的制作方法。

Description

...1... 一种多层电路板及其制造方法 技术领域 本发明涉及电子通信技术领域， 尤其涉及一种多层电路板以及制造方法。 背景技术 在多层电路板的制作过程中， 由于多层电路板包括有多层堆叠在一起的 芯板， 在芯板堆叠过程中， 尤其是芯板的数量较多时， 容易出现堆叠顺序错 乱。 例如： 本来芯板 A应该在第 1层， 结果放在了第 5层。 发明人在实现本发明的过程中， 发现现有技术至少存在以下缺点： 如果 两个芯板堆叠顺序出错， 电网络连接通常是正常的， 但走线的阻抗或 S参数 会受到影响， 在传输信号时， 会出现信号异常， 串扰加大的现象。 发明内容
本发明的实施例提供了一种多层电路板及其制造方法， 以降低芯板 堆叠的出错率。 本发明实施例提供如下方案： 本发明提供一种多层电路板的实施例， 包括： 堆叠在一起的多个芯板， 所述芯板包括贴置在一起的绝缘层和至少一层导体层， 所述导体层包括电路， 所述芯板在至少一层导体层的边缘设置有至少一个标识导体， 所述标识导体 在所述芯板沿着芯板堆叠方向的侧面形成标识图形， 所述多个芯板的标识图 形各不相同。 本发明还提供一种多层电路板制作方法， 包括： 加工多个芯板， 包括： 在多个绝缘层上面分别制作至少一个导体层， 所述导 体层包括位于导体层中部的电路， 以及位于导体层边缘的标识导体， 所述芯 板的标识导体在沿着所述芯板的堆叠方向的侧面上形成标识图形， 所述多个 芯板的标识图形各不相同； 根据所述多个芯板中的每个芯板的标识图形， 对所述多个芯板中的每个芯板 进行识别， 将所述识别出的每个芯板按堆叠顺序进行堆叠， 压合为多层电路 板。
由上述本发明的实施例提供的技术方案可以看出， 在本发明的实施例中， 通 过在导体层的边缘布置标识导体， 多个所述芯板的标识导体在沿着芯板堆叠 方向的侧面上形成各不相同的标识图形， 在多层电路板的制作过程中， 例如： 在内层加工过程阶段， 在堆叠芯板时， 可以根据标识图形安排堆叠顺序。 在 堆叠完成后， 也很容易根据标识图形， 检查芯板堆叠的顺序是否出错， 及早 发现和剔除堆叠错误的物料， 以避免芯板堆叠错误的半成品， 进入下一道工 序。 附图说明 为了更清楚地说明本发明实施例的技术方案， 下面将对实施例描述中所 需要使用的附图作简单地介绍， 显而易见地， 下面描述中的附图仅仅是本发 明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动性的 前提下， 还可以根据这些附图获得其他的附图。
图 1为本发明一种多层电路板中的芯板示意图；
图 2为本发明一种多层电路板的沿着芯板堆叠方向的侧面示意图； 图 3为本发明另一种多层电路板的沿着芯板堆叠方向的侧面示意图； 图 4为本发明再一种多层电路板的沿着芯板堆叠方向的侧面示意图； 图 5为本发明一种多层电路板制作方法的流程示意图。 "' Q" 具体实施方式 为便于对本发明实施例的理解， 下面将结合附图以几个具体实施例为例 做进一步的解释说明， 且各个实施例并不构成对本发明实施例的限定。 如图 1所示， 本发明提供一种多层电路板的实施例， 包括： 堆叠在一起的 多个芯板 1， 所述芯板 1包括贴置在一起的绝缘层和至少一层导体层， 所述导 体层包括电路， 所述芯板在至少一层导体层的边缘设置有至少一个标识导体
11， 所述标识导体 1 1在所述芯板沿着芯板堆叠方向的侧面形成标识图形， 所 述多个芯板的标识图形在所述多层电路板沿着芯板堆叠方向的侧面上各不相 同。
在本发明的实施例中， 通过在导体层的边缘布置标识导体， 多个所述芯 板的标识导体在沿着芯板堆叠方向的侧面上形成各不相同的标识图形， 在多 层电路板的制作过程中， 例如： 在内层加工过程阶段， 在堆叠芯板时， 可以 根据标识图形安排堆叠顺序。 在堆叠完成后， 也很容易根据标识图形， 检查 芯板堆叠的顺序是否出错， 及早发现和剔除堆叠错误的物料， 以避免芯板堆 叠错误的半成品， 进入下一道工序。
进一步地， 在多层电路板制作完成后， 在成品检查过程中， 可以根据标识 图形检查芯板堆叠的顺序是否出错， 及早发现和剔除不合格的多层电路板。
更进一步地，采用的标识导体， 结构简单，仅需要在为芯板布置导体层时， 在导体层的边缘布置标识导体， 不增加多层电路板的加工工序， 加工起来简 单方便。
在本发明的实施例中， 所述芯板可以包括贴置在一起的一层绝缘层和一层 导体层， 或者包括贴置在一起的一层绝缘层和两层导体层， 所述绝缘层位于 所述两层导体层之间。
在本发明的实施例中， 所述标识图形为所述标识导体在所述芯板沿着芯板 堆叠方向的侧面所呈现出来的图形。 在本发明的实施例中， 可以在所述芯板的至少一个导体层的一个侧边的边 缘位置设置至少一个标识导体， 这样， 在所述多层电路板沿着芯板堆叠方向 的一个侧面形成多个标识图形。 在本发明的实施例中， 也可以在所述芯板的至少一个导体层的多个侧边 的边缘位置设置标识导体， 这样， 在所述多层电路板沿着芯板堆叠方向的多 个侧面形成标识图形。 在所述芯板的导体层的多个侧边的边缘位置设置标识 导体的情况下， 所述标识导体在所述芯板沿着芯板堆叠方向的多个侧面形成 有标识图形。 同一芯板在沿着芯板堆叠方向的多个侧面形成的多个标识图形 可以各不相同， 以便于在堆叠芯板时， 区分芯板的各个侧边。 在本发明的实施例中， 组成一个多层电路板的多个芯板设置的标识导 体， 可以位于不同的侧边。 这样， 在所述多层电路板沿着芯板堆叠方向的多 个侧面具有标识图形。 部分芯板的标识图形位于多层电路板的一个侧面， 另 一部分芯板的标识图形位于所述多层电路板的其他侧面。 在本发明的实施例中， 所述标识导体的长度可以根据芯板的板长与板宽 的比例而定， 例如可以大于或等于 2mm。 如果采用肉眼检测芯板是否堆叠错 误， 所述标识导体的长度可以以肉眼可以识别出为最低要求。 如果由测试设 备进行检测， 则以测试设备能够识别出所述标识导体为最低要求。 所述标识导体的宽度可以为 5 ~ 10mil， 甚至更小。 以不妨碍导体层中间 部位的电路布置为原则。 所述标识导体可以为铜皮， 所述铜皮可以为无功能铜皮， 无功能铜皮是 指， 不设置电路的铜皮。 所述多个芯板的标识图形各不相同， 可以采用如下方式实现： 位于不同芯板的标识图形的颜色不同； 或者
位于不同芯板的标识图形的个数不同； 或者 位于不同芯板的标识图形距离所在侧边的末端的长度不同； 或者 位于不同芯板的标识图形位于： 所述多层电路板沿芯板堆叠方向上的不 同的侧面。 位于不同层的芯板的标识图形的个数不同的实现方式可以为： 如图 2或 3所示， 所述芯板的所述标识导体的个数根据所述芯板在所述多 层电路板的层数设置。 例如： 如果从多层电路板顶层芯板开始数， 芯板 A位于 第五层， 则芯板 A设置的标识导体可以设置 5个。 这样在芯板堆叠完成后， 可 以根据每层芯板上标识导体的个数， 更清楚的判断芯板的堆叠顺序有没有错， 如果发现错了， 还可以准确的判断是哪一层错了。 在图 2中， 每层芯板的标识 图形大小不等， 在图 3中， 每层芯板的标识图形大致相等。 位于不同层的芯板的标识图形距离所在侧边的末端的长度不同的实现方式 可以为： 如图 4所示， 所述堆叠在一起的多个芯板的标识图形在所述多层电路板的侧 面上组成一条斜线， 在堆叠芯板的过程中， 可以很容易判断芯板的堆叠顺序 是否出错。 在本发明的实施例中， 所述多层电路板可以为背板， 或者单板等等。
如图 5所示， 本发明还提供一种多层电路板制作方法的实施例， 包括： 步骤 101，加工多个芯板， 包括：在多个绝缘层上面分别制作至少一个导体层， 所述导体层包括位于导体层中部的电路， 以及位于导体层边缘的标识导体， 所述芯板的标识导体在沿着所述芯板的堆叠方向的侧面上形成标识图形， 所 述多个芯板的标识图形各不相同。 步骤 102， 根据所述多个芯板中的每个芯板的标识图形， 对所述多个芯板中的 每个芯板进行识别， 将所述识别出的每个芯板按堆叠顺序进行堆叠， 压合为 多层电路板。 —— g—— 在本发明的实施例中， 通过在导体层的边缘布置标识导体， 多个所述芯板 的标识导体在沿着芯板堆叠方向的侧面上形成各不相同的标识图形， 在多层 电路板的制作过程中， 例如： 在内层加工过程阶段， 在堆叠芯板时， 可以根 据标识图形安排堆叠顺序。 在堆叠完成后， 也很容易根据标识图形， 检查芯 板堆叠的顺序是否出错， 及早发现和剔除堆叠错误的物料， 以避免芯板堆叠 错误的半成品， 进入下一道工序。
进一步地， 在多层电路板制作完成后， 在成品检查过程中， 可以根据标识 图形检查芯板堆叠的顺序是否出错， 及早发现和剔除不合格的多层电路板。
更进一步地，采用的标识导体， 结构简单，仅需要在为芯板布置导体层时， 在导体层的边缘布置标识导体， 不增加多层电路板的加工工序， 加工起来简 单方便。
在本发明的实施例中， 所述堆叠顺序， 可以为所述多个芯板按照每个芯板 的功能及电路连接关系预先确定的堆叠顺序。
在本发明的实施例中， 所述标识导体的长度可以根据芯板的板长与板宽的 比例而定， 例如可以大于或等于 2mm。如果采用肉眼检测芯板是否堆叠错误， 所述标识导体的长度可以以肉眼可以识别出为最低要求。 如果由测试设备进 行检测， 则以测试设备能够识别出所述标识导体为最低要求。 所述标识导体的宽度可以为 5 ~ 10mil， 甚至更小。 以不妨碍导体层中间 部位的电路布置为原则。 所述标识导体可以为铜皮， 所述铜皮可以为无功能铜皮， 无功能铜皮是 指， 不设置电路的铜皮。 所述多个芯板的标识图形各不相同， 可以采用如下方式实现： 位于不同芯板的标识图形的颜色不同； 或者
位于不同芯板的标识图形的个数不同； 或者 位于不同芯板的标识图形距离所在侧边的末端的长度不同； 或者 位于不同芯板的标识图形位于： 所述多层电路板沿芯板堆叠方向上的不 同的侧面。
以上所述， 仅为本发明较佳的具体实施方式， 但本发明的保护范围并不 局限于此， 任何熟悉本技术领域的技术人员在本发明揭露的技术范围内， 可 轻易想到的变化或替换， 都应涵盖在本发明的保护范围之内。 因此， 本发明 的保护范围应该以权利要求的保护范围为准。

Claims

O 权利 要求 书
1、 一种多层电路板， 其特征在于， 所述多层电路板包括： 堆叠在一起的 多个芯板， 所述芯板包括贴置在一起的绝缘层和至少一层导体层， 所述导体层 包括电路， 所述芯板在至少一层导体层的边缘设置有至少一个标识导体， 所述 标识导体在所述芯板沿着芯板堆叠方向的侧面形成标识图形， 所述多个芯板的 标识图形在所述多层电路板沿着芯板堆叠方向的侧面上各不相同。
2、 如权利要求 1所述的多层电路板， 其特征在于， 所述标识导体的长度 大于或等于 2mm。
3、 如权利要求 1 所述的多层电路板， 其特征在于， 所述标识导体的宽度 为 5 ~ 10mil。
4、 如权利要求 1所述的多层电路板， 其特征在于， 所述标识导体为无功能 铜皮。
5、 如权利要求 1所述的多层电路板， 其特征在于， 所述多个芯板的标识图 形各不相同， 可以采用如下方式实现：
位于不同芯板的标识图形的颜色不同； 或者
位于不同芯板的标识图形的个数不同； 或者 位于不同芯板的标识图形距离所在侧边的末端的长度不同； 或者 位于不同芯板的标识图形位于： 所述多层电路板沿芯板堆叠方向上的不同 的侧面。
6、 一种多层电路板的制作方法， 其特征在于， 所述方法包括：
加工多个芯板， 包括： 在多个绝缘层上面分别制作至少一个导体层， 所述 导体层包括位于导体层中部的电路， 以及位于导体层边缘的标识导体， 所述芯 板的标识导体在沿着所述芯板的堆叠方向的侧面上形成标识图形， 所述多个芯 板的标识图形各不相同； 根据所述多个芯板中的每个芯板的标识图形， 对所述多个芯板中的每个芯 板进行识别， 将所述识别出的每个芯板按堆叠顺序进行堆叠， 压合为多层电路 板。
7、 如权利要求 6所述的多层电路板， 其特征在于， 所述标识导体的长度 大于或等于 2mm。
8、 如权利要求 6所述的多层电路板， 其特征在于， 所述标识导体的宽度 为 5 ~ 10mil。
9、 如权利要求 6所述的多层电路板， 其特征在于， 所述标识导体为无功能 铜皮。
10、 如权利要求 6所述的多层电路板， 其特征在于， 所述所述多个芯板的标 识图形各不相同， 包括： 位于不同芯板的标识图形的颜色不同； 或者
位于不同芯板的标识图形的个数不同； 或者 位于不同芯板的标识图形距离所在侧边的末端的长度不同； 或者
位于不同芯板的标识图形位于： 所述多层电路板沿芯板堆叠方向上的不同 的侧面。
PCT/CN2011/074807 2011-05-27 2011-05-27 一种多层电路板及其制造方法 WO2011127867A2 (zh)

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