BR112013000765A2 - painel de circuito de múltiplas camadas e método de fabricação do mesmo - Google Patents

painel de circuito de múltiplas camadas e método de fabricação do mesmo

Info

Publication number
BR112013000765A2
BR112013000765A2 BR112013000765A BR112013000765A BR112013000765A2 BR 112013000765 A2 BR112013000765 A2 BR 112013000765A2 BR 112013000765 A BR112013000765 A BR 112013000765A BR 112013000765 A BR112013000765 A BR 112013000765A BR 112013000765 A2 BR112013000765 A2 BR 112013000765A2
Authority
BR
Brazil
Prior art keywords
multilayer circuit
core
panel
identification
circuit board
Prior art date
Application number
BR112013000765A
Other languages
English (en)
Inventor
Ding Li
Original Assignee
Huawei Tech Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Tech Co Ltd filed Critical Huawei Tech Co Ltd
Publication of BR112013000765A2 publication Critical patent/BR112013000765A2/pt

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4638—Aligning and fixing the circuit boards before lamination; Detecting or measuring the misalignment after lamination; Aligning external circuit patterns or via connections relative to internal circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09936—Marks, inscriptions, etc. for information
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

painel de circuito de múltiplas camadas e método de fabricação do mesmo. é fornecido um painel de circuito de múltiplas camadas, que inclui múltiplos painéis de núcleo (1) empilhados juntos. o painel de núcleo (1) inclui uma camada de isololamento e pelo menos uma camada de condutor fixada junta. a camada de condutor inclui um circuito. o painel de núcleo (1) tem pelo menos um condutor de identificação (11) disposto em uma borda de pelo menos uma camada de condutor. o condutor de identificação (11) forma um padrão de identificação em uma superfície lateral do painel de núcleo (1) ap longo de uma direção de empilhar dos painéis de núcleo. os padrões de identificação dos múltiplos painéis de núcleo (1) são diferentes entre si na superfície lateral do painel de circuito de múltiplas camadas ao longo da direção de empilhar dos painéis de núcleo. é fornecido ainda um método de fabricação do painel de circuito de múltiplas camadas.
BR112013000765A 2011-05-27 2011-05-27 painel de circuito de múltiplas camadas e método de fabricação do mesmo BR112013000765A2 (pt)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2011/074807 WO2011127867A2 (zh) 2011-05-27 2011-05-27 一种多层电路板及其制造方法

Publications (1)

Publication Number Publication Date
BR112013000765A2 true BR112013000765A2 (pt) 2017-06-06

Family

ID=44799084

Family Applications (1)

Application Number Title Priority Date Filing Date
BR112013000765A BR112013000765A2 (pt) 2011-05-27 2011-05-27 painel de circuito de múltiplas camadas e método de fabricação do mesmo

Country Status (6)

Country Link
US (1) US9018531B2 (pt)
EP (1) EP2566306A4 (pt)
CN (1) CN102301837B (pt)
BR (1) BR112013000765A2 (pt)
RU (1) RU2013100939A (pt)
WO (1) WO2011127867A2 (pt)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104427748A (zh) * 2013-09-03 2015-03-18 北大方正集团有限公司 印刷电路板叠层错误检测方法、检测模块及印刷电路板
CN107041063B (zh) * 2017-06-09 2019-05-03 东莞市威力固电路板设备有限公司 一种多层pcb的加工方法及多层pcb
CN108260305A (zh) * 2018-01-11 2018-07-06 郑州云海信息技术有限公司 一种pcb板自动叠板棕化方法
CN108959995B (zh) * 2018-08-17 2022-10-14 张家港康得新光电材料有限公司 一种基板信息管理方法、装置、电子设备及存储介质
CN109451679B (zh) * 2018-11-22 2021-03-05 奥士康科技股份有限公司 一种多层pcb板叠放方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4536239A (en) * 1983-07-18 1985-08-20 Nicolet Instrument Corporation Multi-layer circuit board inspection system
US5010449A (en) * 1990-04-04 1991-04-23 Eastman Kodak Company Multi-layer printed circuit board and a method for assuring assembly in a selected order
US5266380A (en) * 1992-09-08 1993-11-30 Motorola, Inc. Method and apparatus for visual verification of proper assembly and alignment of layers in a multi-layer printed circuit board
US6091026A (en) * 1996-11-30 2000-07-18 Samsung Electro-Mechanics Co. Ltd. Multi-layer printed circuit board with human detectable layer misregistration, and manufacturing method therefor
CN2582331Y (zh) * 2002-10-24 2003-10-22 倚天资讯股份有限公司 可验证叠层顺序的电路板
CN2587131Y (zh) * 2002-10-25 2003-11-19 楠梓电子股份有限公司 多层印刷电路板的对准度及涨缩程度的量测构造
JP2004214472A (ja) * 2003-01-07 2004-07-29 Toppan Printing Co Ltd プリント配線板及びその識別方法
JP2006202978A (ja) * 2005-01-20 2006-08-03 Sharp Corp プリント配線基板およびプリント配線基板の識別方法
CN100490603C (zh) * 2005-09-30 2009-05-20 环隆电气股份有限公司 可验证叠层顺序的电路板
JP2009089223A (ja) * 2007-10-02 2009-04-23 Mitsubishi Electric Corp 積層構造体
US20090211785A1 (en) * 2008-02-21 2009-08-27 Lovskog J Thomas Printed circuit board with edge markings

Also Published As

Publication number Publication date
EP2566306A4 (en) 2013-07-03
US20130081859A1 (en) 2013-04-04
CN102301837A (zh) 2011-12-28
US9018531B2 (en) 2015-04-28
EP2566306A2 (en) 2013-03-06
WO2011127867A2 (zh) 2011-10-20
WO2011127867A3 (zh) 2012-05-03
CN102301837B (zh) 2013-03-20
RU2013100939A (ru) 2014-07-20

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Legal Events

Date Code Title Description
B06F Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]
B06T Formal requirements before examination [chapter 6.20 patent gazette]
B07A Application suspended after technical examination (opinion) [chapter 7.1 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]
B09B Patent application refused [chapter 9.2 patent gazette]

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